#ifndef A5XX_XML #define A5XX_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/a5xx.xml ( 151703 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml ( 15485 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml ( 85907 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif enum a5xx_color_fmt { … }; enum a5xx_tile_mode { … }; enum a5xx_vtx_fmt { … }; enum a5xx_tex_fmt { … }; enum a5xx_depth_format { … }; enum a5xx_blit_buf { … }; enum a5xx_cp_perfcounter_select { … }; enum a5xx_rbbm_perfcounter_select { … }; enum a5xx_pc_perfcounter_select { … }; enum a5xx_vfd_perfcounter_select { … }; enum a5xx_hlsq_perfcounter_select { … }; enum a5xx_vpc_perfcounter_select { … }; enum a5xx_tse_perfcounter_select { … }; enum a5xx_ras_perfcounter_select { … }; enum a5xx_lrz_perfcounter_select { … }; enum a5xx_uche_perfcounter_select { … }; enum a5xx_tp_perfcounter_select { … }; enum a5xx_sp_perfcounter_select { … }; enum a5xx_rb_perfcounter_select { … }; enum a5xx_rb_samples_perfcounter_select { … }; enum a5xx_vsc_perfcounter_select { … }; enum a5xx_ccu_perfcounter_select { … }; enum a5xx_cmp_perfcounter_select { … }; enum a5xx_vbif_perfcounter_select { … }; enum a5xx_tex_filter { … }; enum a5xx_tex_clamp { … }; enum a5xx_tex_aniso { … }; enum a5xx_tex_swiz { … }; enum a5xx_tex_type { … }; #define A5XX_INT0_RBBM_GPU_IDLE … #define A5XX_INT0_RBBM_AHB_ERROR … #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT … #define A5XX_INT0_RBBM_ME_MS_TIMEOUT … #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT … #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT … #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW … #define A5XX_INT0_RBBM_GPC_ERROR … #define A5XX_INT0_CP_SW … #define A5XX_INT0_CP_HW_ERROR … #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS … #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS … #define A5XX_INT0_CP_CCU_RESOLVE_TS … #define A5XX_INT0_CP_IB2 … #define A5XX_INT0_CP_IB1 … #define A5XX_INT0_CP_RB … #define A5XX_INT0_CP_UNUSED_1 … #define A5XX_INT0_CP_RB_DONE_TS … #define A5XX_INT0_CP_WT_DONE_TS … #define A5XX_INT0_UNKNOWN_1 … #define A5XX_INT0_CP_CACHE_FLUSH_TS … #define A5XX_INT0_UNUSED_2 … #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW … #define A5XX_INT0_MISC_HANG_DETECT … #define A5XX_INT0_UCHE_OOB_ACCESS … #define A5XX_INT0_UCHE_TRAP_INTR … #define A5XX_INT0_DEBBUS_INTR_0 … #define A5XX_INT0_DEBBUS_INTR_1 … #define A5XX_INT0_GPMU_VOLTAGE_DROOP … #define A5XX_INT0_GPMU_FIRMWARE … #define A5XX_INT0_ISDB_CPU_IRQ … #define A5XX_INT0_ISDB_UNDER_DEBUG … #define A5XX_CP_INT_CP_OPCODE_ERROR … #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR … #define A5XX_CP_INT_CP_HW_FAULT_ERROR … #define A5XX_CP_INT_CP_DMA_ERROR … #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR … #define A5XX_CP_INT_CP_AHB_ERROR … #define REG_A5XX_CP_RB_BASE … #define REG_A5XX_CP_RB_BASE_HI … #define REG_A5XX_CP_RB_CNTL … #define REG_A5XX_CP_RB_RPTR_ADDR … #define REG_A5XX_CP_RB_RPTR_ADDR_HI … #define REG_A5XX_CP_RB_RPTR … #define REG_A5XX_CP_RB_WPTR … #define REG_A5XX_CP_PFP_STAT_ADDR … #define REG_A5XX_CP_PFP_STAT_DATA … #define REG_A5XX_CP_DRAW_STATE_ADDR … #define REG_A5XX_CP_DRAW_STATE_DATA … #define REG_A5XX_CP_ME_NRT_ADDR_LO … #define REG_A5XX_CP_ME_NRT_ADDR_HI … #define REG_A5XX_CP_ME_NRT_DATA … #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO … #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI … #define REG_A5XX_CP_CRASH_DUMP_CNTL … #define REG_A5XX_CP_ME_STAT_ADDR … #define REG_A5XX_CP_ROQ_THRESHOLDS_1 … #define REG_A5XX_CP_ROQ_THRESHOLDS_2 … #define REG_A5XX_CP_ROQ_DBG_ADDR … #define REG_A5XX_CP_ROQ_DBG_DATA … #define REG_A5XX_CP_MEQ_DBG_ADDR … #define REG_A5XX_CP_MEQ_DBG_DATA … #define REG_A5XX_CP_MEQ_THRESHOLDS … #define REG_A5XX_CP_MERCIU_SIZE … #define REG_A5XX_CP_MERCIU_DBG_ADDR … #define REG_A5XX_CP_MERCIU_DBG_DATA_1 … #define REG_A5XX_CP_MERCIU_DBG_DATA_2 … #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR … #define REG_A5XX_CP_PFP_UCODE_DBG_DATA … #define REG_A5XX_CP_ME_UCODE_DBG_ADDR … #define REG_A5XX_CP_ME_UCODE_DBG_DATA … #define REG_A5XX_CP_CNTL … #define REG_A5XX_CP_PFP_ME_CNTL … #define REG_A5XX_CP_CHICKEN_DBG … #define REG_A5XX_CP_PFP_INSTR_BASE_LO … #define REG_A5XX_CP_PFP_INSTR_BASE_HI … #define REG_A5XX_CP_ME_INSTR_BASE_LO … #define REG_A5XX_CP_ME_INSTR_BASE_HI … #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL … #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO … #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI … #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO … #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI … #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO … #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI … #define REG_A5XX_CP_ADDR_MODE_CNTL … #define REG_A5XX_CP_ME_STAT_DATA … #define REG_A5XX_CP_WFI_PEND_CTR … #define REG_A5XX_CP_INTERRUPT_STATUS … #define REG_A5XX_CP_HW_FAULT … #define REG_A5XX_CP_PROTECT_STATUS … #define REG_A5XX_CP_IB1_BASE … #define REG_A5XX_CP_IB1_BASE_HI … #define REG_A5XX_CP_IB1_BUFSZ … #define REG_A5XX_CP_IB2_BASE … #define REG_A5XX_CP_IB2_BASE_HI … #define REG_A5XX_CP_IB2_BUFSZ … #define REG_A5XX_CP_SCRATCH(i0) … static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { … } #define REG_A5XX_CP_PROTECT(i0) … static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { … } #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK … #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT … static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) { … } #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK … #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT … static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) { … } #define A5XX_CP_PROTECT_REG_TRAP_WRITE … #define A5XX_CP_PROTECT_REG_TRAP_READ … #define REG_A5XX_CP_PROTECT_CNTL … #define REG_A5XX_CP_AHB_FAULT … #define REG_A5XX_CP_PERFCTR_CP_SEL_0 … #define REG_A5XX_CP_PERFCTR_CP_SEL_1 … #define REG_A5XX_CP_PERFCTR_CP_SEL_2 … #define REG_A5XX_CP_PERFCTR_CP_SEL_3 … #define REG_A5XX_CP_PERFCTR_CP_SEL_4 … #define REG_A5XX_CP_PERFCTR_CP_SEL_5 … #define REG_A5XX_CP_PERFCTR_CP_SEL_6 … #define REG_A5XX_CP_PERFCTR_CP_SEL_7 … #define REG_A5XX_VSC_ADDR_MODE_CNTL … #define REG_A5XX_CP_POWERCTR_CP_SEL_0 … #define REG_A5XX_CP_POWERCTR_CP_SEL_1 … #define REG_A5XX_CP_POWERCTR_CP_SEL_2 … #define REG_A5XX_CP_POWERCTR_CP_SEL_3 … #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A … #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B … #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C … #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D … #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT … #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM … #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT … #define REG_A5XX_RBBM_CFG_DBGBUS_OPL … #define REG_A5XX_RBBM_CFG_DBGBUS_OPE … #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 … #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 … #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 … #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 … #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 … #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 … #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 … #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 … #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 … #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 … #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 … #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 … #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 … #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 … #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 … #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 … #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 … #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 … #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE … #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 … #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 … #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG … #define REG_A5XX_RBBM_CFG_DBGBUS_IDX … #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC … #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT … #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL … #define REG_A5XX_RBBM_INT_CLEAR_CMD … #define REG_A5XX_RBBM_INT_0_MASK … #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE … #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR … #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT … #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT … #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT … #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT … #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW … #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR … #define A5XX_RBBM_INT_0_MASK_CP_SW … #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR … #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS … #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS … #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS … #define A5XX_RBBM_INT_0_MASK_CP_IB2 … #define A5XX_RBBM_INT_0_MASK_CP_IB1 … #define A5XX_RBBM_INT_0_MASK_CP_RB … #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS … #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS … #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS … #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW … #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT … #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS … #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR … #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 … #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 … #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP … #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE … #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ … #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG … #define REG_A5XX_RBBM_AHB_DBG_CNTL … #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL … #define REG_A5XX_RBBM_SW_RESET_CMD … #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD … #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 … #define REG_A5XX_RBBM_DBG_LO_HI_GPIO … #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL … #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 … #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 … #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 … #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 … #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 … #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 … #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 … #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 … #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 … #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 … #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 … #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 … #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG … #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE … #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE … #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE … #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE … #define REG_A5XX_RBBM_CLOCK_HYST_UCHE … #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE … #define REG_A5XX_RBBM_CLOCK_MODE_GPC … #define REG_A5XX_RBBM_CLOCK_DELAY_GPC … #define REG_A5XX_RBBM_CLOCK_HYST_GPC … #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM … #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM … #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM … #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ … #define REG_A5XX_RBBM_CLOCK_CNTL … #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 … #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 … #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 … #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 … #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 … #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 … #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 … #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 … #define REG_A5XX_RBBM_CLOCK_HYST_SP0 … #define REG_A5XX_RBBM_CLOCK_HYST_SP1 … #define REG_A5XX_RBBM_CLOCK_HYST_SP2 … #define REG_A5XX_RBBM_CLOCK_HYST_SP3 … #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 … #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 … #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 … #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 … #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 … #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 … #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 … #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 … #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 … #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 … #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 … #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 … #define REG_A5XX_RBBM_CLOCK_HYST_RAC … #define REG_A5XX_RBBM_CLOCK_DELAY_RAC … #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 … #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 … #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 … #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 … #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 … #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 … #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 … #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 … #define REG_A5XX_RBBM_CLOCK_CNTL_RAC … #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC … #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 … #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 … #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 … #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 … #define REG_A5XX_RBBM_CLOCK_HYST_VFD … #define REG_A5XX_RBBM_CLOCK_MODE_VFD … #define REG_A5XX_RBBM_CLOCK_DELAY_VFD … #define REG_A5XX_RBBM_AHB_CNTL0 … #define REG_A5XX_RBBM_AHB_CNTL1 … #define REG_A5XX_RBBM_AHB_CNTL2 … #define REG_A5XX_RBBM_AHB_CMD … #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 … #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 … #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 … #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 … #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 … #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 … #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 … #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 … #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 … #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 … #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 … #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 … #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 … #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 … #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 … #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 … #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 … #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 … #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 … #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 … #define REG_A5XX_RBBM_CLOCK_HYST_TP0 … #define REG_A5XX_RBBM_CLOCK_HYST_TP1 … #define REG_A5XX_RBBM_CLOCK_HYST_TP2 … #define REG_A5XX_RBBM_CLOCK_HYST_TP3 … #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 … #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 … #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 … #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 … #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 … #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 … #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 … #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 … #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU … #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU … #define REG_A5XX_RBBM_CLOCK_HYST_GPMU … #define REG_A5XX_RBBM_PERFCTR_CP_0_LO … #define REG_A5XX_RBBM_PERFCTR_CP_0_HI … #define REG_A5XX_RBBM_PERFCTR_CP_1_LO … #define REG_A5XX_RBBM_PERFCTR_CP_1_HI … #define REG_A5XX_RBBM_PERFCTR_CP_2_LO … #define REG_A5XX_RBBM_PERFCTR_CP_2_HI … #define REG_A5XX_RBBM_PERFCTR_CP_3_LO … #define REG_A5XX_RBBM_PERFCTR_CP_3_HI … #define REG_A5XX_RBBM_PERFCTR_CP_4_LO … #define REG_A5XX_RBBM_PERFCTR_CP_4_HI … #define REG_A5XX_RBBM_PERFCTR_CP_5_LO … #define REG_A5XX_RBBM_PERFCTR_CP_5_HI … #define REG_A5XX_RBBM_PERFCTR_CP_6_LO … #define REG_A5XX_RBBM_PERFCTR_CP_6_HI … #define REG_A5XX_RBBM_PERFCTR_CP_7_LO … #define REG_A5XX_RBBM_PERFCTR_CP_7_HI … #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO … #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI … #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO … #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI … #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO … #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI … #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO … #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI … #define REG_A5XX_RBBM_PERFCTR_PC_0_LO … #define REG_A5XX_RBBM_PERFCTR_PC_0_HI … #define REG_A5XX_RBBM_PERFCTR_PC_1_LO … #define REG_A5XX_RBBM_PERFCTR_PC_1_HI … #define REG_A5XX_RBBM_PERFCTR_PC_2_LO … #define REG_A5XX_RBBM_PERFCTR_PC_2_HI … #define REG_A5XX_RBBM_PERFCTR_PC_3_LO … #define REG_A5XX_RBBM_PERFCTR_PC_3_HI … #define REG_A5XX_RBBM_PERFCTR_PC_4_LO … #define REG_A5XX_RBBM_PERFCTR_PC_4_HI … #define REG_A5XX_RBBM_PERFCTR_PC_5_LO … #define REG_A5XX_RBBM_PERFCTR_PC_5_HI … #define REG_A5XX_RBBM_PERFCTR_PC_6_LO … #define REG_A5XX_RBBM_PERFCTR_PC_6_HI … #define REG_A5XX_RBBM_PERFCTR_PC_7_LO … #define REG_A5XX_RBBM_PERFCTR_PC_7_HI … #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO … #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI … #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO … #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI … #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO … #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI … #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO … #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI … #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO … #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI … #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO … #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI … #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO … #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI … #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO … #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI … #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO … #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI … #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO … #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI … #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO … #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI … #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO … #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI … #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO … #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI … #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO … #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI … #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO … #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI … #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO … #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI … #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO … #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI … #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO … #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI … #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO … #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI … #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO … #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI … #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO … #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI … #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO … #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI … #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO … #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI … #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO … #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI … #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO … #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI … #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO … #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI … #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO … #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI … #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO … #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI … #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO … #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI … #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO … #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI … #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO … #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI … #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO … #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI … #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO … #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI … #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO … #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI … #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO … #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI … #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO … #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI … #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO … #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI … #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO … #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI … #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO … #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI … #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO … #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI … #define REG_A5XX_RBBM_PERFCTR_TP_0_LO … #define REG_A5XX_RBBM_PERFCTR_TP_0_HI … #define REG_A5XX_RBBM_PERFCTR_TP_1_LO … #define REG_A5XX_RBBM_PERFCTR_TP_1_HI … #define REG_A5XX_RBBM_PERFCTR_TP_2_LO … #define REG_A5XX_RBBM_PERFCTR_TP_2_HI … #define REG_A5XX_RBBM_PERFCTR_TP_3_LO … #define REG_A5XX_RBBM_PERFCTR_TP_3_HI … #define REG_A5XX_RBBM_PERFCTR_TP_4_LO … #define REG_A5XX_RBBM_PERFCTR_TP_4_HI … #define REG_A5XX_RBBM_PERFCTR_TP_5_LO … #define REG_A5XX_RBBM_PERFCTR_TP_5_HI … #define REG_A5XX_RBBM_PERFCTR_TP_6_LO … #define REG_A5XX_RBBM_PERFCTR_TP_6_HI … #define REG_A5XX_RBBM_PERFCTR_TP_7_LO … #define REG_A5XX_RBBM_PERFCTR_TP_7_HI … #define REG_A5XX_RBBM_PERFCTR_SP_0_LO … #define REG_A5XX_RBBM_PERFCTR_SP_0_HI … #define REG_A5XX_RBBM_PERFCTR_SP_1_LO … #define REG_A5XX_RBBM_PERFCTR_SP_1_HI … #define REG_A5XX_RBBM_PERFCTR_SP_2_LO … #define REG_A5XX_RBBM_PERFCTR_SP_2_HI … #define REG_A5XX_RBBM_PERFCTR_SP_3_LO … #define REG_A5XX_RBBM_PERFCTR_SP_3_HI … #define REG_A5XX_RBBM_PERFCTR_SP_4_LO … #define REG_A5XX_RBBM_PERFCTR_SP_4_HI … #define REG_A5XX_RBBM_PERFCTR_SP_5_LO … #define REG_A5XX_RBBM_PERFCTR_SP_5_HI … #define REG_A5XX_RBBM_PERFCTR_SP_6_LO … #define REG_A5XX_RBBM_PERFCTR_SP_6_HI … #define REG_A5XX_RBBM_PERFCTR_SP_7_LO … #define REG_A5XX_RBBM_PERFCTR_SP_7_HI … #define REG_A5XX_RBBM_PERFCTR_SP_8_LO … #define REG_A5XX_RBBM_PERFCTR_SP_8_HI … #define REG_A5XX_RBBM_PERFCTR_SP_9_LO … #define REG_A5XX_RBBM_PERFCTR_SP_9_HI … #define REG_A5XX_RBBM_PERFCTR_SP_10_LO … #define REG_A5XX_RBBM_PERFCTR_SP_10_HI … #define REG_A5XX_RBBM_PERFCTR_SP_11_LO … #define REG_A5XX_RBBM_PERFCTR_SP_11_HI … #define REG_A5XX_RBBM_PERFCTR_RB_0_LO … #define REG_A5XX_RBBM_PERFCTR_RB_0_HI … #define REG_A5XX_RBBM_PERFCTR_RB_1_LO … #define REG_A5XX_RBBM_PERFCTR_RB_1_HI … #define REG_A5XX_RBBM_PERFCTR_RB_2_LO … #define REG_A5XX_RBBM_PERFCTR_RB_2_HI … #define REG_A5XX_RBBM_PERFCTR_RB_3_LO … #define REG_A5XX_RBBM_PERFCTR_RB_3_HI … #define REG_A5XX_RBBM_PERFCTR_RB_4_LO … #define REG_A5XX_RBBM_PERFCTR_RB_4_HI … #define REG_A5XX_RBBM_PERFCTR_RB_5_LO … #define REG_A5XX_RBBM_PERFCTR_RB_5_HI … #define REG_A5XX_RBBM_PERFCTR_RB_6_LO … #define REG_A5XX_RBBM_PERFCTR_RB_6_HI … #define REG_A5XX_RBBM_PERFCTR_RB_7_LO … #define REG_A5XX_RBBM_PERFCTR_RB_7_HI … #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO … #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI … #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO … #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI … #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO … #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI … #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO … #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI … #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO … #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI … #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO … #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI … #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO … #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI … #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO … #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI … #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO … #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI … #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO … #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI … #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 … #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 … #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 … #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 … #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO … #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI … #define REG_A5XX_RBBM_STATUS … #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB … #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP … #define A5XX_RBBM_STATUS_HLSQ_BUSY … #define A5XX_RBBM_STATUS_VSC_BUSY … #define A5XX_RBBM_STATUS_TPL1_BUSY … #define A5XX_RBBM_STATUS_SP_BUSY … #define A5XX_RBBM_STATUS_UCHE_BUSY … #define A5XX_RBBM_STATUS_VPC_BUSY … #define A5XX_RBBM_STATUS_VFDP_BUSY … #define A5XX_RBBM_STATUS_VFD_BUSY … #define A5XX_RBBM_STATUS_TESS_BUSY … #define A5XX_RBBM_STATUS_PC_VSD_BUSY … #define A5XX_RBBM_STATUS_PC_DCALL_BUSY … #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY … #define A5XX_RBBM_STATUS_DCOM_BUSY … #define A5XX_RBBM_STATUS_COM_BUSY … #define A5XX_RBBM_STATUS_LRZ_BUZY … #define A5XX_RBBM_STATUS_A2D_DSP_BUSY … #define A5XX_RBBM_STATUS_CCUFCHE_BUSY … #define A5XX_RBBM_STATUS_RB_BUSY … #define A5XX_RBBM_STATUS_RAS_BUSY … #define A5XX_RBBM_STATUS_TSE_BUSY … #define A5XX_RBBM_STATUS_VBIF_BUSY … #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST … #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST … #define A5XX_RBBM_STATUS_CP_BUSY … #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY … #define A5XX_RBBM_STATUS_CP_CRASH_BUSY … #define A5XX_RBBM_STATUS_CP_ETS_BUSY … #define A5XX_RBBM_STATUS_CP_PFP_BUSY … #define A5XX_RBBM_STATUS_CP_ME_BUSY … #define A5XX_RBBM_STATUS_HI_BUSY … #define REG_A5XX_RBBM_STATUS3 … #define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT … #define REG_A5XX_RBBM_INT_0_STATUS … #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS … #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS … #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS … #define REG_A5XX_RBBM_AHB_ERROR_STATUS … #define REG_A5XX_RBBM_PERFCTR_CNTL … #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 … #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 … #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 … #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 … #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO … #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI … #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED … #define REG_A5XX_RBBM_AHB_ERROR … #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC … #define REG_A5XX_RBBM_CFG_DBGBUS_OVER … #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 … #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 … #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 … #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 … #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 … #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 … #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR … #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 … #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 … #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 … #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 … #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 … #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 … #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 … #define REG_A5XX_RBBM_ISDB_CNT … #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG … #define REG_A5XX_RBBM_SECVID_TRUST_CNTL … #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO … #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI … #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE … #define REG_A5XX_RBBM_SECVID_TSB_CNTL … #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO … #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI … #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO … #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI … #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL … #define REG_A5XX_VSC_BIN_SIZE … #define A5XX_VSC_BIN_SIZE_WIDTH__MASK … #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT … static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) { … } #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK … #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT … static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) { … } #define REG_A5XX_VSC_SIZE_ADDRESS_LO … #define REG_A5XX_VSC_SIZE_ADDRESS_HI … #define REG_A5XX_UNKNOWN_0BC5 … #define REG_A5XX_UNKNOWN_0BC6 … #define REG_A5XX_VSC_PIPE_CONFIG(i0) … static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { … } #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK … #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT … static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) { … } #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK … #define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT … static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) { … } #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK … #define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT … static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) { … } #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK … #define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT … static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) { … } #define REG_A5XX_VSC_PIPE_DATA_ADDRESS(i0) … static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { … } static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { … } #define REG_A5XX_VSC_PIPE_DATA_LENGTH(i0) … static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { … } #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 … #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 … #define REG_A5XX_VSC_RESOLVE_CNTL … #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE … #define A5XX_VSC_RESOLVE_CNTL_X__MASK … #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT … static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val) { … } #define A5XX_VSC_RESOLVE_CNTL_Y__MASK … #define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT … static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) { … } #define REG_A5XX_GRAS_ADDR_MODE_CNTL … #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 … #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 … #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 … #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 … #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 … #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 … #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 … #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 … #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 … #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 … #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 … #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 … #define REG_A5XX_RB_DBG_ECO_CNTL … #define REG_A5XX_RB_ADDR_MODE_CNTL … #define REG_A5XX_RB_MODE_CNTL … #define REG_A5XX_RB_CCU_CNTL … #define REG_A5XX_RB_PERFCTR_RB_SEL_0 … #define REG_A5XX_RB_PERFCTR_RB_SEL_1 … #define REG_A5XX_RB_PERFCTR_RB_SEL_2 … #define REG_A5XX_RB_PERFCTR_RB_SEL_3 … #define REG_A5XX_RB_PERFCTR_RB_SEL_4 … #define REG_A5XX_RB_PERFCTR_RB_SEL_5 … #define REG_A5XX_RB_PERFCTR_RB_SEL_6 … #define REG_A5XX_RB_PERFCTR_RB_SEL_7 … #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 … #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 … #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 … #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 … #define REG_A5XX_RB_POWERCTR_RB_SEL_0 … #define REG_A5XX_RB_POWERCTR_RB_SEL_1 … #define REG_A5XX_RB_POWERCTR_RB_SEL_2 … #define REG_A5XX_RB_POWERCTR_RB_SEL_3 … #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 … #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 … #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 … #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 … #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 … #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 … #define REG_A5XX_PC_DBG_ECO_CNTL … #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI … #define REG_A5XX_PC_ADDR_MODE_CNTL … #define REG_A5XX_PC_MODE_CNTL … #define REG_A5XX_PC_INDEX_BUF_LO … #define REG_A5XX_PC_INDEX_BUF_HI … #define REG_A5XX_PC_START_INDEX … #define REG_A5XX_PC_MAX_INDEX … #define REG_A5XX_PC_TESSFACTOR_ADDR_LO … #define REG_A5XX_PC_TESSFACTOR_ADDR_HI … #define REG_A5XX_PC_PERFCTR_PC_SEL_0 … #define REG_A5XX_PC_PERFCTR_PC_SEL_1 … #define REG_A5XX_PC_PERFCTR_PC_SEL_2 … #define REG_A5XX_PC_PERFCTR_PC_SEL_3 … #define REG_A5XX_PC_PERFCTR_PC_SEL_4 … #define REG_A5XX_PC_PERFCTR_PC_SEL_5 … #define REG_A5XX_PC_PERFCTR_PC_SEL_6 … #define REG_A5XX_PC_PERFCTR_PC_SEL_7 … #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 … #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 … #define REG_A5XX_HLSQ_DBG_ECO_CNTL … #define REG_A5XX_HLSQ_ADDR_MODE_CNTL … #define REG_A5XX_HLSQ_MODE_CNTL … #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 … #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 … #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 … #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 … #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 … #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 … #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 … #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 … #define REG_A5XX_HLSQ_SPTP_RDSEL … #define REG_A5XX_HLSQ_DBG_READ_SEL … #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE … #define REG_A5XX_VFD_ADDR_MODE_CNTL … #define REG_A5XX_VFD_MODE_CNTL … #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 … #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 … #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 … #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 … #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 … #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 … #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 … #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 … #define REG_A5XX_VPC_DBG_ECO_CNTL … #define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS … #define REG_A5XX_VPC_ADDR_MODE_CNTL … #define REG_A5XX_VPC_MODE_CNTL … #define A5XX_VPC_MODE_CNTL_BINNING_PASS … #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 … #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 … #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 … #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 … #define REG_A5XX_UCHE_ADDR_MODE_CNTL … #define REG_A5XX_UCHE_MODE_CNTL … #define REG_A5XX_UCHE_SVM_CNTL … #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO … #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI … #define REG_A5XX_UCHE_TRAP_BASE_LO … #define REG_A5XX_UCHE_TRAP_BASE_HI … #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO … #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI … #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO … #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI … #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 … #define REG_A5XX_UCHE_DBG_ECO_CNTL … #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO … #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI … #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO … #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI … #define REG_A5XX_UCHE_CACHE_INVALIDATE … #define REG_A5XX_UCHE_CACHE_WAYS … #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 … #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 … #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 … #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 … #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 … #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 … #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 … #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 … #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 … #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 … #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 … #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 … #define REG_A5XX_UCHE_TRAP_LOG_LO … #define REG_A5XX_UCHE_TRAP_LOG_HI … #define REG_A5XX_SP_DBG_ECO_CNTL … #define REG_A5XX_SP_ADDR_MODE_CNTL … #define REG_A5XX_SP_MODE_CNTL … #define REG_A5XX_SP_PERFCTR_SP_SEL_0 … #define REG_A5XX_SP_PERFCTR_SP_SEL_1 … #define REG_A5XX_SP_PERFCTR_SP_SEL_2 … #define REG_A5XX_SP_PERFCTR_SP_SEL_3 … #define REG_A5XX_SP_PERFCTR_SP_SEL_4 … #define REG_A5XX_SP_PERFCTR_SP_SEL_5 … #define REG_A5XX_SP_PERFCTR_SP_SEL_6 … #define REG_A5XX_SP_PERFCTR_SP_SEL_7 … #define REG_A5XX_SP_PERFCTR_SP_SEL_8 … #define REG_A5XX_SP_PERFCTR_SP_SEL_9 … #define REG_A5XX_SP_PERFCTR_SP_SEL_10 … #define REG_A5XX_SP_PERFCTR_SP_SEL_11 … #define REG_A5XX_SP_POWERCTR_SP_SEL_0 … #define REG_A5XX_SP_POWERCTR_SP_SEL_1 … #define REG_A5XX_SP_POWERCTR_SP_SEL_2 … #define REG_A5XX_SP_POWERCTR_SP_SEL_3 … #define REG_A5XX_TPL1_ADDR_MODE_CNTL … #define REG_A5XX_TPL1_MODE_CNTL … #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 … #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 … #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 … #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 … #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 … #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 … #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 … #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 … #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 … #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 … #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 … #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 … #define REG_A5XX_VBIF_VERSION … #define REG_A5XX_VBIF_CLKON … #define REG_A5XX_VBIF_ABIT_SORT … #define REG_A5XX_VBIF_ABIT_SORT_CONF … #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB … #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN … #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 … #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 … #define REG_A5XX_VBIF_XIN_HALT_CTRL0 … #define REG_A5XX_VBIF_XIN_HALT_CTRL1 … #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL … #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 … #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 … #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 … #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 … #define REG_A5XX_VBIF_TEST_BUS_OUT … #define REG_A5XX_VBIF_PERF_CNT_EN0 … #define REG_A5XX_VBIF_PERF_CNT_EN1 … #define REG_A5XX_VBIF_PERF_CNT_EN2 … #define REG_A5XX_VBIF_PERF_CNT_EN3 … #define REG_A5XX_VBIF_PERF_CNT_CLR0 … #define REG_A5XX_VBIF_PERF_CNT_CLR1 … #define REG_A5XX_VBIF_PERF_CNT_CLR2 … #define REG_A5XX_VBIF_PERF_CNT_CLR3 … #define REG_A5XX_VBIF_PERF_CNT_SEL0 … #define REG_A5XX_VBIF_PERF_CNT_SEL1 … #define REG_A5XX_VBIF_PERF_CNT_SEL2 … #define REG_A5XX_VBIF_PERF_CNT_SEL3 … #define REG_A5XX_VBIF_PERF_CNT_LOW0 … #define REG_A5XX_VBIF_PERF_CNT_LOW1 … #define REG_A5XX_VBIF_PERF_CNT_LOW2 … #define REG_A5XX_VBIF_PERF_CNT_LOW3 … #define REG_A5XX_VBIF_PERF_CNT_HIGH0 … #define REG_A5XX_VBIF_PERF_CNT_HIGH1 … #define REG_A5XX_VBIF_PERF_CNT_HIGH2 … #define REG_A5XX_VBIF_PERF_CNT_HIGH3 … #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 … #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 … #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 … #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 … #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 … #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 … #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 … #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 … #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 … #define REG_A5XX_GPMU_INST_RAM_BASE … #define REG_A5XX_GPMU_DATA_RAM_BASE … #define REG_A5XX_SP_POWER_COUNTER_0_LO … #define REG_A5XX_SP_POWER_COUNTER_0_HI … #define REG_A5XX_SP_POWER_COUNTER_1_LO … #define REG_A5XX_SP_POWER_COUNTER_1_HI … #define REG_A5XX_SP_POWER_COUNTER_2_LO … #define REG_A5XX_SP_POWER_COUNTER_2_HI … #define REG_A5XX_SP_POWER_COUNTER_3_LO … #define REG_A5XX_SP_POWER_COUNTER_3_HI … #define REG_A5XX_TP_POWER_COUNTER_0_LO … #define REG_A5XX_TP_POWER_COUNTER_0_HI … #define REG_A5XX_TP_POWER_COUNTER_1_LO … #define REG_A5XX_TP_POWER_COUNTER_1_HI … #define REG_A5XX_TP_POWER_COUNTER_2_LO … #define REG_A5XX_TP_POWER_COUNTER_2_HI … #define REG_A5XX_TP_POWER_COUNTER_3_LO … #define REG_A5XX_TP_POWER_COUNTER_3_HI … #define REG_A5XX_RB_POWER_COUNTER_0_LO … #define REG_A5XX_RB_POWER_COUNTER_0_HI … #define REG_A5XX_RB_POWER_COUNTER_1_LO … #define REG_A5XX_RB_POWER_COUNTER_1_HI … #define REG_A5XX_RB_POWER_COUNTER_2_LO … #define REG_A5XX_RB_POWER_COUNTER_2_HI … #define REG_A5XX_RB_POWER_COUNTER_3_LO … #define REG_A5XX_RB_POWER_COUNTER_3_HI … #define REG_A5XX_CCU_POWER_COUNTER_0_LO … #define REG_A5XX_CCU_POWER_COUNTER_0_HI … #define REG_A5XX_CCU_POWER_COUNTER_1_LO … #define REG_A5XX_CCU_POWER_COUNTER_1_HI … #define REG_A5XX_UCHE_POWER_COUNTER_0_LO … #define REG_A5XX_UCHE_POWER_COUNTER_0_HI … #define REG_A5XX_UCHE_POWER_COUNTER_1_LO … #define REG_A5XX_UCHE_POWER_COUNTER_1_HI … #define REG_A5XX_UCHE_POWER_COUNTER_2_LO … #define REG_A5XX_UCHE_POWER_COUNTER_2_HI … #define REG_A5XX_UCHE_POWER_COUNTER_3_LO … #define REG_A5XX_UCHE_POWER_COUNTER_3_HI … #define REG_A5XX_CP_POWER_COUNTER_0_LO … #define REG_A5XX_CP_POWER_COUNTER_0_HI … #define REG_A5XX_CP_POWER_COUNTER_1_LO … #define REG_A5XX_CP_POWER_COUNTER_1_HI … #define REG_A5XX_CP_POWER_COUNTER_2_LO … #define REG_A5XX_CP_POWER_COUNTER_2_HI … #define REG_A5XX_CP_POWER_COUNTER_3_LO … #define REG_A5XX_CP_POWER_COUNTER_3_HI … #define REG_A5XX_GPMU_POWER_COUNTER_0_LO … #define REG_A5XX_GPMU_POWER_COUNTER_0_HI … #define REG_A5XX_GPMU_POWER_COUNTER_1_LO … #define REG_A5XX_GPMU_POWER_COUNTER_1_HI … #define REG_A5XX_GPMU_POWER_COUNTER_2_LO … #define REG_A5XX_GPMU_POWER_COUNTER_2_HI … #define REG_A5XX_GPMU_POWER_COUNTER_3_LO … #define REG_A5XX_GPMU_POWER_COUNTER_3_HI … #define REG_A5XX_GPMU_POWER_COUNTER_4_LO … #define REG_A5XX_GPMU_POWER_COUNTER_4_HI … #define REG_A5XX_GPMU_POWER_COUNTER_5_LO … #define REG_A5XX_GPMU_POWER_COUNTER_5_HI … #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE … #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO … #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI … #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET … #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 … #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 … #define REG_A5XX_GPMU_GPMU_SP_CLOCK_CONTROL … #define REG_A5XX_GPMU_SP_POWER_CNTL … #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL … #define REG_A5XX_GPMU_RBCCU_POWER_CNTL … #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS … #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON … #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS … #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON … #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY … #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL … #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST … #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL … #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL … #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL … #define REG_A5XX_GPMU_WFI_CONFIG … #define REG_A5XX_GPMU_RBBM_INTR_INFO … #define REG_A5XX_GPMU_CM3_SYSRESET … #define REG_A5XX_GPMU_GENERAL_0 … #define REG_A5XX_GPMU_GENERAL_1 … #define REG_A5XX_GPMU_TEMP_SENSOR_ID … #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG … #define REG_A5XX_GPMU_TEMP_VAL … #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD … #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS … #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK … #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 … #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 … #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 … #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 … #define REG_A5XX_GPMU_BASE_LEAKAGE … #define REG_A5XX_GPMU_GPMU_VOLTAGE … #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS … #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK … #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD … #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL … #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS … #define REG_A5XX_GDPM_CONFIG1 … #define REG_A5XX_GDPM_CONFIG2 … #define REG_A5XX_GDPM_INT_EN … #define REG_A5XX_GDPM_INT_MASK … #define REG_A5XX_GPMU_BEC_ENABLE … #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS … #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 … #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 … #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 … #define REG_A5XX_GPU_CS_ENABLE_REG … #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 … #define REG_A5XX_GRAS_CL_CNTL … #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z … #define REG_A5XX_GRAS_VS_CL_CNTL … #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK … #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) { … } #define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK … #define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT … static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) { … } #define REG_A5XX_UNKNOWN_E004 … #define REG_A5XX_GRAS_CNTL … #define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL … #define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID … #define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE … #define A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL … #define A5XX_GRAS_CNTL_IJ_LINEAR_CENTROID … #define A5XX_GRAS_CNTL_IJ_LINEAR_SAMPLE … #define A5XX_GRAS_CNTL_COORD_MASK__MASK … #define A5XX_GRAS_CNTL_COORD_MASK__SHIFT … static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val) { … } #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ … #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK … #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT … static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) { … } #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK … #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT … static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) { … } #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 … #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK … #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT … static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val) { … } #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 … #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK … #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT … static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val) { … } #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 … #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK … #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT … static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val) { … } #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 … #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK … #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT … static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val) { … } #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 … #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK … #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT … static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val) { … } #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 … #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK … #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT … static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val) { … } #define REG_A5XX_GRAS_SU_CNTL … #define A5XX_GRAS_SU_CNTL_CULL_FRONT … #define A5XX_GRAS_SU_CNTL_CULL_BACK … #define A5XX_GRAS_SU_CNTL_FRONT_CW … #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK … #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT … static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) { … } #define A5XX_GRAS_SU_CNTL_POLY_OFFSET … #define A5XX_GRAS_SU_CNTL_LINE_MODE__MASK … #define A5XX_GRAS_SU_CNTL_LINE_MODE__SHIFT … static inline uint32_t A5XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) { … } #define REG_A5XX_GRAS_SU_POINT_MINMAX … #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK … #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT … static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val) { … } #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK … #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT … static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val) { … } #define REG_A5XX_GRAS_SU_POINT_SIZE … #define A5XX_GRAS_SU_POINT_SIZE__MASK … #define A5XX_GRAS_SU_POINT_SIZE__SHIFT … static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val) { … } #define REG_A5XX_GRAS_SU_LAYERED … #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL … #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z … #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 … #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE … #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK … #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT … static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val) { … } #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET … #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK … #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT … static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) { … } #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP … #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK … #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT … static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) { … } #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO … #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK … #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT … static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) { … } #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL … #define REG_A5XX_GRAS_SC_CNTL … #define A5XX_GRAS_SC_CNTL_BINNING_PASS … #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED … #define REG_A5XX_GRAS_SC_BIN_CNTL … #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL … #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK … #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL … #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK … #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE … #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL … #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 … #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE … #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK … #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT … static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) { … } #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK … #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT … static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) { … } #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 … #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE … #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK … #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT … static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) { … } #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK … #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT … static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) { … } #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 … #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE … #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK … #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT … static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) { … } #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK … #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT … static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) { … } #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 … #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE … #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK … #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT … static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) { … } #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK … #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT … static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) { … } #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL … #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE … #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK … #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT … static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) { … } #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK … #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT … static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) { … } #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR … #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE … #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK … #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT … static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) { … } #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK … #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT … static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) { … } #define REG_A5XX_GRAS_LRZ_CNTL … #define A5XX_GRAS_LRZ_CNTL_ENABLE … #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE … #define A5XX_GRAS_LRZ_CNTL_GREATER … #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO … #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI … #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH … #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK … #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT … static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val) { … } #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO … #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI … #define REG_A5XX_RB_CNTL … #define A5XX_RB_CNTL_WIDTH__MASK … #define A5XX_RB_CNTL_WIDTH__SHIFT … static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) { … } #define A5XX_RB_CNTL_HEIGHT__MASK … #define A5XX_RB_CNTL_HEIGHT__SHIFT … static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) { … } #define A5XX_RB_CNTL_BYPASS … #define REG_A5XX_RB_RENDER_CNTL … #define A5XX_RB_RENDER_CNTL_BINNING_PASS … #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED … #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE … #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH … #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 … #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK … #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT … static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) { … } #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK … #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT … static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val) { … } #define REG_A5XX_RB_RAS_MSAA_CNTL … #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK … #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define REG_A5XX_RB_DEST_MSAA_CNTL … #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK … #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE … #define REG_A5XX_RB_RENDER_CONTROL0 … #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL … #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID … #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE … #define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL … #define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID … #define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE … #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK … #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT … static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) { … } #define REG_A5XX_RB_RENDER_CONTROL1 … #define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK … #define A5XX_RB_RENDER_CONTROL1_FACENESS … #define A5XX_RB_RENDER_CONTROL1_SAMPLEID … #define REG_A5XX_RB_FS_OUTPUT_CNTL … #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK … #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT … static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val) { … } #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z … #define REG_A5XX_RB_RENDER_COMPONENTS … #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK … #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT … static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) { … } #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK … #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT … static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) { … } #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK … #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT … static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) { … } #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK … #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT … static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) { … } #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK … #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT … static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) { … } #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK … #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT … static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) { … } #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK … #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT … static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) { … } #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK … #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT … static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) { … } #define REG_A5XX_RB_MRT(i0) … static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { … } #define A5XX_RB_MRT_CONTROL_BLEND … #define A5XX_RB_MRT_CONTROL_BLEND2 … #define A5XX_RB_MRT_CONTROL_ROP_ENABLE … #define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK … #define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT … static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) { … } #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK … #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT … static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) { … } static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { … } #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK … #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT … static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) { … } #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK … #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT … static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { … } #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK … #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT … static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) { … } #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK … #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT … static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) { … } #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK … #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT … static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { … } #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK … #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT … static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) { … } static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { … } #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK … #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) { … } #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK … #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT … static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val) { … } #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK … #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT … static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) { … } #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK … #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB … static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { … } #define A5XX_RB_MRT_PITCH__MASK … #define A5XX_RB_MRT_PITCH__SHIFT … static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val) { … } static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { … } #define A5XX_RB_MRT_ARRAY_PITCH__MASK … #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT … static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) { … } static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { … } static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { … } #define REG_A5XX_RB_BLEND_RED … #define A5XX_RB_BLEND_RED_UINT__MASK … #define A5XX_RB_BLEND_RED_UINT__SHIFT … static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val) { … } #define A5XX_RB_BLEND_RED_SINT__MASK … #define A5XX_RB_BLEND_RED_SINT__SHIFT … static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) { … } #define A5XX_RB_BLEND_RED_FLOAT__MASK … #define A5XX_RB_BLEND_RED_FLOAT__SHIFT … static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val) { … } #define REG_A5XX_RB_BLEND_RED_F32 … #define A5XX_RB_BLEND_RED_F32__MASK … #define A5XX_RB_BLEND_RED_F32__SHIFT … static inline uint32_t A5XX_RB_BLEND_RED_F32(float val) { … } #define REG_A5XX_RB_BLEND_GREEN … #define A5XX_RB_BLEND_GREEN_UINT__MASK … #define A5XX_RB_BLEND_GREEN_UINT__SHIFT … static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val) { … } #define A5XX_RB_BLEND_GREEN_SINT__MASK … #define A5XX_RB_BLEND_GREEN_SINT__SHIFT … static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) { … } #define A5XX_RB_BLEND_GREEN_FLOAT__MASK … #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT … static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val) { … } #define REG_A5XX_RB_BLEND_GREEN_F32 … #define A5XX_RB_BLEND_GREEN_F32__MASK … #define A5XX_RB_BLEND_GREEN_F32__SHIFT … static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val) { … } #define REG_A5XX_RB_BLEND_BLUE … #define A5XX_RB_BLEND_BLUE_UINT__MASK … #define A5XX_RB_BLEND_BLUE_UINT__SHIFT … static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val) { … } #define A5XX_RB_BLEND_BLUE_SINT__MASK … #define A5XX_RB_BLEND_BLUE_SINT__SHIFT … static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) { … } #define A5XX_RB_BLEND_BLUE_FLOAT__MASK … #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT … static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val) { … } #define REG_A5XX_RB_BLEND_BLUE_F32 … #define A5XX_RB_BLEND_BLUE_F32__MASK … #define A5XX_RB_BLEND_BLUE_F32__SHIFT … static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val) { … } #define REG_A5XX_RB_BLEND_ALPHA … #define A5XX_RB_BLEND_ALPHA_UINT__MASK … #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT … static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val) { … } #define A5XX_RB_BLEND_ALPHA_SINT__MASK … #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT … static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) { … } #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK … #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT … static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val) { … } #define REG_A5XX_RB_BLEND_ALPHA_F32 … #define A5XX_RB_BLEND_ALPHA_F32__MASK … #define A5XX_RB_BLEND_ALPHA_F32__SHIFT … static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val) { … } #define REG_A5XX_RB_ALPHA_CONTROL … #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK … #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT … static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) { … } #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST … #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK … #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT … static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) { … } #define REG_A5XX_RB_BLEND_CNTL … #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK … #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT … static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) { … } #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND … #define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE … #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK … #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT … static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) { … } #define REG_A5XX_RB_DEPTH_PLANE_CNTL … #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z … #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 … #define REG_A5XX_RB_DEPTH_CNTL … #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE … #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE … #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK … #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT … static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) { … } #define A5XX_RB_DEPTH_CNTL_Z_READ_ENABLE … #define REG_A5XX_RB_DEPTH_BUFFER_INFO … #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK … #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT … static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) { … } #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO … #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI … #define REG_A5XX_RB_DEPTH_BUFFER_PITCH … #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK … #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT … static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) { … } #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH … #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK … #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT … static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) { … } #define REG_A5XX_RB_STENCIL_CONTROL … #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE … #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF … #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ … #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK … #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT … static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) { … } #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK … #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT … static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) { … } #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK … #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT … static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) { … } #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK … #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT … static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) { … } #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK … #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT … static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) { … } #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK … #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT … static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) { … } #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK … #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT … static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) { … } #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK … #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT … static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) { … } #define REG_A5XX_RB_STENCIL_INFO … #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL … #define REG_A5XX_RB_STENCIL_BASE_LO … #define REG_A5XX_RB_STENCIL_BASE_HI … #define REG_A5XX_RB_STENCIL_PITCH … #define A5XX_RB_STENCIL_PITCH__MASK … #define A5XX_RB_STENCIL_PITCH__SHIFT … static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) { … } #define REG_A5XX_RB_STENCIL_ARRAY_PITCH … #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK … #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT … static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) { … } #define REG_A5XX_RB_STENCILREFMASK … #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK … #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT … static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) { … } #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK … #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT … static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) { … } #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK … #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT … static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) { … } #define REG_A5XX_RB_STENCILREFMASK_BF … #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK … #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT … static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) { … } #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK … #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT … static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) { … } #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK … #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT … static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) { … } #define REG_A5XX_RB_WINDOW_OFFSET … #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE … #define A5XX_RB_WINDOW_OFFSET_X__MASK … #define A5XX_RB_WINDOW_OFFSET_X__SHIFT … static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val) { … } #define A5XX_RB_WINDOW_OFFSET_Y__MASK … #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT … static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val) { … } #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL … #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY … #define REG_A5XX_RB_BLIT_CNTL … #define A5XX_RB_BLIT_CNTL_BUF__MASK … #define A5XX_RB_BLIT_CNTL_BUF__SHIFT … static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val) { … } #define REG_A5XX_RB_RESOLVE_CNTL_1 … #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE … #define A5XX_RB_RESOLVE_CNTL_1_X__MASK … #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT … static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val) { … } #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK … #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT … static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val) { … } #define REG_A5XX_RB_RESOLVE_CNTL_2 … #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE … #define A5XX_RB_RESOLVE_CNTL_2_X__MASK … #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT … static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val) { … } #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK … #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT … static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) { … } #define REG_A5XX_RB_RESOLVE_CNTL_3 … #define A5XX_RB_RESOLVE_CNTL_3_TILED … #define REG_A5XX_RB_BLIT_DST_LO … #define REG_A5XX_RB_BLIT_DST_HI … #define REG_A5XX_RB_BLIT_DST_PITCH … #define A5XX_RB_BLIT_DST_PITCH__MASK … #define A5XX_RB_BLIT_DST_PITCH__SHIFT … static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) { … } #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH … #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK … #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT … static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) { … } #define REG_A5XX_RB_CLEAR_COLOR_DW0 … #define REG_A5XX_RB_CLEAR_COLOR_DW1 … #define REG_A5XX_RB_CLEAR_COLOR_DW2 … #define REG_A5XX_RB_CLEAR_COLOR_DW3 … #define REG_A5XX_RB_CLEAR_CNTL … #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR … #define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE … #define A5XX_RB_CLEAR_CNTL_MASK__MASK … #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT … static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val) { … } #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO … #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI … #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH … #define REG_A5XX_RB_MRT_FLAG_BUFFER(i0) … static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { … } static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { … } static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { … } #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK … #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT … static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) { … } static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { … } #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK … #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT … static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) { … } #define REG_A5XX_RB_BLIT_FLAG_DST_LO … #define REG_A5XX_RB_BLIT_FLAG_DST_HI … #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH … #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK … #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT … static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) { … } #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH … #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK … #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT … static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) { … } #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO … #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI … #define REG_A5XX_VPC_CNTL_0 … #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK … #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT … static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) { … } #define A5XX_VPC_CNTL_0_VARYING … #define REG_A5XX_VPC_VARYING_INTERP(i0) … static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { … } #define REG_A5XX_VPC_VARYING_PS_REPL(i0) … static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { … } #define REG_A5XX_UNKNOWN_E292 … #define REG_A5XX_UNKNOWN_E293 … #define REG_A5XX_VPC_VAR(i0) … static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { … } #define REG_A5XX_VPC_GS_SIV_CNTL … #define REG_A5XX_VPC_CLIP_CNTL … #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK … #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val) { … } #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK … #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT … static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) { … } #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK … #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT … static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) { … } #define REG_A5XX_VPC_PACK … #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK … #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT … static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) { … } #define A5XX_VPC_PACK_PSIZELOC__MASK … #define A5XX_VPC_PACK_PSIZELOC__SHIFT … static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val) { … } #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL … #define REG_A5XX_VPC_SO_BUF_CNTL … #define A5XX_VPC_SO_BUF_CNTL_BUF0 … #define A5XX_VPC_SO_BUF_CNTL_BUF1 … #define A5XX_VPC_SO_BUF_CNTL_BUF2 … #define A5XX_VPC_SO_BUF_CNTL_BUF3 … #define A5XX_VPC_SO_BUF_CNTL_ENABLE … #define REG_A5XX_VPC_SO_OVERRIDE … #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE … #define REG_A5XX_VPC_SO_CNTL … #define A5XX_VPC_SO_CNTL_ENABLE … #define REG_A5XX_VPC_SO_PROG … #define A5XX_VPC_SO_PROG_A_BUF__MASK … #define A5XX_VPC_SO_PROG_A_BUF__SHIFT … static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val) { … } #define A5XX_VPC_SO_PROG_A_OFF__MASK … #define A5XX_VPC_SO_PROG_A_OFF__SHIFT … static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val) { … } #define A5XX_VPC_SO_PROG_A_EN … #define A5XX_VPC_SO_PROG_B_BUF__MASK … #define A5XX_VPC_SO_PROG_B_BUF__SHIFT … static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val) { … } #define A5XX_VPC_SO_PROG_B_OFF__MASK … #define A5XX_VPC_SO_PROG_B_OFF__SHIFT … static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val) { … } #define A5XX_VPC_SO_PROG_B_EN … #define REG_A5XX_VPC_SO(i0) … static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { … } static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { … } static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { … } static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { … } static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { … } static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { … } static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { … } #define REG_A5XX_PC_PRIMITIVE_CNTL … #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK … #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT … static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) { … } #define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART … #define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES … #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST … #define REG_A5XX_PC_PRIM_VTX_CNTL … #define A5XX_PC_PRIM_VTX_CNTL_PSIZE … #define REG_A5XX_PC_RASTER_CNTL … #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK … #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT … static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) { … } #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK … #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT … static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) { … } #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE … #define REG_A5XX_PC_CLIP_CNTL … #define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK … #define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val) { … } #define REG_A5XX_PC_RESTART_INDEX … #define REG_A5XX_PC_GS_LAYERED … #define REG_A5XX_PC_GS_PARAM … #define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK … #define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT … static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) { … } #define A5XX_PC_GS_PARAM_INVOCATIONS__MASK … #define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT … static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) { … } #define A5XX_PC_GS_PARAM_PRIMTYPE__MASK … #define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT … static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) { … } #define REG_A5XX_PC_HS_PARAM … #define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK … #define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT … static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) { … } #define A5XX_PC_HS_PARAM_SPACING__MASK … #define A5XX_PC_HS_PARAM_SPACING__SHIFT … static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) { … } #define A5XX_PC_HS_PARAM_CW … #define A5XX_PC_HS_PARAM_CONNECTED … #define REG_A5XX_PC_POWER_CNTL … #define REG_A5XX_VFD_CONTROL_0 … #define A5XX_VFD_CONTROL_0_VTXCNT__MASK … #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT … static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val) { … } #define REG_A5XX_VFD_CONTROL_1 … #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK … #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT … static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) { … } #define A5XX_VFD_CONTROL_1_REGID4INST__MASK … #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT … static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val) { … } #define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK … #define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT … static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) { … } #define REG_A5XX_VFD_CONTROL_2 … #define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK … #define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT … static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) { … } #define REG_A5XX_VFD_CONTROL_3 … #define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK … #define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT … static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) { … } #define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK … #define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT … static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) { … } #define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK … #define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT … static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) { … } #define REG_A5XX_VFD_CONTROL_4 … #define REG_A5XX_VFD_CONTROL_5 … #define REG_A5XX_VFD_INDEX_OFFSET … #define REG_A5XX_VFD_INSTANCE_START_OFFSET … #define REG_A5XX_VFD_FETCH(i0) … static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { … } static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { … } static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { … } static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { … } #define REG_A5XX_VFD_DECODE(i0) … static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { … } #define A5XX_VFD_DECODE_INSTR_IDX__MASK … #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT … static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val) { … } #define A5XX_VFD_DECODE_INSTR_INSTANCED … #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK … #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT … static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val) { … } #define A5XX_VFD_DECODE_INSTR_SWAP__MASK … #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT … static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) { … } #define A5XX_VFD_DECODE_INSTR_UNK30 … #define A5XX_VFD_DECODE_INSTR_FLOAT … static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { … } #define REG_A5XX_VFD_DEST_CNTL(i0) … static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { … } #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK … #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT … static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) { … } #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK … #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT … static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) { … } #define REG_A5XX_VFD_POWER_CNTL … #define REG_A5XX_SP_SP_CNTL … #define REG_A5XX_SP_VS_CONFIG … #define A5XX_SP_VS_CONFIG_ENABLED … #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_SP_FS_CONFIG … #define A5XX_SP_FS_CONFIG_ENABLED … #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_SP_HS_CONFIG … #define A5XX_SP_HS_CONFIG_ENABLED … #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_SP_DS_CONFIG … #define A5XX_SP_DS_CONFIG_ENABLED … #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_SP_GS_CONFIG … #define A5XX_SP_GS_CONFIG_ENABLED … #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_SP_CS_CONFIG … #define A5XX_SP_CS_CONFIG_ENABLED … #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_SP_VS_CONFIG_MAX_CONST … #define REG_A5XX_SP_FS_CONFIG_MAX_CONST … #define REG_A5XX_SP_VS_CTRL_REG0 … #define A5XX_SP_VS_CTRL_REG0_BUFFER … #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK … #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) { … } #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_VS_CTRL_REG0_VARYING … #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE … #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK … #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define REG_A5XX_SP_PRIMITIVE_CNTL … #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK … #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT … static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) { … } #define REG_A5XX_SP_VS_OUT(i0) … static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { … } #define A5XX_SP_VS_OUT_REG_A_REGID__MASK … #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT … static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val) { … } #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK … #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT … static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) { … } #define A5XX_SP_VS_OUT_REG_B_REGID__MASK … #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT … static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val) { … } #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK … #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT … static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) { … } #define REG_A5XX_SP_VS_VPC_DST(i0) … static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { … } #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK … #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT … static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) { … } #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK … #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT … static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) { … } #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK … #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT … static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) { … } #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK … #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT … static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) { … } #define REG_A5XX_UNKNOWN_E5AB … #define REG_A5XX_SP_VS_OBJ_START_LO … #define REG_A5XX_SP_VS_OBJ_START_HI … #define REG_A5XX_SP_VS_PVT_MEM_PARAM … #define A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK … #define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT … static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) { … } #define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A5XX_SP_VS_PVT_MEM_ADDR … #define REG_A5XX_SP_VS_PVT_MEM_SIZE … #define A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define REG_A5XX_SP_FS_CTRL_REG0 … #define A5XX_SP_FS_CTRL_REG0_BUFFER … #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK … #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) { … } #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_FS_CTRL_REG0_VARYING … #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE … #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK … #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define REG_A5XX_UNKNOWN_E5C2 … #define REG_A5XX_SP_FS_OBJ_START_LO … #define REG_A5XX_SP_FS_OBJ_START_HI … #define REG_A5XX_SP_FS_PVT_MEM_PARAM … #define A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK … #define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT … static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) { … } #define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A5XX_SP_FS_PVT_MEM_ADDR … #define REG_A5XX_SP_FS_PVT_MEM_SIZE … #define A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define REG_A5XX_SP_BLEND_CNTL … #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK … #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT … static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) { … } #define A5XX_SP_BLEND_CNTL_UNK8 … #define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE … #define REG_A5XX_SP_FS_OUTPUT_CNTL … #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK … #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT … static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val) { … } #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK … #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT … static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val) { … } #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK … #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT … static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) { … } #define REG_A5XX_SP_FS_OUTPUT(i0) … static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { … } #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK … #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT … static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) { … } #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION … #define REG_A5XX_SP_FS_MRT(i0) … static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { … } #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK … #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT … static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val) { … } #define A5XX_SP_FS_MRT_REG_COLOR_SINT … #define A5XX_SP_FS_MRT_REG_COLOR_UINT … #define A5XX_SP_FS_MRT_REG_COLOR_SRGB … #define REG_A5XX_UNKNOWN_E5DB … #define REG_A5XX_SP_CS_CTRL_REG0 … #define A5XX_SP_CS_CTRL_REG0_BUFFER … #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK … #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) { … } #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_CS_CTRL_REG0_VARYING … #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE … #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK … #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define REG_A5XX_UNKNOWN_E5F2 … #define REG_A5XX_SP_CS_OBJ_START_LO … #define REG_A5XX_SP_CS_OBJ_START_HI … #define REG_A5XX_SP_CS_PVT_MEM_PARAM … #define A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK … #define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT … static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) { … } #define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A5XX_SP_CS_PVT_MEM_ADDR … #define REG_A5XX_SP_CS_PVT_MEM_SIZE … #define A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define REG_A5XX_SP_HS_CTRL_REG0 … #define A5XX_SP_HS_CTRL_REG0_BUFFER … #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK … #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) { … } #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_HS_CTRL_REG0_VARYING … #define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE … #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK … #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define REG_A5XX_UNKNOWN_E602 … #define REG_A5XX_SP_HS_OBJ_START_LO … #define REG_A5XX_SP_HS_OBJ_START_HI … #define REG_A5XX_SP_HS_PVT_MEM_PARAM … #define A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK … #define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT … static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) { … } #define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A5XX_SP_HS_PVT_MEM_ADDR … #define REG_A5XX_SP_HS_PVT_MEM_SIZE … #define A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define REG_A5XX_SP_DS_CTRL_REG0 … #define A5XX_SP_DS_CTRL_REG0_BUFFER … #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK … #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) { … } #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_DS_CTRL_REG0_VARYING … #define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE … #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK … #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define REG_A5XX_UNKNOWN_E62B … #define REG_A5XX_SP_DS_OBJ_START_LO … #define REG_A5XX_SP_DS_OBJ_START_HI … #define REG_A5XX_SP_DS_PVT_MEM_PARAM … #define A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK … #define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT … static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) { … } #define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A5XX_SP_DS_PVT_MEM_ADDR … #define REG_A5XX_SP_DS_PVT_MEM_SIZE … #define A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define REG_A5XX_SP_GS_CTRL_REG0 … #define A5XX_SP_GS_CTRL_REG0_BUFFER … #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK … #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) { … } #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A5XX_SP_GS_CTRL_REG0_VARYING … #define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE … #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK … #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define REG_A5XX_UNKNOWN_E65B … #define REG_A5XX_SP_GS_OBJ_START_LO … #define REG_A5XX_SP_GS_OBJ_START_HI … #define REG_A5XX_SP_GS_PVT_MEM_PARAM … #define A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK … #define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT … static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) { … } #define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A5XX_SP_GS_PVT_MEM_ADDR … #define REG_A5XX_SP_GS_PVT_MEM_SIZE … #define A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL … #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK … #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL … #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK … #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE … #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO … #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI … #define REG_A5XX_TPL1_VS_TEX_COUNT … #define REG_A5XX_TPL1_HS_TEX_COUNT … #define REG_A5XX_TPL1_DS_TEX_COUNT … #define REG_A5XX_TPL1_GS_TEX_COUNT … #define REG_A5XX_TPL1_VS_TEX_SAMP_LO … #define REG_A5XX_TPL1_VS_TEX_SAMP_HI … #define REG_A5XX_TPL1_HS_TEX_SAMP_LO … #define REG_A5XX_TPL1_HS_TEX_SAMP_HI … #define REG_A5XX_TPL1_DS_TEX_SAMP_LO … #define REG_A5XX_TPL1_DS_TEX_SAMP_HI … #define REG_A5XX_TPL1_GS_TEX_SAMP_LO … #define REG_A5XX_TPL1_GS_TEX_SAMP_HI … #define REG_A5XX_TPL1_VS_TEX_CONST_LO … #define REG_A5XX_TPL1_VS_TEX_CONST_HI … #define REG_A5XX_TPL1_HS_TEX_CONST_LO … #define REG_A5XX_TPL1_HS_TEX_CONST_HI … #define REG_A5XX_TPL1_DS_TEX_CONST_LO … #define REG_A5XX_TPL1_DS_TEX_CONST_HI … #define REG_A5XX_TPL1_GS_TEX_CONST_LO … #define REG_A5XX_TPL1_GS_TEX_CONST_HI … #define REG_A5XX_TPL1_FS_TEX_COUNT … #define REG_A5XX_TPL1_CS_TEX_COUNT … #define REG_A5XX_TPL1_FS_TEX_SAMP_LO … #define REG_A5XX_TPL1_FS_TEX_SAMP_HI … #define REG_A5XX_TPL1_CS_TEX_SAMP_LO … #define REG_A5XX_TPL1_CS_TEX_SAMP_HI … #define REG_A5XX_TPL1_FS_TEX_CONST_LO … #define REG_A5XX_TPL1_FS_TEX_CONST_HI … #define REG_A5XX_TPL1_CS_TEX_CONST_LO … #define REG_A5XX_TPL1_CS_TEX_CONST_HI … #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL … #define REG_A5XX_HLSQ_CONTROL_0_REG … #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK … #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) { … } #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK … #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val) { … } #define REG_A5XX_HLSQ_CONTROL_1_REG … #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK … #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) { … } #define REG_A5XX_HLSQ_CONTROL_2_REG … #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK … #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) { … } #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK … #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) { … } #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK … #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) { … } #define A5XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK … #define A5XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) { … } #define REG_A5XX_HLSQ_CONTROL_3_REG … #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK … #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) { … } #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK … #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) { … } #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK … #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) { … } #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK … #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) { … } #define REG_A5XX_HLSQ_CONTROL_4_REG … #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK … #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) { … } #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK … #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) { … } #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK … #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) { … } #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK … #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT … static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) { … } #define REG_A5XX_HLSQ_UPDATE_CNTL … #define REG_A5XX_HLSQ_VS_CONFIG … #define A5XX_HLSQ_VS_CONFIG_ENABLED … #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_HLSQ_FS_CONFIG … #define A5XX_HLSQ_FS_CONFIG_ENABLED … #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_HLSQ_HS_CONFIG … #define A5XX_HLSQ_HS_CONFIG_ENABLED … #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_HLSQ_DS_CONFIG … #define A5XX_HLSQ_DS_CONFIG_ENABLED … #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_HLSQ_GS_CONFIG … #define A5XX_HLSQ_GS_CONFIG_ENABLED … #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_HLSQ_CS_CONFIG … #define A5XX_HLSQ_CS_CONFIG_ENABLED … #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK … #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK … #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A5XX_HLSQ_VS_CNTL … #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE … #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK … #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT … static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val) { … } #define REG_A5XX_HLSQ_FS_CNTL … #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE … #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK … #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT … static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val) { … } #define REG_A5XX_HLSQ_HS_CNTL … #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE … #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK … #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT … static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val) { … } #define REG_A5XX_HLSQ_DS_CNTL … #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE … #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK … #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT … static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val) { … } #define REG_A5XX_HLSQ_GS_CNTL … #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE … #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK … #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT … static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val) { … } #define REG_A5XX_HLSQ_CS_CNTL … #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE … #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK … #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT … static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val) { … } #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X … #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y … #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z … #define REG_A5XX_HLSQ_CS_NDRANGE_0 … #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK … #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT … static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) { … } #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK … #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT … static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) { … } #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK … #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT … static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) { … } #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK … #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT … static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) { … } #define REG_A5XX_HLSQ_CS_NDRANGE_1 … #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK … #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT … static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) { … } #define REG_A5XX_HLSQ_CS_NDRANGE_2 … #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK … #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT … static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) { … } #define REG_A5XX_HLSQ_CS_NDRANGE_3 … #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK … #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT … static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) { … } #define REG_A5XX_HLSQ_CS_NDRANGE_4 … #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK … #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT … static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) { … } #define REG_A5XX_HLSQ_CS_NDRANGE_5 … #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK … #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT … static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) { … } #define REG_A5XX_HLSQ_CS_NDRANGE_6 … #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK … #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT … static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) { … } #define REG_A5XX_HLSQ_CS_CNTL_0 … #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK … #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT … static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) { … } #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK … #define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT … static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) { … } #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK … #define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT … static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) { … } #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK … #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT … static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) { … } #define REG_A5XX_HLSQ_CS_CNTL_1 … #define REG_A5XX_UNKNOWN_E7C0 … #define REG_A5XX_HLSQ_VS_CONSTLEN … #define REG_A5XX_HLSQ_VS_INSTRLEN … #define REG_A5XX_UNKNOWN_E7C5 … #define REG_A5XX_HLSQ_HS_CONSTLEN … #define REG_A5XX_HLSQ_HS_INSTRLEN … #define REG_A5XX_UNKNOWN_E7CA … #define REG_A5XX_HLSQ_DS_CONSTLEN … #define REG_A5XX_HLSQ_DS_INSTRLEN … #define REG_A5XX_UNKNOWN_E7CF … #define REG_A5XX_HLSQ_GS_CONSTLEN … #define REG_A5XX_HLSQ_GS_INSTRLEN … #define REG_A5XX_UNKNOWN_E7D4 … #define REG_A5XX_HLSQ_FS_CONSTLEN … #define REG_A5XX_HLSQ_FS_INSTRLEN … #define REG_A5XX_UNKNOWN_E7D9 … #define REG_A5XX_HLSQ_CS_CONSTLEN … #define REG_A5XX_HLSQ_CS_INSTRLEN … #define REG_A5XX_RB_2D_BLIT_CNTL … #define REG_A5XX_RB_2D_SRC_SOLID_DW0 … #define REG_A5XX_RB_2D_SRC_SOLID_DW1 … #define REG_A5XX_RB_2D_SRC_SOLID_DW2 … #define REG_A5XX_RB_2D_SRC_SOLID_DW3 … #define REG_A5XX_RB_2D_SRC_INFO … #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK … #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) { … } #define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK … #define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT … static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) { … } #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK … #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } #define A5XX_RB_2D_SRC_INFO_FLAGS … #define A5XX_RB_2D_SRC_INFO_SRGB … #define REG_A5XX_RB_2D_SRC_LO … #define REG_A5XX_RB_2D_SRC_HI … #define REG_A5XX_RB_2D_SRC_SIZE … #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK … #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT … static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val) { … } #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK … #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT … static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val) { … } #define REG_A5XX_RB_2D_DST_INFO … #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK … #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) { … } #define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK … #define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT … static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) { … } #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK … #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } #define A5XX_RB_2D_DST_INFO_FLAGS … #define A5XX_RB_2D_DST_INFO_SRGB … #define REG_A5XX_RB_2D_DST_LO … #define REG_A5XX_RB_2D_DST_HI … #define REG_A5XX_RB_2D_DST_SIZE … #define A5XX_RB_2D_DST_SIZE_PITCH__MASK … #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT … static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val) { … } #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK … #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT … static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val) { … } #define REG_A5XX_RB_2D_SRC_FLAGS_LO … #define REG_A5XX_RB_2D_SRC_FLAGS_HI … #define REG_A5XX_RB_2D_SRC_FLAGS_PITCH … #define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK … #define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT … static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val) { … } #define REG_A5XX_RB_2D_DST_FLAGS_LO … #define REG_A5XX_RB_2D_DST_FLAGS_HI … #define REG_A5XX_RB_2D_DST_FLAGS_PITCH … #define A5XX_RB_2D_DST_FLAGS_PITCH__MASK … #define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT … static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) { … } #define REG_A5XX_GRAS_2D_BLIT_CNTL … #define REG_A5XX_GRAS_2D_SRC_INFO … #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK … #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) { … } #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK … #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT … static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) { … } #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK … #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } #define A5XX_GRAS_2D_SRC_INFO_FLAGS … #define A5XX_GRAS_2D_SRC_INFO_SRGB … #define REG_A5XX_GRAS_2D_DST_INFO … #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK … #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) { … } #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK … #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT … static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) { … } #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK … #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } #define A5XX_GRAS_2D_DST_INFO_FLAGS … #define A5XX_GRAS_2D_DST_INFO_SRGB … #define REG_A5XX_UNKNOWN_2184 … #define REG_A5XX_TEX_SAMP_0 … #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR … #define A5XX_TEX_SAMP_0_XY_MAG__MASK … #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT … static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val) { … } #define A5XX_TEX_SAMP_0_XY_MIN__MASK … #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT … static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val) { … } #define A5XX_TEX_SAMP_0_WRAP_S__MASK … #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT … static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val) { … } #define A5XX_TEX_SAMP_0_WRAP_T__MASK … #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT … static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val) { … } #define A5XX_TEX_SAMP_0_WRAP_R__MASK … #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT … static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val) { … } #define A5XX_TEX_SAMP_0_ANISO__MASK … #define A5XX_TEX_SAMP_0_ANISO__SHIFT … static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val) { … } #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK … #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT … static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val) { … } #define REG_A5XX_TEX_SAMP_1 … #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK … #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT … static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) { … } #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF … #define A5XX_TEX_SAMP_1_UNNORM_COORDS … #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR … #define A5XX_TEX_SAMP_1_MAX_LOD__MASK … #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT … static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val) { … } #define A5XX_TEX_SAMP_1_MIN_LOD__MASK … #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT … static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) { … } #define REG_A5XX_TEX_SAMP_2 … #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK … #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT … static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) { … } #define REG_A5XX_TEX_SAMP_3 … #define REG_A5XX_TEX_CONST_0 … #define A5XX_TEX_CONST_0_TILE_MODE__MASK … #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT … static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val) { … } #define A5XX_TEX_CONST_0_SRGB … #define A5XX_TEX_CONST_0_SWIZ_X__MASK … #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT … static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val) { … } #define A5XX_TEX_CONST_0_SWIZ_Y__MASK … #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT … static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val) { … } #define A5XX_TEX_CONST_0_SWIZ_Z__MASK … #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT … static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val) { … } #define A5XX_TEX_CONST_0_SWIZ_W__MASK … #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT … static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val) { … } #define A5XX_TEX_CONST_0_MIPLVLS__MASK … #define A5XX_TEX_CONST_0_MIPLVLS__SHIFT … static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val) { … } #define A5XX_TEX_CONST_0_SAMPLES__MASK … #define A5XX_TEX_CONST_0_SAMPLES__SHIFT … static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) { … } #define A5XX_TEX_CONST_0_FMT__MASK … #define A5XX_TEX_CONST_0_FMT__SHIFT … static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val) { … } #define A5XX_TEX_CONST_0_SWAP__MASK … #define A5XX_TEX_CONST_0_SWAP__SHIFT … static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) { … } #define REG_A5XX_TEX_CONST_1 … #define A5XX_TEX_CONST_1_WIDTH__MASK … #define A5XX_TEX_CONST_1_WIDTH__SHIFT … static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val) { … } #define A5XX_TEX_CONST_1_HEIGHT__MASK … #define A5XX_TEX_CONST_1_HEIGHT__SHIFT … static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) { … } #define REG_A5XX_TEX_CONST_2 … #define A5XX_TEX_CONST_2_BUFFER … #define A5XX_TEX_CONST_2_PITCHALIGN__MASK … #define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT … static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val) { … } #define A5XX_TEX_CONST_2_PITCH__MASK … #define A5XX_TEX_CONST_2_PITCH__SHIFT … static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val) { … } #define A5XX_TEX_CONST_2_TYPE__MASK … #define A5XX_TEX_CONST_2_TYPE__SHIFT … static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) { … } #define REG_A5XX_TEX_CONST_3 … #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK … #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT … static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) { … } #define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK … #define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT … static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) { … } #define A5XX_TEX_CONST_3_TILE_ALL … #define A5XX_TEX_CONST_3_FLAG … #define REG_A5XX_TEX_CONST_4 … #define A5XX_TEX_CONST_4_BASE_LO__MASK … #define A5XX_TEX_CONST_4_BASE_LO__SHIFT … static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val) { … } #define REG_A5XX_TEX_CONST_5 … #define A5XX_TEX_CONST_5_BASE_HI__MASK … #define A5XX_TEX_CONST_5_BASE_HI__SHIFT … static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val) { … } #define A5XX_TEX_CONST_5_DEPTH__MASK … #define A5XX_TEX_CONST_5_DEPTH__SHIFT … static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val) { … } #define REG_A5XX_TEX_CONST_6 … #define REG_A5XX_TEX_CONST_7 … #define REG_A5XX_TEX_CONST_8 … #define REG_A5XX_TEX_CONST_9 … #define REG_A5XX_TEX_CONST_10 … #define REG_A5XX_TEX_CONST_11 … #define REG_A5XX_SSBO_0_0 … #define A5XX_SSBO_0_0_BASE_LO__MASK … #define A5XX_SSBO_0_0_BASE_LO__SHIFT … static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val) { … } #define REG_A5XX_SSBO_0_1 … #define A5XX_SSBO_0_1_PITCH__MASK … #define A5XX_SSBO_0_1_PITCH__SHIFT … static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val) { … } #define REG_A5XX_SSBO_0_2 … #define A5XX_SSBO_0_2_ARRAY_PITCH__MASK … #define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT … static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) { … } #define REG_A5XX_SSBO_0_3 … #define A5XX_SSBO_0_3_CPP__MASK … #define A5XX_SSBO_0_3_CPP__SHIFT … static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val) { … } #define REG_A5XX_SSBO_1_0 … #define A5XX_SSBO_1_0_FMT__MASK … #define A5XX_SSBO_1_0_FMT__SHIFT … static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val) { … } #define A5XX_SSBO_1_0_WIDTH__MASK … #define A5XX_SSBO_1_0_WIDTH__SHIFT … static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val) { … } #define REG_A5XX_SSBO_1_1 … #define A5XX_SSBO_1_1_HEIGHT__MASK … #define A5XX_SSBO_1_1_HEIGHT__SHIFT … static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val) { … } #define A5XX_SSBO_1_1_DEPTH__MASK … #define A5XX_SSBO_1_1_DEPTH__SHIFT … static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val) { … } #define REG_A5XX_SSBO_2_0 … #define A5XX_SSBO_2_0_BASE_LO__MASK … #define A5XX_SSBO_2_0_BASE_LO__SHIFT … static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val) { … } #define REG_A5XX_SSBO_2_1 … #define A5XX_SSBO_2_1_BASE_HI__MASK … #define A5XX_SSBO_2_1_BASE_HI__SHIFT … static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val) { … } #define REG_A5XX_UBO_0 … #define A5XX_UBO_0_BASE_LO__MASK … #define A5XX_UBO_0_BASE_LO__SHIFT … static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val) { … } #define REG_A5XX_UBO_1 … #define A5XX_UBO_1_BASE_HI__MASK … #define A5XX_UBO_1_BASE_HI__SHIFT … static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val) { … } #ifdef __cplusplus #endif #endif /* A5XX_XML */
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