#ifndef A6XX_GMU_XML #define A6XX_GMU_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml ( 11830 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml ( 15485 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif #define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB … #define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB … #define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK … #define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK … #define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK … #define A6XX_GMU_OOB_DCVS_SET_MASK … #define A6XX_GMU_OOB_DCVS_CHECK_MASK … #define A6XX_GMU_OOB_DCVS_CLEAR_MASK … #define A6XX_GMU_OOB_GPU_SET_MASK … #define A6XX_GMU_OOB_GPU_CHECK_MASK … #define A6XX_GMU_OOB_GPU_CLEAR_MASK … #define A6XX_GMU_OOB_PERFCNTR_SET_MASK … #define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK … #define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK … #define A6XX_HFI_IRQ_MSGQ_MASK … #define A6XX_HFI_IRQ_DSGQ_MASK … #define A6XX_HFI_IRQ_BLOCKED_MSG_MASK … #define A6XX_HFI_IRQ_CM3_FAULT_MASK … #define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK … #define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT … static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val) { … } #define A6XX_HFI_IRQ_OOB_MASK__MASK … #define A6XX_HFI_IRQ_OOB_MASK__SHIFT … static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val) { … } #define A6XX_HFI_H2F_IRQ_MASK_BIT … #define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL … #define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL … #define REG_A6XX_GMU_CM3_ITCM_START … #define REG_A6XX_GMU_CM3_DTCM_START … #define REG_A6XX_GMU_NMI_CONTROL_STATUS … #define REG_A6XX_GMU_BOOT_SLUMBER_OPTION … #define REG_A6XX_GMU_GX_VOTE_IDX … #define REG_A6XX_GMU_MX_VOTE_IDX … #define REG_A6XX_GMU_DCVS_ACK_OPTION … #define REG_A6XX_GMU_DCVS_PERF_SETTING … #define REG_A6XX_GMU_DCVS_BW_SETTING … #define REG_A6XX_GMU_DCVS_RETURN … #define REG_A6XX_GMU_ICACHE_CONFIG … #define REG_A6XX_GMU_DCACHE_CONFIG … #define REG_A6XX_GMU_SYS_BUS_CONFIG … #define REG_A6XX_GMU_CM3_SYSRESET … #define REG_A6XX_GMU_CM3_BOOT_CONFIG … #define REG_A6XX_GMU_CM3_FW_BUSY … #define REG_A6XX_GMU_CM3_FW_INIT_RESULT … #define REG_A6XX_GMU_CM3_CFG … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L … #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H … #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL … #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE … #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE … #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE … #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK … #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT … static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val) { … } #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK … #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT … static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val) { … } #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST … #define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST … #define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS … #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF … #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON … #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF … #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON … #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF … #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE … #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF … #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF … #define REG_A6XX_GMU_GPU_NAP_CTRL … #define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE … #define A6XX_GMU_GPU_NAP_CTRL_SID__MASK … #define A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT … static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) { … } #define REG_A6XX_GMU_RPMH_CTRL … #define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE … #define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE … #define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE … #define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE … #define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE … #define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE … #define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE … #define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE … #define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE … #define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE … #define REG_A6XX_GMU_RPMH_HYST_CTRL … #define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE … #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF … #define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF … #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG … #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP … #define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE … #define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL … #define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS … #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L … #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H … #define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE … #define REG_A6XX_GMU_HFI_CTRL_STATUS … #define REG_A6XX_GMU_HFI_VERSION_INFO … #define REG_A6XX_GMU_HFI_SFR_ADDR … #define REG_A6XX_GMU_HFI_MMAP_ADDR … #define REG_A6XX_GMU_HFI_QTBL_INFO … #define REG_A6XX_GMU_HFI_QTBL_ADDR … #define REG_A6XX_GMU_HFI_CTRL_INIT … #define REG_A6XX_GMU_GMU2HOST_INTR_SET … #define REG_A6XX_GMU_GMU2HOST_INTR_CLR … #define REG_A6XX_GMU_GMU2HOST_INTR_INFO … #define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ … #define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT … #define REG_A6XX_GMU_GMU2HOST_INTR_MASK … #define REG_A6XX_GMU_HOST2GMU_INTR_SET … #define REG_A6XX_GMU_HOST2GMU_INTR_CLR … #define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO … #define REG_A6XX_GMU_HOST2GMU_INTR_EN_0 … #define REG_A6XX_GMU_HOST2GMU_INTR_EN_1 … #define REG_A6XX_GMU_HOST2GMU_INTR_EN_2 … #define REG_A6XX_GMU_HOST2GMU_INTR_EN_3 … #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0 … #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1 … #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2 … #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 … #define REG_A6XX_GMU_GENERAL_0 … #define REG_A6XX_GMU_GENERAL_1 … #define REG_A6XX_GMU_GENERAL_6 … #define REG_A6XX_GMU_GENERAL_7 … #define REG_A7XX_GMU_GENERAL_8 … #define REG_A7XX_GMU_GENERAL_9 … #define REG_A7XX_GMU_GENERAL_10 … #define REG_A6XX_GMU_ISENSE_CTRL … #define REG_A6XX_GPU_CS_ENABLE_REG … #define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL … #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3 … #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2 … #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0 … #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2 … #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS … #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1 … #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS … #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 … #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 … #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 … #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE … #define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL … #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE … #define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD … #define REG_A6XX_GMU_AO_INTERRUPT_EN … #define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR … #define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS … #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE … #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP … #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP … #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR … #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP … #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR … #define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK … #define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL … #define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL … #define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL … #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS … #define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB … #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 … #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK … #define REG_A6XX_GMU_AO_AHB_FENCE_CTRL … #define REG_A6XX_GMU_AHB_FENCE_STATUS … #define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR … #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS … #define REG_A6XX_GMU_AO_SPARE_CNTL … #define REG_A6XX_GMU_RSCC_CONTROL_REQ … #define REG_A6XX_GMU_RSCC_CONTROL_ACK … #define REG_A6XX_GMU_AHB_FENCE_RANGE_0 … #define REG_A6XX_GMU_AHB_FENCE_RANGE_1 … #define REG_A6XX_GPU_CC_GX_GDSCR … #define REG_A6XX_GPU_CC_GX_DOMAIN_MISC … #define REG_A6XX_GPU_CPR_FSM_CTL … #define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 … #define REG_A6XX_RSCC_PDC_SEQ_START_ADDR … #define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO … #define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI … #define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 … #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR … #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA … #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 … #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 … #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 … #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 … #define REG_A6XX_RSCC_OVERRIDE_START_ADDR … #define REG_A6XX_RSCC_SEQ_BUSY_DRV0 … #define REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740 … #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 … #define REG_A6XX_RSCC_TCS0_DRV0_STATUS … #define REG_A6XX_RSCC_TCS1_DRV0_STATUS … #define REG_A6XX_RSCC_TCS2_DRV0_STATUS … #define REG_A6XX_RSCC_TCS3_DRV0_STATUS … #ifdef __cplusplus #endif #endif /* A6XX_GMU_XML */
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