#ifndef HDMI_XML #define HDMI_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/display/hdmi.xml ( 44040 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif enum hdmi_hdcp_key_state { … }; enum hdmi_ddc_read_write { … }; enum hdmi_acr_cts { … }; enum hdmi_cec_tx_status { … }; #define REG_HDMI_CTRL … #define HDMI_CTRL_ENABLE … #define HDMI_CTRL_HDMI … #define HDMI_CTRL_ENCRYPTED … #define REG_HDMI_AUDIO_PKT_CTRL1 … #define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND … #define REG_HDMI_ACR_PKT_CTRL … #define HDMI_ACR_PKT_CTRL_CONT … #define HDMI_ACR_PKT_CTRL_SEND … #define HDMI_ACR_PKT_CTRL_SELECT__MASK … #define HDMI_ACR_PKT_CTRL_SELECT__SHIFT … static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val) { … } #define HDMI_ACR_PKT_CTRL_SOURCE … #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK … #define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT … static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val) { … } #define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY … #define REG_HDMI_VBI_PKT_CTRL … #define HDMI_VBI_PKT_CTRL_GC_ENABLE … #define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME … #define HDMI_VBI_PKT_CTRL_ISRC_SEND … #define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS … #define HDMI_VBI_PKT_CTRL_ACP_SEND … #define HDMI_VBI_PKT_CTRL_ACP_SRC_SW … #define REG_HDMI_INFOFRAME_CTRL0 … #define HDMI_INFOFRAME_CTRL0_AVI_SEND … #define HDMI_INFOFRAME_CTRL0_AVI_CONT … #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND … #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT … #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE … #define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE … #define REG_HDMI_INFOFRAME_CTRL1 … #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK … #define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT … static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val) { … } #define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK … #define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT … static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val) { … } #define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK … #define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT … static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val) { … } #define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK … #define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT … static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val) { … } #define REG_HDMI_GEN_PKT_CTRL … #define HDMI_GEN_PKT_CTRL_GENERIC0_SEND … #define HDMI_GEN_PKT_CTRL_GENERIC0_CONT … #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK … #define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT … static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val) { … } #define HDMI_GEN_PKT_CTRL_GENERIC1_SEND … #define HDMI_GEN_PKT_CTRL_GENERIC1_CONT … #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK … #define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT … static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val) { … } #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK … #define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT … static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val) { … } #define REG_HDMI_GC … #define HDMI_GC_MUTE … #define REG_HDMI_AUDIO_PKT_CTRL2 … #define HDMI_AUDIO_PKT_CTRL2_OVERRIDE … #define HDMI_AUDIO_PKT_CTRL2_LAYOUT … static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { … } #define REG_HDMI_GENERIC0_HDR … static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { … } #define REG_HDMI_GENERIC1_HDR … static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { … } #define REG_HDMI_ACR(i0) … static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { … } #define HDMI_ACR_0_CTS__MASK … #define HDMI_ACR_0_CTS__SHIFT … static inline uint32_t HDMI_ACR_0_CTS(uint32_t val) { … } static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { … } #define HDMI_ACR_1_N__MASK … #define HDMI_ACR_1_N__SHIFT … static inline uint32_t HDMI_ACR_1_N(uint32_t val) { … } #define REG_HDMI_AUDIO_INFO0 … #define HDMI_AUDIO_INFO0_CHECKSUM__MASK … #define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT … static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val) { … } #define HDMI_AUDIO_INFO0_CC__MASK … #define HDMI_AUDIO_INFO0_CC__SHIFT … static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val) { … } #define REG_HDMI_AUDIO_INFO1 … #define HDMI_AUDIO_INFO1_CA__MASK … #define HDMI_AUDIO_INFO1_CA__SHIFT … static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val) { … } #define HDMI_AUDIO_INFO1_LSV__MASK … #define HDMI_AUDIO_INFO1_LSV__SHIFT … static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val) { … } #define HDMI_AUDIO_INFO1_DM_INH … #define REG_HDMI_HDCP_CTRL … #define HDMI_HDCP_CTRL_ENABLE … #define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE … #define REG_HDMI_HDCP_DEBUG_CTRL … #define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER … #define REG_HDMI_HDCP_INT_CTRL … #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT … #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK … #define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK … #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT … #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK … #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK … #define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK … #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT … #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK … #define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK … #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT … #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK … #define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK … #define REG_HDMI_HDCP_LINK0_STATUS … #define HDMI_HDCP_LINK0_STATUS_AN_0_READY … #define HDMI_HDCP_LINK0_STATUS_AN_1_READY … #define HDMI_HDCP_LINK0_STATUS_RI_MATCHES … #define HDMI_HDCP_LINK0_STATUS_V_MATCHES … #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK … #define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT … static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val) { … } #define REG_HDMI_HDCP_DDC_CTRL_0 … #define HDMI_HDCP_DDC_CTRL_0_DISABLE … #define REG_HDMI_HDCP_DDC_CTRL_1 … #define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK … #define REG_HDMI_HDCP_DDC_STATUS … #define HDMI_HDCP_DDC_STATUS_XFER_REQ … #define HDMI_HDCP_DDC_STATUS_XFER_DONE … #define HDMI_HDCP_DDC_STATUS_ABORTED … #define HDMI_HDCP_DDC_STATUS_TIMEOUT … #define HDMI_HDCP_DDC_STATUS_NACK0 … #define HDMI_HDCP_DDC_STATUS_NACK1 … #define HDMI_HDCP_DDC_STATUS_FAILED … #define REG_HDMI_HDCP_ENTROPY_CTRL0 … #define REG_HDMI_HDCP_ENTROPY_CTRL1 … #define REG_HDMI_HDCP_RESET … #define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE … #define REG_HDMI_HDCP_RCVPORT_DATA0 … #define REG_HDMI_HDCP_RCVPORT_DATA1 … #define REG_HDMI_HDCP_RCVPORT_DATA2_0 … #define REG_HDMI_HDCP_RCVPORT_DATA2_1 … #define REG_HDMI_HDCP_RCVPORT_DATA3 … #define REG_HDMI_HDCP_RCVPORT_DATA4 … #define REG_HDMI_HDCP_RCVPORT_DATA5 … #define REG_HDMI_HDCP_RCVPORT_DATA6 … #define REG_HDMI_HDCP_RCVPORT_DATA7 … #define REG_HDMI_HDCP_RCVPORT_DATA8 … #define REG_HDMI_HDCP_RCVPORT_DATA9 … #define REG_HDMI_HDCP_RCVPORT_DATA10 … #define REG_HDMI_HDCP_RCVPORT_DATA11 … #define REG_HDMI_HDCP_RCVPORT_DATA12 … #define REG_HDMI_VENSPEC_INFO0 … #define REG_HDMI_VENSPEC_INFO1 … #define REG_HDMI_VENSPEC_INFO2 … #define REG_HDMI_VENSPEC_INFO3 … #define REG_HDMI_VENSPEC_INFO4 … #define REG_HDMI_VENSPEC_INFO5 … #define REG_HDMI_VENSPEC_INFO6 … #define REG_HDMI_AUDIO_CFG … #define HDMI_AUDIO_CFG_ENGINE_ENABLE … #define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK … #define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT … static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val) { … } #define REG_HDMI_USEC_REFTIMER … #define REG_HDMI_DDC_CTRL … #define HDMI_DDC_CTRL_GO … #define HDMI_DDC_CTRL_SOFT_RESET … #define HDMI_DDC_CTRL_SEND_RESET … #define HDMI_DDC_CTRL_SW_STATUS_RESET … #define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK … #define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT … static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val) { … } #define REG_HDMI_DDC_ARBITRATION … #define HDMI_DDC_ARBITRATION_HW_ARBITRATION … #define REG_HDMI_DDC_INT_CTRL … #define HDMI_DDC_INT_CTRL_SW_DONE_INT … #define HDMI_DDC_INT_CTRL_SW_DONE_ACK … #define HDMI_DDC_INT_CTRL_SW_DONE_MASK … #define REG_HDMI_DDC_SW_STATUS … #define HDMI_DDC_SW_STATUS_NACK0 … #define HDMI_DDC_SW_STATUS_NACK1 … #define HDMI_DDC_SW_STATUS_NACK2 … #define HDMI_DDC_SW_STATUS_NACK3 … #define REG_HDMI_DDC_HW_STATUS … #define HDMI_DDC_HW_STATUS_DONE … #define REG_HDMI_DDC_SPEED … #define HDMI_DDC_SPEED_THRESHOLD__MASK … #define HDMI_DDC_SPEED_THRESHOLD__SHIFT … static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val) { … } #define HDMI_DDC_SPEED_PRESCALE__MASK … #define HDMI_DDC_SPEED_PRESCALE__SHIFT … static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val) { … } #define REG_HDMI_DDC_SETUP … #define HDMI_DDC_SETUP_TIMEOUT__MASK … #define HDMI_DDC_SETUP_TIMEOUT__SHIFT … static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val) { … } #define REG_HDMI_I2C_TRANSACTION(i0) … static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { … } #define HDMI_I2C_TRANSACTION_REG_RW__MASK … #define HDMI_I2C_TRANSACTION_REG_RW__SHIFT … static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val) { … } #define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK … #define HDMI_I2C_TRANSACTION_REG_START … #define HDMI_I2C_TRANSACTION_REG_STOP … #define HDMI_I2C_TRANSACTION_REG_CNT__MASK … #define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT … static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val) { … } #define REG_HDMI_DDC_DATA … #define HDMI_DDC_DATA_DATA_RW__MASK … #define HDMI_DDC_DATA_DATA_RW__SHIFT … static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val) { … } #define HDMI_DDC_DATA_DATA__MASK … #define HDMI_DDC_DATA_DATA__SHIFT … static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val) { … } #define HDMI_DDC_DATA_INDEX__MASK … #define HDMI_DDC_DATA_INDEX__SHIFT … static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val) { … } #define HDMI_DDC_DATA_INDEX_WRITE … #define REG_HDMI_HDCP_SHA_CTRL … #define REG_HDMI_HDCP_SHA_STATUS … #define HDMI_HDCP_SHA_STATUS_BLOCK_DONE … #define HDMI_HDCP_SHA_STATUS_COMP_DONE … #define REG_HDMI_HDCP_SHA_DATA … #define HDMI_HDCP_SHA_DATA_DONE … #define REG_HDMI_HPD_INT_STATUS … #define HDMI_HPD_INT_STATUS_INT … #define HDMI_HPD_INT_STATUS_CABLE_DETECTED … #define REG_HDMI_HPD_INT_CTRL … #define HDMI_HPD_INT_CTRL_INT_ACK … #define HDMI_HPD_INT_CTRL_INT_CONNECT … #define HDMI_HPD_INT_CTRL_INT_EN … #define HDMI_HPD_INT_CTRL_RX_INT_ACK … #define HDMI_HPD_INT_CTRL_RX_INT_EN … #define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK … #define REG_HDMI_HPD_CTRL … #define HDMI_HPD_CTRL_TIMEOUT__MASK … #define HDMI_HPD_CTRL_TIMEOUT__SHIFT … static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val) { … } #define HDMI_HPD_CTRL_ENABLE … #define REG_HDMI_DDC_REF … #define HDMI_DDC_REF_REFTIMER_ENABLE … #define HDMI_DDC_REF_REFTIMER__MASK … #define HDMI_DDC_REF_REFTIMER__SHIFT … static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) { … } #define REG_HDMI_HDCP_SW_UPPER_AKSV … #define REG_HDMI_HDCP_SW_LOWER_AKSV … #define REG_HDMI_CEC_CTRL … #define HDMI_CEC_CTRL_ENABLE … #define HDMI_CEC_CTRL_SEND_TRIGGER … #define HDMI_CEC_CTRL_FRAME_SIZE__MASK … #define HDMI_CEC_CTRL_FRAME_SIZE__SHIFT … static inline uint32_t HDMI_CEC_CTRL_FRAME_SIZE(uint32_t val) { … } #define HDMI_CEC_CTRL_LINE_OE … #define REG_HDMI_CEC_WR_DATA … #define HDMI_CEC_WR_DATA_BROADCAST … #define HDMI_CEC_WR_DATA_DATA__MASK … #define HDMI_CEC_WR_DATA_DATA__SHIFT … static inline uint32_t HDMI_CEC_WR_DATA_DATA(uint32_t val) { … } #define REG_HDMI_CEC_RETRANSMIT … #define HDMI_CEC_RETRANSMIT_ENABLE … #define HDMI_CEC_RETRANSMIT_COUNT__MASK … #define HDMI_CEC_RETRANSMIT_COUNT__SHIFT … static inline uint32_t HDMI_CEC_RETRANSMIT_COUNT(uint32_t val) { … } #define REG_HDMI_CEC_STATUS … #define HDMI_CEC_STATUS_BUSY … #define HDMI_CEC_STATUS_TX_FRAME_DONE … #define HDMI_CEC_STATUS_TX_STATUS__MASK … #define HDMI_CEC_STATUS_TX_STATUS__SHIFT … static inline uint32_t HDMI_CEC_STATUS_TX_STATUS(enum hdmi_cec_tx_status val) { … } #define REG_HDMI_CEC_INT … #define HDMI_CEC_INT_TX_DONE … #define HDMI_CEC_INT_TX_DONE_MASK … #define HDMI_CEC_INT_TX_ERROR … #define HDMI_CEC_INT_TX_ERROR_MASK … #define HDMI_CEC_INT_MONITOR … #define HDMI_CEC_INT_MONITOR_MASK … #define HDMI_CEC_INT_RX_DONE … #define HDMI_CEC_INT_RX_DONE_MASK … #define REG_HDMI_CEC_ADDR … #define REG_HDMI_CEC_TIME … #define HDMI_CEC_TIME_ENABLE … #define HDMI_CEC_TIME_SIGNAL_FREE_TIME__MASK … #define HDMI_CEC_TIME_SIGNAL_FREE_TIME__SHIFT … static inline uint32_t HDMI_CEC_TIME_SIGNAL_FREE_TIME(uint32_t val) { … } #define REG_HDMI_CEC_REFTIMER … #define HDMI_CEC_REFTIMER_REFTIMER__MASK … #define HDMI_CEC_REFTIMER_REFTIMER__SHIFT … static inline uint32_t HDMI_CEC_REFTIMER_REFTIMER(uint32_t val) { … } #define HDMI_CEC_REFTIMER_ENABLE … #define REG_HDMI_CEC_RD_DATA … #define HDMI_CEC_RD_DATA_DATA__MASK … #define HDMI_CEC_RD_DATA_DATA__SHIFT … static inline uint32_t HDMI_CEC_RD_DATA_DATA(uint32_t val) { … } #define HDMI_CEC_RD_DATA_SIZE__MASK … #define HDMI_CEC_RD_DATA_SIZE__SHIFT … static inline uint32_t HDMI_CEC_RD_DATA_SIZE(uint32_t val) { … } #define REG_HDMI_CEC_RD_FILTER … #define REG_HDMI_ACTIVE_HSYNC … #define HDMI_ACTIVE_HSYNC_START__MASK … #define HDMI_ACTIVE_HSYNC_START__SHIFT … static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val) { … } #define HDMI_ACTIVE_HSYNC_END__MASK … #define HDMI_ACTIVE_HSYNC_END__SHIFT … static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val) { … } #define REG_HDMI_ACTIVE_VSYNC … #define HDMI_ACTIVE_VSYNC_START__MASK … #define HDMI_ACTIVE_VSYNC_START__SHIFT … static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val) { … } #define HDMI_ACTIVE_VSYNC_END__MASK … #define HDMI_ACTIVE_VSYNC_END__SHIFT … static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val) { … } #define REG_HDMI_VSYNC_ACTIVE_F2 … #define HDMI_VSYNC_ACTIVE_F2_START__MASK … #define HDMI_VSYNC_ACTIVE_F2_START__SHIFT … static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val) { … } #define HDMI_VSYNC_ACTIVE_F2_END__MASK … #define HDMI_VSYNC_ACTIVE_F2_END__SHIFT … static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val) { … } #define REG_HDMI_TOTAL … #define HDMI_TOTAL_H_TOTAL__MASK … #define HDMI_TOTAL_H_TOTAL__SHIFT … static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val) { … } #define HDMI_TOTAL_V_TOTAL__MASK … #define HDMI_TOTAL_V_TOTAL__SHIFT … static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val) { … } #define REG_HDMI_VSYNC_TOTAL_F2 … #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK … #define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT … static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val) { … } #define REG_HDMI_FRAME_CTRL … #define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR … #define HDMI_FRAME_CTRL_VSYNC_LOW … #define HDMI_FRAME_CTRL_HSYNC_LOW … #define HDMI_FRAME_CTRL_INTERLACED_EN … #define REG_HDMI_AUD_INT … #define HDMI_AUD_INT_AUD_FIFO_URUN_INT … #define HDMI_AUD_INT_AUD_FIFO_URAN_MASK … #define HDMI_AUD_INT_AUD_SAM_DROP_INT … #define HDMI_AUD_INT_AUD_SAM_DROP_MASK … #define REG_HDMI_PHY_CTRL … #define HDMI_PHY_CTRL_SW_RESET_PLL … #define HDMI_PHY_CTRL_SW_RESET_PLL_LOW … #define HDMI_PHY_CTRL_SW_RESET … #define HDMI_PHY_CTRL_SW_RESET_LOW … #define REG_HDMI_CEC_WR_RANGE … #define REG_HDMI_CEC_RD_RANGE … #define REG_HDMI_VERSION … #define REG_HDMI_CEC_COMPL_CTL … #define REG_HDMI_CEC_RD_START_RANGE … #define REG_HDMI_CEC_RD_TOTAL_RANGE … #define REG_HDMI_CEC_RD_ERR_RESP_LO … #define REG_HDMI_CEC_WR_CHECK_CONFIG … #define REG_HDMI_8x60_PHY_REG0 … #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK … #define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT … static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val) { … } #define REG_HDMI_8x60_PHY_REG1 … #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK … #define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT … static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val) { … } #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK … #define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT … static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val) { … } #define REG_HDMI_8x60_PHY_REG2 … #define HDMI_8x60_PHY_REG2_PD_DESER … #define HDMI_8x60_PHY_REG2_PD_DRIVE_1 … #define HDMI_8x60_PHY_REG2_PD_DRIVE_2 … #define HDMI_8x60_PHY_REG2_PD_DRIVE_3 … #define HDMI_8x60_PHY_REG2_PD_DRIVE_4 … #define HDMI_8x60_PHY_REG2_PD_PLL … #define HDMI_8x60_PHY_REG2_PD_PWRGEN … #define HDMI_8x60_PHY_REG2_RCV_SENSE_EN … #define REG_HDMI_8x60_PHY_REG3 … #define HDMI_8x60_PHY_REG3_PLL_ENABLE … #define REG_HDMI_8x60_PHY_REG4 … #define REG_HDMI_8x60_PHY_REG5 … #define REG_HDMI_8x60_PHY_REG6 … #define REG_HDMI_8x60_PHY_REG7 … #define REG_HDMI_8x60_PHY_REG8 … #define REG_HDMI_8x60_PHY_REG9 … #define REG_HDMI_8x60_PHY_REG10 … #define REG_HDMI_8x60_PHY_REG11 … #define REG_HDMI_8x60_PHY_REG12 … #define HDMI_8x60_PHY_REG12_RETIMING_EN … #define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN … #define HDMI_8x60_PHY_REG12_FORCE_LOCK … #define REG_HDMI_8960_PHY_REG0 … #define REG_HDMI_8960_PHY_REG1 … #define REG_HDMI_8960_PHY_REG2 … #define REG_HDMI_8960_PHY_REG3 … #define REG_HDMI_8960_PHY_REG4 … #define REG_HDMI_8960_PHY_REG5 … #define REG_HDMI_8960_PHY_REG6 … #define REG_HDMI_8960_PHY_REG7 … #define REG_HDMI_8960_PHY_REG8 … #define REG_HDMI_8960_PHY_REG9 … #define REG_HDMI_8960_PHY_REG10 … #define REG_HDMI_8960_PHY_REG11 … #define REG_HDMI_8960_PHY_REG12 … #define HDMI_8960_PHY_REG12_SW_RESET … #define HDMI_8960_PHY_REG12_PWRDN_B … #define REG_HDMI_8960_PHY_REG_BIST_CFG … #define REG_HDMI_8960_PHY_DEBUG_BUS_SEL … #define REG_HDMI_8960_PHY_REG_MISC0 … #define REG_HDMI_8960_PHY_REG13 … #define REG_HDMI_8960_PHY_REG14 … #define REG_HDMI_8960_PHY_REG15 … #define REG_HDMI_8960_PHY_PLL_REFCLK_CFG … #define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG … #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 … #define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 … #define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG … #define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG … #define REG_HDMI_8960_PHY_PLL_PWRDN_B … #define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL … #define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B … #define REG_HDMI_8960_PHY_PLL_SDM_CFG0 … #define REG_HDMI_8960_PHY_PLL_SDM_CFG1 … #define REG_HDMI_8960_PHY_PLL_SDM_CFG2 … #define REG_HDMI_8960_PHY_PLL_SDM_CFG3 … #define REG_HDMI_8960_PHY_PLL_SDM_CFG4 … #define REG_HDMI_8960_PHY_PLL_SSC_CFG0 … #define REG_HDMI_8960_PHY_PLL_SSC_CFG1 … #define REG_HDMI_8960_PHY_PLL_SSC_CFG2 … #define REG_HDMI_8960_PHY_PLL_SSC_CFG3 … #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 … #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 … #define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 … #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 … #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 … #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 … #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 … #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 … #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 … #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 … #define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 … #define REG_HDMI_8960_PHY_PLL_DEBUG_SEL … #define REG_HDMI_8960_PHY_PLL_MISC0 … #define REG_HDMI_8960_PHY_PLL_MISC1 … #define REG_HDMI_8960_PHY_PLL_MISC2 … #define REG_HDMI_8960_PHY_PLL_MISC3 … #define REG_HDMI_8960_PHY_PLL_MISC4 … #define REG_HDMI_8960_PHY_PLL_MISC5 … #define REG_HDMI_8960_PHY_PLL_MISC6 … #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 … #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 … #define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 … #define REG_HDMI_8960_PHY_PLL_STATUS0 … #define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK … #define REG_HDMI_8960_PHY_PLL_STATUS1 … #define REG_HDMI_8x74_ANA_CFG0 … #define REG_HDMI_8x74_ANA_CFG1 … #define REG_HDMI_8x74_ANA_CFG2 … #define REG_HDMI_8x74_ANA_CFG3 … #define REG_HDMI_8x74_PD_CTRL0 … #define REG_HDMI_8x74_PD_CTRL1 … #define REG_HDMI_8x74_GLB_CFG … #define REG_HDMI_8x74_DCC_CFG0 … #define REG_HDMI_8x74_DCC_CFG1 … #define REG_HDMI_8x74_TXCAL_CFG0 … #define REG_HDMI_8x74_TXCAL_CFG1 … #define REG_HDMI_8x74_TXCAL_CFG2 … #define REG_HDMI_8x74_TXCAL_CFG3 … #define REG_HDMI_8x74_BIST_CFG0 … #define REG_HDMI_8x74_BIST_PATN0 … #define REG_HDMI_8x74_BIST_PATN1 … #define REG_HDMI_8x74_BIST_PATN2 … #define REG_HDMI_8x74_BIST_PATN3 … #define REG_HDMI_8x74_STATUS … #define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG … #define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG … #define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG … #define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG … #define REG_HDMI_28nm_PHY_PLL_VREG_CFG … #define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG … #define REG_HDMI_28nm_PHY_PLL_DMUX_CFG … #define REG_HDMI_28nm_PHY_PLL_AMUX_CFG … #define REG_HDMI_28nm_PHY_PLL_GLB_CFG … #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B … #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B … #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B … #define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE … #define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG … #define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG … #define REG_HDMI_28nm_PHY_PLL_LPFR_CFG … #define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG … #define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG … #define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 … #define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 … #define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 … #define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 … #define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 … #define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 … #define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 … #define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 … #define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 … #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 … #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 … #define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 … #define REG_HDMI_28nm_PHY_PLL_TEST_CFG … #define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 … #define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 … #define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG … #define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL … #define REG_HDMI_28nm_PHY_PLL_STATUS … #define REG_HDMI_8996_PHY_CFG … #define REG_HDMI_8996_PHY_PD_CTL … #define REG_HDMI_8996_PHY_MODE … #define REG_HDMI_8996_PHY_MISR_CLEAR … #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 … #define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 … #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 … #define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 … #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 … #define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 … #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 … #define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 … #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 … #define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 … #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 … #define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 … #define REG_HDMI_8996_PHY_DEBUG_BUS_SEL … #define REG_HDMI_8996_PHY_TXCAL_CFG0 … #define REG_HDMI_8996_PHY_TXCAL_CFG1 … #define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL … #define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL … #define REG_HDMI_8996_PHY_LANE_BIST_CONFIG … #define REG_HDMI_8996_PHY_CLOCK … #define REG_HDMI_8996_PHY_MISC1 … #define REG_HDMI_8996_PHY_MISC2 … #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 … #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 … #define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 … #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 … #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 … #define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 … #define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 … #define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 … #define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 … #define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 … #define REG_HDMI_8996_PHY_POST_MISR_STATUS0 … #define REG_HDMI_8996_PHY_POST_MISR_STATUS1 … #define REG_HDMI_8996_PHY_POST_MISR_STATUS2 … #define REG_HDMI_8996_PHY_POST_MISR_STATUS3 … #define REG_HDMI_8996_PHY_STATUS … #define REG_HDMI_8996_PHY_MISC3_STATUS … #define REG_HDMI_8996_PHY_MISC4_STATUS … #define REG_HDMI_8996_PHY_DEBUG_BUS0 … #define REG_HDMI_8996_PHY_DEBUG_BUS1 … #define REG_HDMI_8996_PHY_DEBUG_BUS2 … #define REG_HDMI_8996_PHY_DEBUG_BUS3 … #define REG_HDMI_8996_PHY_PHY_REVISION_ID0 … #define REG_HDMI_8996_PHY_PHY_REVISION_ID1 … #define REG_HDMI_8996_PHY_PHY_REVISION_ID2 … #define REG_HDMI_8996_PHY_PHY_REVISION_ID3 … #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 … #define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 … #define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE … #define REG_HDMI_PHY_QSERDES_COM_BG_TIMER … #define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER … #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 … #define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 … #define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 … #define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 … #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 … #define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 … #define REG_HDMI_PHY_QSERDES_COM_POST_DIV … #define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX … #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN … #define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 … #define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL … #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE … #define REG_HDMI_PHY_QSERDES_COM_PLL_EN … #define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO … #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 … #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL … #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS … #define REG_HDMI_PHY_QSERDES_COM_BG_TRIM … #define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV … #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 … #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 … #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 … #define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL … #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL … #define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC … #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL … #define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM … #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL … #define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL … #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL … #define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 … #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL … #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 … #define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM … #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN … #define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG … #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL … #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 … #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 … #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 … #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL … #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN … #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 … #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 … #define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 … #define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 … #define REG_HDMI_PHY_QSERDES_COM_SAR … #define REG_HDMI_PHY_QSERDES_COM_SAR_CLK … #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS … #define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS … #define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS … #define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS … #define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS … #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS … #define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS … #define REG_HDMI_PHY_QSERDES_COM_BG_CTRL … #define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT … #define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL … #define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS … #define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG … #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV … #define REG_HDMI_PHY_QSERDES_COM_SW_RESET … #define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN … #define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS … #define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG … #define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE … #define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL … #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 … #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 … #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 … #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 … #define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL … #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 … #define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 … #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 … #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 … #define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT … #define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE … #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE … #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO … #define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE … #define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL … #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH … #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN … #define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES … #define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP … #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL … #define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET … #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN … #define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN … #define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND … #define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL … #define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT … #define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN … #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX … #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX … #define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET … #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 … #define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 … #define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT … #define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL … #define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN … #define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV … #define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 … #define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE … #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE … #define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION … #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 … #define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 … #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL … #define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 … #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 … #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 … #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 … #define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 … #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN … #define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES … #define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN … #define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE … #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL … #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA … #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 … #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 … #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 … #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 … #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 … #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 … #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 … #define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 … #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 … #define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 … #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 … #define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 … #define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV … #ifdef __cplusplus #endif #endif /* HDMI_XML */
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