linux/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */
#ifndef __ADRENO_GEN7_9_0_SNAPSHOT_H
#define __ADRENO_GEN7_9_0_SNAPSHOT_H

#include "a6xx_gpu_state.h"

static const u32 gen7_9_0_debugbus_blocks[] = …;

static const u32 gen7_9_0_gbif_debugbus_blocks[] = …;

static const u32 gen7_9_0_cx_debugbus_blocks[] = …;

static struct gen7_shader_block gen7_9_0_shader_blocks[] = …;

/*
 * Block   : ['PRE_CRASHDUMPER', 'GBIF']
 * pairs   : 2 (Regs:5), 5 (Regs:38)
 */
static const u32 gen7_9_0_pre_crashdumper_gpu_registers[] = …;
static_assert(…);

/*
 * Block   : ['BROADCAST', 'CP', 'GRAS', 'GXCLKCTL']
 * Block   : ['PC', 'RBBM', 'RDVM', 'UCHE']
 * Block   : ['VFD', 'VPC', 'VSC']
 * Pipeline: A7XX_PIPE_NONE
 * pairs   : 196 (Regs:1778)
 */
static const u32 gen7_9_0_gpu_registers[] = …;
static_assert(…);

static const u32 gen7_9_0_gxclkctl_registers[] = …;
static_assert(…);

/*
 * Block   : ['GMUAO', 'GMUCX', 'GMUCX_RAM']
 * Pipeline: A7XX_PIPE_NONE
 * pairs   : 134 (Regs:429)
 */
static const u32 gen7_9_0_gmu_registers[] = …;
static_assert(…);

/*
 * Block   : ['GMUGX']
 * Pipeline: A7XX_PIPE_NONE
 * pairs   : 44 (Regs:454)
 */
static const u32 gen7_9_0_gmugx_registers[] = …;
static_assert(…);

/*
 * Block   : ['CX_MISC']
 * Pipeline: A7XX_PIPE_NONE
 * pairs   : 7 (Regs:56)
 */
static const u32 gen7_9_0_cx_misc_registers[] = …;
static_assert(…);

/*
 * Block   : ['DBGC']
 * Pipeline: A7XX_PIPE_NONE
 * pairs   : 19 (Regs:155)
 */
static const u32 gen7_9_0_dbgc_registers[] = …;
static_assert(…);

/*
 * Block   : ['CX_DBGC']
 * Pipeline: A7XX_PIPE_NONE
 * pairs   : 7 (Regs:75)
 */
static const u32 gen7_9_0_cx_dbgc_registers[] = …;
static_assert(…);

/*
 * Block   : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF']
 * Block   : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC']
 * Block   : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_NONE
 * pairs   : 29 (Regs:573)
 */
static const u32 gen7_9_0_non_context_pipe_br_registers[] = …;
static_assert(…);

/*
 * Block   : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF']
 * Block   : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC']
 * Block   : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC']
 * Pipeline: A7XX_PIPE_BV
 * Cluster : A7XX_CLUSTER_NONE
 * pairs   : 29 (Regs:573)
 */
static const u32 gen7_9_0_non_context_pipe_bv_registers[] = …;
static_assert(…);

/*
 * Block   : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF']
 * Block   : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC']
 * Block   : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC']
 * Pipeline: A7XX_PIPE_LPAC
 * Cluster : A7XX_CLUSTER_NONE
 * pairs   : 2 (Regs:7)
 */
static const u32 gen7_9_0_non_context_pipe_lpac_registers[] = …;
static_assert(…);

/*
 * Block   : ['RB']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_NONE
 * pairs   : 5 (Regs:37)
 */
static const u32 gen7_9_0_non_context_rb_pipe_br_rac_registers[] = …;
static_assert(…);

/*
 * Block   : ['RB']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_NONE
 * pairs   : 15 (Regs:66)
 */
static const u32 gen7_9_0_non_context_rb_pipe_br_rbp_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_NONE
 * Location: A7XX_HLSQ_STATE
 * pairs   : 4 (Regs:28)
 */
static const u32 gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_NONE
 * Location: A7XX_SP_TOP
 * pairs   : 10 (Regs:61)
 */
static const u32 gen7_9_0_non_context_sp_pipe_br_sp_top_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_NONE
 * Location: A7XX_USPTP
 * pairs   : 12 (Regs:62)
 */
static const u32 gen7_9_0_non_context_sp_pipe_br_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_NONE
 * Location: A7XX_HLSQ_DP_STR
 * pairs   : 2 (Regs:5)
 */
static const u32 gen7_9_0_non_context_sp_pipe_br_hlsq_dp_str_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_LPAC
 * Cluster : A7XX_CLUSTER_NONE
 * Location: A7XX_HLSQ_STATE
 * pairs   : 1 (Regs:5)
 */
static const u32 gen7_9_0_non_context_sp_pipe_lpac_hlsq_state_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_LPAC
 * Cluster : A7XX_CLUSTER_NONE
 * Location: A7XX_SP_TOP
 * pairs   : 1 (Regs:6)
 */
static const u32 gen7_9_0_non_context_sp_pipe_lpac_sp_top_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_LPAC
 * Cluster : A7XX_CLUSTER_NONE
 * Location: A7XX_USPTP
 * pairs   : 2 (Regs:9)
 */
static const u32 gen7_9_0_non_context_sp_pipe_lpac_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['TPL1']
 * Pipeline: A7XX_PIPE_NONE
 * Cluster : A7XX_CLUSTER_NONE
 * Location: A7XX_USPTP
 * pairs   : 5 (Regs:29)
 */
static const u32 gen7_9_0_non_context_tpl1_pipe_none_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['TPL1']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_NONE
 * Location: A7XX_USPTP
 * pairs   : 1 (Regs:1)
 */
static const u32 gen7_9_0_non_context_tpl1_pipe_br_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['TPL1']
 * Pipeline: A7XX_PIPE_LPAC
 * Cluster : A7XX_CLUSTER_NONE
 * Location: A7XX_USPTP
 * pairs   : 1 (Regs:1)
 */
static const u32 gen7_9_0_non_context_tpl1_pipe_lpac_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['GRAS']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_GRAS
 * pairs   : 14 (Regs:293)
 */
static const u32 gen7_9_0_gras_pipe_br_cluster_gras_registers[] = …;
static_assert(…);

/*
 * Block   : ['GRAS']
 * Pipeline: A7XX_PIPE_BV
 * Cluster : A7XX_CLUSTER_GRAS
 * pairs   : 14 (Regs:293)
 */
static const u32 gen7_9_0_gras_pipe_bv_cluster_gras_registers[] = …;
static_assert(…);

/*
 * Block   : ['PC']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_FE
 * pairs   : 6 (Regs:31)
 */
static const u32 gen7_9_0_pc_pipe_br_cluster_fe_registers[] = …;
static_assert(…);

/*
 * Block   : ['PC']
 * Pipeline: A7XX_PIPE_BV
 * Cluster : A7XX_CLUSTER_FE
 * pairs   : 6 (Regs:31)
 */
static const u32 gen7_9_0_pc_pipe_bv_cluster_fe_registers[] = …;
static_assert(…);

/*
 * Block   : ['VFD']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_FE
 * pairs   : 2 (Regs:236)
 */
static const u32 gen7_9_0_vfd_pipe_br_cluster_fe_registers[] = …;
static_assert(…);

/*
 * Block   : ['VFD']
 * Pipeline: A7XX_PIPE_BV
 * Cluster : A7XX_CLUSTER_FE
 * pairs   : 2 (Regs:236)
 */
static const u32 gen7_9_0_vfd_pipe_bv_cluster_fe_registers[] = …;
static_assert(…);

/*
 * Block   : ['VPC']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_FE
 * pairs   : 2 (Regs:18)
 */
static const u32 gen7_9_0_vpc_pipe_br_cluster_fe_registers[] = …;
static_assert(…);

/*
 * Block   : ['VPC']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_PC_VS
 * pairs   : 3 (Regs:30)
 */
static const u32 gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers[] = …;
static_assert(…);

/*
 * Block   : ['VPC']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_VPC_PS
 * pairs   : 5 (Regs:76)
 */
static const u32 gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers[] = …;
static_assert(…);

/*
 * Block   : ['VPC']
 * Pipeline: A7XX_PIPE_BV
 * Cluster : A7XX_CLUSTER_FE
 * pairs   : 2 (Regs:18)
 */
static const u32 gen7_9_0_vpc_pipe_bv_cluster_fe_registers[] = …;
static_assert(…);

/*
 * Block   : ['VPC']
 * Pipeline: A7XX_PIPE_BV
 * Cluster : A7XX_CLUSTER_PC_VS
 * pairs   : 3 (Regs:30)
 */
static const u32 gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers[] = …;
static_assert(…);

/*
 * Block   : ['VPC']
 * Pipeline: A7XX_PIPE_BV
 * Cluster : A7XX_CLUSTER_VPC_PS
 * pairs   : 5 (Regs:76)
 */
static const u32 gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers[] = …;
static_assert(…);

/*
 * Block   : ['RB']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_PS
 * pairs   : 39 (Regs:133)
 */
static const u32 gen7_9_0_rb_pipe_br_cluster_ps_rac_registers[] = …;
static_assert(…);

/*
 * Block   : ['RB']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_PS
 * pairs   : 34 (Regs:100)
 */
static const u32 gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_SP_VS
 * Location: A7XX_HLSQ_STATE
 * pairs   : 29 (Regs:215)
 */
static const u32 gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_SP_VS
 * Location: A7XX_SP_TOP
 * pairs   : 22 (Regs:73)
 */
static const u32 gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_SP_VS
 * Location: A7XX_USPTP
 * pairs   : 16 (Regs:269)
 */
static const u32 gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_SP_PS
 * Location: A7XX_HLSQ_STATE
 * pairs   : 21 (Regs:334)
 */
static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_SP_PS
 * Location: A7XX_HLSQ_DP
 * pairs   : 3 (Regs:19)
 */
static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_SP_PS
 * Location: A7XX_SP_TOP
 * pairs   : 18 (Regs:77)
 */
static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_SP_PS
 * Location: A7XX_USPTP
 * pairs   : 17 (Regs:333)
 */
static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_SP_PS
 * Location: A7XX_HLSQ_DP_STR
 * pairs   : 1 (Regs:6)
 */
static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BV
 * Cluster : A7XX_CLUSTER_SP_VS
 * Location: A7XX_HLSQ_STATE
 * pairs   : 28 (Regs:213)
 */
static const u32 gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BV
 * Cluster : A7XX_CLUSTER_SP_VS
 * Location: A7XX_SP_TOP
 * pairs   : 21 (Regs:71)
 */
static const u32 gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_BV
 * Cluster : A7XX_CLUSTER_SP_VS
 * Location: A7XX_USPTP
 * pairs   : 16 (Regs:266)
 */
static const u32 gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_LPAC
 * Cluster : A7XX_CLUSTER_SP_PS
 * Location: A7XX_HLSQ_STATE
 * pairs   : 14 (Regs:299)
 */
static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_state_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_LPAC
 * Cluster : A7XX_CLUSTER_SP_PS
 * Location: A7XX_HLSQ_DP
 * pairs   : 2 (Regs:13)
 */
static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_dp_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_LPAC
 * Cluster : A7XX_CLUSTER_SP_PS
 * Location: A7XX_SP_TOP
 * pairs   : 9 (Regs:34)
 */
static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_sp_top_registers[] = …;
static_assert(…);

/*
 * Block   : ['SP']
 * Pipeline: A7XX_PIPE_LPAC
 * Cluster : A7XX_CLUSTER_SP_PS
 * Location: A7XX_USPTP
 * pairs   : 11 (Regs:279)
 */
static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['TPL1']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_SP_VS
 * Location: A7XX_USPTP
 * pairs   : 3 (Regs:10)
 */
static const u32 gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['TPL1']
 * Pipeline: A7XX_PIPE_BR
 * Cluster : A7XX_CLUSTER_SP_PS
 * Location: A7XX_USPTP
 * pairs   : 6 (Regs:42)
 */
static const u32 gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['TPL1']
 * Pipeline: A7XX_PIPE_BV
 * Cluster : A7XX_CLUSTER_SP_VS
 * Location: A7XX_USPTP
 * pairs   : 3 (Regs:10)
 */
static const u32 gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers[] = …;
static_assert(…);

/*
 * Block   : ['TPL1']
 * Pipeline: A7XX_PIPE_LPAC
 * Cluster : A7XX_CLUSTER_SP_PS
 * Location: A7XX_USPTP
 * pairs   : 5 (Regs:7)
 */
static const u32 gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers[] = …;
static_assert(…);

static const struct gen7_sel_reg gen7_9_0_rb_rac_sel = …;

static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel = …;

static struct gen7_cluster_registers gen7_9_0_clusters[] = …;

static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = …;

static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = …;

static struct gen7_reg_list gen7_9_0_reg_list[] = …;

static const u32 gen7_9_0_cpr_registers[] = …;
static_assert(…);

static const u32 gen7_9_0_dpm_registers[] = …;
static_assert(…);

static const u32 gen7_9_0_dpm_leakage_registers[] = …;
static_assert(…);

static const u32 gen7_9_0_gfx_gpu_acd_registers[] = …;
static_assert(…);

static const u32 gen7_9_0_gpucc_registers[] = …;
static_assert(…);

static const u32 gen7_9_0_isense_registers[] = …;
static_assert(…);

static const u32 gen7_9_0_rscc_registers[] = …;
static_assert(…);

static const u32 *gen7_9_0_external_core_regs[] = …;
#endif /*_ADRENO_GEN7_9_0_SNAPSHOT_H */