// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2024 AIROHA Inc * Author: Lorenzo Bianconi <[email protected]> * Author: Ray Liu <[email protected]> */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/device.h> #include <linux/dma-mapping.h> #include <linux/errno.h> #include <linux/limits.h> #include <linux/math.h> #include <linux/minmax.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/sizes.h> #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> #include <linux/types.h> #include <asm/unaligned.h> /* SPI */ #define REG_SPI_CTRL_BASE … #define REG_SPI_CTRL_READ_MODE … #define REG_SPI_CTRL_READ_IDLE_EN … #define REG_SPI_CTRL_SIDLY … #define REG_SPI_CTRL_CSHEXT … #define REG_SPI_CTRL_CSLEXT … #define REG_SPI_CTRL_MTX_MODE_TOG … #define SPI_CTRL_MTX_MODE_TOG … #define REG_SPI_CTRL_RDCTL_FSM … #define SPI_CTRL_RDCTL_FSM … #define REG_SPI_CTRL_MACMUX_SEL … #define REG_SPI_CTRL_MANUAL_EN … #define SPI_CTRL_MANUAL_EN … #define REG_SPI_CTRL_OPFIFO_EMPTY … #define SPI_CTRL_OPFIFO_EMPTY … #define REG_SPI_CTRL_OPFIFO_WDATA … #define SPI_CTRL_OPFIFO_LEN … #define SPI_CTRL_OPFIFO_OP … #define REG_SPI_CTRL_OPFIFO_FULL … #define SPI_CTRL_OPFIFO_FULL … #define REG_SPI_CTRL_OPFIFO_WR … #define SPI_CTRL_OPFIFO_WR … #define REG_SPI_CTRL_DFIFO_FULL … #define SPI_CTRL_DFIFO_FULL … #define REG_SPI_CTRL_DFIFO_WDATA … #define SPI_CTRL_DFIFO_WDATA … #define REG_SPI_CTRL_DFIFO_EMPTY … #define SPI_CTRL_DFIFO_EMPTY … #define REG_SPI_CTRL_DFIFO_RD … #define SPI_CTRL_DFIFO_RD … #define REG_SPI_CTRL_DFIFO_RDATA … #define SPI_CTRL_DFIFO_RDATA … #define REG_SPI_CTRL_DUMMY … #define SPI_CTRL_CTRL_DUMMY … #define REG_SPI_CTRL_PROBE_SEL … #define REG_SPI_CTRL_INTERRUPT … #define REG_SPI_CTRL_INTERRUPT_EN … #define REG_SPI_CTRL_SI_CK_SEL … #define REG_SPI_CTRL_SW_CFGNANDADDR_VAL … #define REG_SPI_CTRL_SW_CFGNANDADDR_EN … #define REG_SPI_CTRL_SFC_STRAP … #define REG_SPI_CTRL_NFI2SPI_EN … #define SPI_CTRL_NFI2SPI_EN … /* NFI2SPI */ #define REG_SPI_NFI_CNFG … #define SPI_NFI_DMA_MODE … #define SPI_NFI_READ_MODE … #define SPI_NFI_DMA_BURST_EN … #define SPI_NFI_HW_ECC_EN … #define SPI_NFI_AUTO_FDM_EN … #define SPI_NFI_OPMODE … #define REG_SPI_NFI_PAGEFMT … #define SPI_NFI_PAGE_SIZE … #define SPI_NFI_SPARE_SIZE … #define REG_SPI_NFI_CON … #define SPI_NFI_FIFO_FLUSH … #define SPI_NFI_RST … #define SPI_NFI_RD_TRIG … #define SPI_NFI_WR_TRIG … #define SPI_NFI_SEC_NUM … #define REG_SPI_NFI_INTR_EN … #define SPI_NFI_RD_DONE_EN … #define SPI_NFI_WR_DONE_EN … #define SPI_NFI_RST_DONE_EN … #define SPI_NFI_ERASE_DONE_EN … #define SPI_NFI_BUSY_RETURN_EN … #define SPI_NFI_ACCESS_LOCK_EN … #define SPI_NFI_AHB_DONE_EN … #define SPI_NFI_ALL_IRQ_EN … #define REG_SPI_NFI_INTR … #define SPI_NFI_AHB_DONE … #define REG_SPI_NFI_CMD … #define REG_SPI_NFI_ADDR_NOB … #define SPI_NFI_ROW_ADDR_NOB … #define REG_SPI_NFI_STA … #define REG_SPI_NFI_FIFOSTA … #define REG_SPI_NFI_STRADDR … #define REG_SPI_NFI_FDM0L … #define REG_SPI_NFI_FDM0M … #define REG_SPI_NFI_FDM7L … #define REG_SPI_NFI_FDM7M … #define REG_SPI_NFI_FIFODATA0 … #define REG_SPI_NFI_FIFODATA1 … #define REG_SPI_NFI_FIFODATA2 … #define REG_SPI_NFI_FIFODATA3 … #define REG_SPI_NFI_MASTERSTA … #define REG_SPI_NFI_SECCUS_SIZE … #define SPI_NFI_CUS_SEC_SIZE … #define SPI_NFI_CUS_SEC_SIZE_EN … #define REG_SPI_NFI_RD_CTL2 … #define REG_SPI_NFI_RD_CTL3 … #define REG_SPI_NFI_PG_CTL1 … #define SPI_NFI_PG_LOAD_CMD … #define REG_SPI_NFI_PG_CTL2 … #define REG_SPI_NFI_NOR_PROG_ADDR … #define REG_SPI_NFI_NOR_RD_ADDR … #define REG_SPI_NFI_SNF_MISC_CTL … #define SPI_NFI_DATA_READ_WR_MODE … #define REG_SPI_NFI_SNF_MISC_CTL2 … #define SPI_NFI_READ_DATA_BYTE_NUM … #define SPI_NFI_PROG_LOAD_BYTE_NUM … #define REG_SPI_NFI_SNF_STA_CTL1 … #define SPI_NFI_READ_FROM_CACHE_DONE … #define SPI_NFI_LOAD_TO_CACHE_DONE … #define REG_SPI_NFI_SNF_STA_CTL2 … #define REG_SPI_NFI_SNF_NFI_CNFG … #define SPI_NFI_SPI_MODE … /* SPI NAND Protocol OP */ #define SPI_NAND_OP_GET_FEATURE … #define SPI_NAND_OP_SET_FEATURE … #define SPI_NAND_OP_PAGE_READ … #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE … #define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST … #define SPI_NAND_OP_READ_FROM_CACHE_DUAL … #define SPI_NAND_OP_READ_FROM_CACHE_QUAD … #define SPI_NAND_OP_WRITE_ENABLE … #define SPI_NAND_OP_WRITE_DISABLE … #define SPI_NAND_OP_PROGRAM_LOAD_SINGLE … #define SPI_NAND_OP_PROGRAM_LOAD_QUAD … #define SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE … #define SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD … #define SPI_NAND_OP_PROGRAM_EXECUTE … #define SPI_NAND_OP_READ_ID … #define SPI_NAND_OP_BLOCK_ERASE … #define SPI_NAND_OP_RESET … #define SPI_NAND_OP_DIE_SELECT … #define SPI_NAND_CACHE_SIZE … #define SPI_MAX_TRANSFER_SIZE … enum airoha_snand_mode { … }; enum airoha_snand_cs { … }; struct airoha_snand_dev { … }; struct airoha_snand_ctrl { … }; static int airoha_snand_set_fifo_op(struct airoha_snand_ctrl *as_ctrl, u8 op_cmd, int op_len) { … } static int airoha_snand_set_cs(struct airoha_snand_ctrl *as_ctrl, u8 cs) { … } static int airoha_snand_write_data_to_fifo(struct airoha_snand_ctrl *as_ctrl, const u8 *data, int len) { … } static int airoha_snand_read_data_from_fifo(struct airoha_snand_ctrl *as_ctrl, u8 *ptr, int len) { … } static int airoha_snand_set_mode(struct airoha_snand_ctrl *as_ctrl, enum airoha_snand_mode mode) { … } static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd, const u8 *data, int len) { … } static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data, int len) { … } static int airoha_snand_nfi_init(struct airoha_snand_ctrl *as_ctrl) { … } static int airoha_snand_nfi_config(struct airoha_snand_ctrl *as_ctrl) { … } static bool airoha_snand_is_page_ops(const struct spi_mem_op *op) { … } static int airoha_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) { … } static bool airoha_snand_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc) { … } static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf) { … } static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, const void *buf) { … } static int airoha_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) { … } static const struct spi_controller_mem_ops airoha_snand_mem_ops = …; static int airoha_snand_setup(struct spi_device *spi) { … } static void airoha_snand_cleanup(struct spi_device *spi) { … } static int airoha_snand_nfi_setup(struct airoha_snand_ctrl *as_ctrl) { … } static const struct regmap_config spi_ctrl_regmap_config = …; static const struct regmap_config spi_nfi_regmap_config = …; static const struct of_device_id airoha_snand_ids[] = …; MODULE_DEVICE_TABLE(of, airoha_snand_ids); static int airoha_snand_probe(struct platform_device *pdev) { … } static struct platform_driver airoha_snand_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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