#ifndef MDP4_XML #define MDP4_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/display/mdp4.xml ( 21898 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/display/mdp_common.xml ( 3067 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif enum mdp4_pipe { … }; enum mdp4_mixer { … }; enum mdp4_intf { … }; enum mdp4_cursor_format { … }; enum mdp4_frame_format { … }; enum mdp4_scale_unit { … }; enum mdp4_dma { … }; #define MDP4_IRQ_OVERLAY0_DONE … #define MDP4_IRQ_OVERLAY1_DONE … #define MDP4_IRQ_DMA_S_DONE … #define MDP4_IRQ_DMA_E_DONE … #define MDP4_IRQ_DMA_P_DONE … #define MDP4_IRQ_VG1_HISTOGRAM … #define MDP4_IRQ_VG2_HISTOGRAM … #define MDP4_IRQ_PRIMARY_VSYNC … #define MDP4_IRQ_PRIMARY_INTF_UDERRUN … #define MDP4_IRQ_EXTERNAL_VSYNC … #define MDP4_IRQ_EXTERNAL_INTF_UDERRUN … #define MDP4_IRQ_PRIMARY_RDPTR … #define MDP4_IRQ_DMA_P_HISTOGRAM … #define MDP4_IRQ_DMA_S_HISTOGRAM … #define MDP4_IRQ_OVERLAY2_DONE … #define REG_MDP4_VERSION … #define MDP4_VERSION_MINOR__MASK … #define MDP4_VERSION_MINOR__SHIFT … static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) { … } #define MDP4_VERSION_MAJOR__MASK … #define MDP4_VERSION_MAJOR__SHIFT … static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) { … } #define REG_MDP4_OVLP0_KICK … #define REG_MDP4_OVLP1_KICK … #define REG_MDP4_OVLP2_KICK … #define REG_MDP4_DMA_P_KICK … #define REG_MDP4_DMA_S_KICK … #define REG_MDP4_DMA_E_KICK … #define REG_MDP4_DISP_STATUS … #define REG_MDP4_DISP_INTF_SEL … #define MDP4_DISP_INTF_SEL_PRIM__MASK … #define MDP4_DISP_INTF_SEL_PRIM__SHIFT … static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) { … } #define MDP4_DISP_INTF_SEL_SEC__MASK … #define MDP4_DISP_INTF_SEL_SEC__SHIFT … static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) { … } #define MDP4_DISP_INTF_SEL_EXT__MASK … #define MDP4_DISP_INTF_SEL_EXT__SHIFT … static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) { … } #define MDP4_DISP_INTF_SEL_DSI_VIDEO … #define MDP4_DISP_INTF_SEL_DSI_CMD … #define REG_MDP4_RESET_STATUS … #define REG_MDP4_READ_CNFG … #define REG_MDP4_INTR_ENABLE … #define REG_MDP4_INTR_STATUS … #define REG_MDP4_INTR_CLEAR … #define REG_MDP4_EBI2_LCD0 … #define REG_MDP4_EBI2_LCD1 … #define REG_MDP4_PORTMAP_MODE … #define REG_MDP4_CS_CONTROLLER0 … #define REG_MDP4_CS_CONTROLLER1 … #define REG_MDP4_LAYERMIXER2_IN_CFG … #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK … #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT … static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 … #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK … #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT … static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 … #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK … #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT … static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 … #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK … #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT … static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 … #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK … #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT … static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 … #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK … #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT … static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 … #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK … #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT … static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 … #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK … #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT … static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 … #define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD … #define REG_MDP4_LAYERMIXER_IN_CFG … #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK … #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT … static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 … #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK … #define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT … static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 … #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK … #define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT … static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 … #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK … #define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT … static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 … #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK … #define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT … static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 … #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK … #define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT … static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 … #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK … #define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT … static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 … #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK … #define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT … static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val) { … } #define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 … #define REG_MDP4_VG2_SRC_FORMAT … #define REG_MDP4_VG2_CONST_COLOR … #define REG_MDP4_OVERLAY_FLUSH … #define MDP4_OVERLAY_FLUSH_OVLP0 … #define MDP4_OVERLAY_FLUSH_OVLP1 … #define MDP4_OVERLAY_FLUSH_VG1 … #define MDP4_OVERLAY_FLUSH_VG2 … #define MDP4_OVERLAY_FLUSH_RGB1 … #define MDP4_OVERLAY_FLUSH_RGB2 … static inline uint32_t __offset_OVLP(uint32_t idx) { … } #define REG_MDP4_OVLP(i0) … static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { … } static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { … } #define MDP4_OVLP_SIZE_HEIGHT__MASK … #define MDP4_OVLP_SIZE_HEIGHT__SHIFT … static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val) { … } #define MDP4_OVLP_SIZE_WIDTH__MASK … #define MDP4_OVLP_SIZE_WIDTH__SHIFT … static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val) { … } static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { … } static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { … } static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { … } static inline uint32_t __offset_STAGE(uint32_t idx) { … } #define REG_MDP4_OVLP_STAGE(i0, i1) … static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { … } #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK … #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT … static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val) { … } #define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA … #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA … #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK … #define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT … static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val) { … } #define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA … #define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA … #define MDP4_OVLP_STAGE_OP_FG_TRANSP … #define MDP4_OVLP_STAGE_OP_BG_TRANSP … static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { … } static inline uint32_t __offset_STAGE_CO3(uint32_t idx) { … } #define REG_MDP4_OVLP_STAGE_CO3(i0, i1) … static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { … } #define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA … static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { … } static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { … } static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { … } static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { … } static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { … } #define REG_MDP4_OVLP_CSC(i0) … #define REG_MDP4_OVLP_CSC_MV(i0, i1) … static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { … } #define REG_MDP4_OVLP_CSC_PRE_BV(i0, i1) … static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { … } #define REG_MDP4_OVLP_CSC_POST_BV(i0, i1) … static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { … } #define REG_MDP4_OVLP_CSC_PRE_LV(i0, i1) … static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { … } #define REG_MDP4_OVLP_CSC_POST_LV(i0, i1) … static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { … } #define REG_MDP4_DMA_P_OP_MODE … #define REG_MDP4_LUTN(i0) … #define REG_MDP4_LUTN_LUT(i0, i1) … static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { … } #define REG_MDP4_DMA_S_OP_MODE … static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { … } static inline uint32_t __offset_DMA(enum mdp4_dma idx) { … } #define REG_MDP4_DMA(i0) … static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { … } #define MDP4_DMA_CONFIG_G_BPC__MASK … #define MDP4_DMA_CONFIG_G_BPC__SHIFT … static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val) { … } #define MDP4_DMA_CONFIG_B_BPC__MASK … #define MDP4_DMA_CONFIG_B_BPC__SHIFT … static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val) { … } #define MDP4_DMA_CONFIG_R_BPC__MASK … #define MDP4_DMA_CONFIG_R_BPC__SHIFT … static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val) { … } #define MDP4_DMA_CONFIG_PACK_ALIGN_MSB … #define MDP4_DMA_CONFIG_PACK__MASK … #define MDP4_DMA_CONFIG_PACK__SHIFT … static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val) { … } #define MDP4_DMA_CONFIG_DEFLKR_EN … #define MDP4_DMA_CONFIG_DITHER_EN … static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { … } #define MDP4_DMA_SRC_SIZE_HEIGHT__MASK … #define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT … static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val) { … } #define MDP4_DMA_SRC_SIZE_WIDTH__MASK … #define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT … static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val) { … } static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { … } static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { … } static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { … } #define MDP4_DMA_DST_SIZE_HEIGHT__MASK … #define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT … static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val) { … } #define MDP4_DMA_DST_SIZE_WIDTH__MASK … #define MDP4_DMA_DST_SIZE_WIDTH__SHIFT … static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val) { … } static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { … } #define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK … #define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT … static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val) { … } #define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK … #define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT … static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val) { … } static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { … } static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { … } #define MDP4_DMA_CURSOR_POS_X__MASK … #define MDP4_DMA_CURSOR_POS_X__SHIFT … static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val) { … } #define MDP4_DMA_CURSOR_POS_Y__MASK … #define MDP4_DMA_CURSOR_POS_Y__SHIFT … static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val) { … } static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { … } #define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN … #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK … #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT … static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val) { … } #define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN … static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { … } static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { … } static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { … } static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { … } #define REG_MDP4_DMA_CSC(i0) … #define REG_MDP4_DMA_CSC_MV(i0, i1) … static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { … } #define REG_MDP4_DMA_CSC_PRE_BV(i0, i1) … static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { … } #define REG_MDP4_DMA_CSC_POST_BV(i0, i1) … static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { … } #define REG_MDP4_DMA_CSC_PRE_LV(i0, i1) … static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { … } #define REG_MDP4_DMA_CSC_POST_LV(i0, i1) … static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { … } #define REG_MDP4_PIPE(i0) … static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { … } #define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK … #define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT … static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val) { … } #define MDP4_PIPE_SRC_SIZE_WIDTH__MASK … #define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT … static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val) { … } static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { … } #define MDP4_PIPE_SRC_XY_Y__MASK … #define MDP4_PIPE_SRC_XY_Y__SHIFT … static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val) { … } #define MDP4_PIPE_SRC_XY_X__MASK … #define MDP4_PIPE_SRC_XY_X__SHIFT … static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val) { … } static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { … } #define MDP4_PIPE_DST_SIZE_HEIGHT__MASK … #define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT … static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val) { … } #define MDP4_PIPE_DST_SIZE_WIDTH__MASK … #define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT … static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val) { … } static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { … } #define MDP4_PIPE_DST_XY_Y__MASK … #define MDP4_PIPE_DST_XY_Y__SHIFT … static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val) { … } #define MDP4_PIPE_DST_XY_X__MASK … #define MDP4_PIPE_DST_XY_X__SHIFT … static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val) { … } static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { … } static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { … } static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { … } static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { … } static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { … } #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK … #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT … static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val) { … } #define MDP4_PIPE_SRC_STRIDE_A_P1__MASK … #define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT … static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val) { … } static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { … } #define MDP4_PIPE_SRC_STRIDE_B_P2__MASK … #define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT … static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val) { … } #define MDP4_PIPE_SRC_STRIDE_B_P3__MASK … #define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT … static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val) { … } static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { … } #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK … #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT … static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val) { … } #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK … #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT … static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val) { … } static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { … } #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK … #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT … static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) { … } #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK … #define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT … static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) { … } #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK … #define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT … static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) { … } #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK … #define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT … static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) { … } #define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE … #define MDP4_PIPE_SRC_FORMAT_CPP__MASK … #define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT … static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val) { … } #define MDP4_PIPE_SRC_FORMAT_ROTATED_90 … #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK … #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT … static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) { … } #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT … #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB … #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK … #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT … static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val) { … } #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL … #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK … #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT … static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) { … } #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK … #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT … static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val) { … } static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { … } #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK … #define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT … static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val) { … } #define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK … #define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT … static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val) { … } #define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK … #define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT … static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val) { … } #define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK … #define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT … static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val) { … } static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { … } #define MDP4_PIPE_OP_MODE_SCALEX_EN … #define MDP4_PIPE_OP_MODE_SCALEY_EN … #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK … #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT … static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val) { … } #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK … #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT … static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val) { … } #define MDP4_PIPE_OP_MODE_SRC_YCBCR … #define MDP4_PIPE_OP_MODE_DST_YCBCR … #define MDP4_PIPE_OP_MODE_CSC_EN … #define MDP4_PIPE_OP_MODE_FLIP_LR … #define MDP4_PIPE_OP_MODE_FLIP_UD … #define MDP4_PIPE_OP_MODE_DITHER_EN … #define MDP4_PIPE_OP_MODE_IGC_LUT_EN … #define MDP4_PIPE_OP_MODE_DEINT_EN … #define MDP4_PIPE_OP_MODE_DEINT_ODD_REF … static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { … } static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { … } static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { … } static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { … } #define REG_MDP4_PIPE_CSC(i0) … #define REG_MDP4_PIPE_CSC_MV(i0, i1) … static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { … } #define REG_MDP4_PIPE_CSC_PRE_BV(i0, i1) … static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { … } #define REG_MDP4_PIPE_CSC_POST_BV(i0, i1) … static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { … } #define REG_MDP4_PIPE_CSC_PRE_LV(i0, i1) … static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { … } #define REG_MDP4_PIPE_CSC_POST_LV(i0, i1) … static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { … } #define REG_MDP4_LCDC … #define REG_MDP4_LCDC_ENABLE … #define REG_MDP4_LCDC_HSYNC_CTRL … #define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK … #define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT … static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val) { … } #define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK … #define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT … static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val) { … } #define REG_MDP4_LCDC_VSYNC_PERIOD … #define REG_MDP4_LCDC_VSYNC_LEN … #define REG_MDP4_LCDC_DISPLAY_HCTRL … #define MDP4_LCDC_DISPLAY_HCTRL_START__MASK … #define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT … static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val) { … } #define MDP4_LCDC_DISPLAY_HCTRL_END__MASK … #define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT … static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val) { … } #define REG_MDP4_LCDC_DISPLAY_VSTART … #define REG_MDP4_LCDC_DISPLAY_VEND … #define REG_MDP4_LCDC_ACTIVE_HCTL … #define MDP4_LCDC_ACTIVE_HCTL_START__MASK … #define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT … static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val) { … } #define MDP4_LCDC_ACTIVE_HCTL_END__MASK … #define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT … static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val) { … } #define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X … #define REG_MDP4_LCDC_ACTIVE_VSTART … #define REG_MDP4_LCDC_ACTIVE_VEND … #define REG_MDP4_LCDC_BORDER_CLR … #define REG_MDP4_LCDC_UNDERFLOW_CLR … #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK … #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT … static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val) { … } #define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY … #define REG_MDP4_LCDC_HSYNC_SKEW … #define REG_MDP4_LCDC_TEST_CNTL … #define REG_MDP4_LCDC_CTRL_POLARITY … #define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW … #define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW … #define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW … #define REG_MDP4_LCDC_LVDS_INTF_CTL … #define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL … #define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT … #define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP … #define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT … #define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT … #define MDP4_LCDC_LVDS_INTF_CTL_ENABLE … #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN … #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN … #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN … #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN … #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN … #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN … #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN … #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN … #define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN … #define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN … #define REG_MDP4_LCDC_LVDS_MUX_CTL(i0) … static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { … } #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK … #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT … static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val) { … } #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK … #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT … static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val) { … } #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK … #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT … static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val) { … } #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK … #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT … static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val) { … } static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { … } #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK … #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT … static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val) { … } #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK … #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT … static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val) { … } #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK … #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT … static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val) { … } #define REG_MDP4_LCDC_LVDS_PHY_RESET … #define REG_MDP4_LVDS_PHY_PLL_CTRL_0 … #define REG_MDP4_LVDS_PHY_PLL_CTRL_1 … #define REG_MDP4_LVDS_PHY_PLL_CTRL_2 … #define REG_MDP4_LVDS_PHY_PLL_CTRL_3 … #define REG_MDP4_LVDS_PHY_PLL_CTRL_5 … #define REG_MDP4_LVDS_PHY_PLL_CTRL_6 … #define REG_MDP4_LVDS_PHY_PLL_CTRL_7 … #define REG_MDP4_LVDS_PHY_PLL_CTRL_8 … #define REG_MDP4_LVDS_PHY_PLL_CTRL_9 … #define REG_MDP4_LVDS_PHY_PLL_LOCKED … #define REG_MDP4_LVDS_PHY_CFG2 … #define REG_MDP4_LVDS_PHY_CFG0 … #define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE … #define MDP4_LVDS_PHY_CFG0_CHANNEL0 … #define MDP4_LVDS_PHY_CFG0_CHANNEL1 … #define REG_MDP4_DTV … #define REG_MDP4_DTV_ENABLE … #define REG_MDP4_DTV_HSYNC_CTRL … #define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK … #define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT … static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val) { … } #define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK … #define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT … static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val) { … } #define REG_MDP4_DTV_VSYNC_PERIOD … #define REG_MDP4_DTV_VSYNC_LEN … #define REG_MDP4_DTV_DISPLAY_HCTRL … #define MDP4_DTV_DISPLAY_HCTRL_START__MASK … #define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT … static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val) { … } #define MDP4_DTV_DISPLAY_HCTRL_END__MASK … #define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT … static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val) { … } #define REG_MDP4_DTV_DISPLAY_VSTART … #define REG_MDP4_DTV_DISPLAY_VEND … #define REG_MDP4_DTV_ACTIVE_HCTL … #define MDP4_DTV_ACTIVE_HCTL_START__MASK … #define MDP4_DTV_ACTIVE_HCTL_START__SHIFT … static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val) { … } #define MDP4_DTV_ACTIVE_HCTL_END__MASK … #define MDP4_DTV_ACTIVE_HCTL_END__SHIFT … static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val) { … } #define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X … #define REG_MDP4_DTV_ACTIVE_VSTART … #define REG_MDP4_DTV_ACTIVE_VEND … #define REG_MDP4_DTV_BORDER_CLR … #define REG_MDP4_DTV_UNDERFLOW_CLR … #define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK … #define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT … static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val) { … } #define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY … #define REG_MDP4_DTV_HSYNC_SKEW … #define REG_MDP4_DTV_TEST_CNTL … #define REG_MDP4_DTV_CTRL_POLARITY … #define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW … #define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW … #define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW … #define REG_MDP4_DSI … #define REG_MDP4_DSI_ENABLE … #define REG_MDP4_DSI_HSYNC_CTRL … #define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK … #define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT … static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val) { … } #define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK … #define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT … static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val) { … } #define REG_MDP4_DSI_VSYNC_PERIOD … #define REG_MDP4_DSI_VSYNC_LEN … #define REG_MDP4_DSI_DISPLAY_HCTRL … #define MDP4_DSI_DISPLAY_HCTRL_START__MASK … #define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT … static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val) { … } #define MDP4_DSI_DISPLAY_HCTRL_END__MASK … #define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT … static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val) { … } #define REG_MDP4_DSI_DISPLAY_VSTART … #define REG_MDP4_DSI_DISPLAY_VEND … #define REG_MDP4_DSI_ACTIVE_HCTL … #define MDP4_DSI_ACTIVE_HCTL_START__MASK … #define MDP4_DSI_ACTIVE_HCTL_START__SHIFT … static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val) { … } #define MDP4_DSI_ACTIVE_HCTL_END__MASK … #define MDP4_DSI_ACTIVE_HCTL_END__SHIFT … static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val) { … } #define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X … #define REG_MDP4_DSI_ACTIVE_VSTART … #define REG_MDP4_DSI_ACTIVE_VEND … #define REG_MDP4_DSI_BORDER_CLR … #define REG_MDP4_DSI_UNDERFLOW_CLR … #define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK … #define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT … static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val) { … } #define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY … #define REG_MDP4_DSI_HSYNC_SKEW … #define REG_MDP4_DSI_TEST_CNTL … #define REG_MDP4_DSI_CTRL_POLARITY … #define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW … #define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW … #define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW … #ifdef __cplusplus #endif #endif /* MDP4_XML */
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