linux/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#define SWSMU_CODE_LAYER_L2

#include <linux/firmware.h>
#include <linux/pci.h>
#include <linux/i2c.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "amdgpu_atombios.h"
#include "smu_v14_0.h"
#include "smu14_driver_if_v14_0.h"
#include "soc15_common.h"
#include "atom.h"
#include "smu_v14_0_2_ppt.h"
#include "smu_v14_0_2_pptable.h"
#include "smu_v14_0_2_ppsmc.h"
#include "mp/mp_14_0_2_offset.h"
#include "mp/mp_14_0_2_sh_mask.h"

#include "smu_cmn.h"
#include "amdgpu_ras.h"

/*
 * DO NOT use these for err/warn/info/debug messages.
 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
 * They are more MGPU friendly.
 */
#undef pr_err
#undef pr_warn
#undef pr_info
#undef pr_debug

#define to_amdgpu_device(x)

#define FEATURE_MASK(feature)
#define SMC_DPM_FEATURE

#define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE
#define DEBUGSMC_MSG_Mode1Reset
#define LINK_SPEED_MAX

static struct cmn2asic_msg_mapping smu_v14_0_2_message_map[SMU_MSG_MAX_COUNT] =;

static struct cmn2asic_mapping smu_v14_0_2_clk_map[SMU_CLK_COUNT] =;

static struct cmn2asic_mapping smu_v14_0_2_feature_mask_map[SMU_FEATURE_COUNT] =;

static struct cmn2asic_mapping smu_v14_0_2_table_map[SMU_TABLE_COUNT] =;

static struct cmn2asic_mapping smu_v14_0_2_pwr_src_map[SMU_POWER_SOURCE_COUNT] =;

static struct cmn2asic_mapping smu_v14_0_2_workload_map[PP_SMC_POWER_PROFILE_COUNT] =;

static const uint8_t smu_v14_0_2_throttler_map[] =;

static int
smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu,
				  uint32_t *feature_mask, uint32_t num)
{}

static int smu_v14_0_2_check_powerplay_table(struct smu_context *smu)
{}

static int smu_v14_0_2_store_powerplay_table(struct smu_context *smu)
{}

#ifndef atom_smc_dpm_info_table_14_0_0
struct atom_smc_dpm_info_table_14_0_0 {};
#endif

static int smu_v14_0_2_append_powerplay_table(struct smu_context *smu)
{}

#if 0
static int smu_v14_0_2_get_pptable_from_pmfw(struct smu_context *smu,
					     void **table,
					     uint32_t *size)
{
	struct smu_table_context *smu_table = &smu->smu_table;
	void *combo_pptable = smu_table->combo_pptable;
	int ret = 0;

	ret = smu_cmn_get_combo_pptable(smu);
	if (ret)
		return ret;

	*table = combo_pptable;
	*size = sizeof(struct smu_14_0_powerplay_table);

	return 0;
}
#endif

static int smu_v14_0_2_get_pptable_from_pmfw(struct smu_context *smu,
					     void **table,
					     uint32_t *size)
{}

static int smu_v14_0_2_setup_pptable(struct smu_context *smu)
{}

static int smu_v14_0_2_tables_init(struct smu_context *smu)
{}

static int smu_v14_0_2_allocate_dpm_context(struct smu_context *smu)
{}

static int smu_v14_0_2_init_smc_tables(struct smu_context *smu)
{}

static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu)
{}

static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu)
{}

static void smu_v14_0_2_dump_pptable(struct smu_context *smu)
{}

static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics)
{}

#define SMU_14_0_2_BUSY_THRESHOLD
static int smu_v14_0_2_get_smu_metrics_data(struct smu_context *smu,
					    MetricsMember_t member,
					    uint32_t *value)
{}

static int smu_v14_0_2_get_dpm_ultimate_freq(struct smu_context *smu,
					     enum smu_clk_type clk_type,
					     uint32_t *min,
					     uint32_t *max)
{}

static int smu_v14_0_2_read_sensor(struct smu_context *smu,
				   enum amd_pp_sensors sensor,
				   void *data,
				   uint32_t *size)
{}

static int smu_v14_0_2_get_current_clk_freq_by_table(struct smu_context *smu,
						     enum smu_clk_type clk_type,
						     uint32_t *value)
{}

static int smu_v14_0_2_print_clk_levels(struct smu_context *smu,
					enum smu_clk_type clk_type,
					char *buf)
{}

static int smu_v14_0_2_force_clk_levels(struct smu_context *smu,
					enum smu_clk_type clk_type,
					uint32_t mask)
{}

static int smu_v14_0_2_update_pcie_parameters(struct smu_context *smu,
					      uint8_t pcie_gen_cap,
					      uint8_t pcie_width_cap)
{}

static const struct smu_temperature_range smu14_thermal_policy[] =;

static int smu_v14_0_2_get_thermal_temperature_range(struct smu_context *smu,
						     struct smu_temperature_range *range)
{}

static int smu_v14_0_2_populate_umd_state_clk(struct smu_context *smu)
{}

static void smu_v14_0_2_get_unique_id(struct smu_context *smu)
{}

static int smu_v14_0_2_get_power_limit(struct smu_context *smu,
				       uint32_t *current_power_limit,
				       uint32_t *default_power_limit,
				       uint32_t *max_power_limit,
				       uint32_t *min_power_limit)
{}

static int smu_v14_0_2_get_power_profile_mode(struct smu_context *smu,
					      char *buf)
{}

static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu,
					      long *input,
					      uint32_t size)
{}

static int smu_v14_0_2_baco_enter(struct smu_context *smu)
{}

static int smu_v14_0_2_baco_exit(struct smu_context *smu)
{}

static bool smu_v14_0_2_is_mode1_reset_supported(struct smu_context *smu)
{}

static int smu_v14_0_2_i2c_xfer(struct i2c_adapter *i2c_adap,
				   struct i2c_msg *msg, int num_msgs)
{}

static u32 smu_v14_0_2_i2c_func(struct i2c_adapter *adap)
{}

static const struct i2c_algorithm smu_v14_0_2_i2c_algo =;

static const struct i2c_adapter_quirks smu_v14_0_2_i2c_control_quirks =;

static int smu_v14_0_2_i2c_control_init(struct smu_context *smu)
{}

static void smu_v14_0_2_i2c_control_fini(struct smu_context *smu)
{}

static int smu_v14_0_2_set_mp1_state(struct smu_context *smu,
				     enum pp_mp1_state mp1_state)
{}

static int smu_v14_0_2_set_df_cstate(struct smu_context *smu,
				     enum pp_df_cstate state)
{}

static int smu_v14_0_2_mode1_reset(struct smu_context *smu)
{}

static int smu_v14_0_2_mode2_reset(struct smu_context *smu)
{}

static int smu_v14_0_2_enable_gfx_features(struct smu_context *smu)
{}

static void smu_v14_0_2_set_smu_mailbox_registers(struct smu_context *smu)
{}

static int smu_v14_0_2_smu_send_bad_mem_page_num(struct smu_context *smu,
		uint32_t size)
{}

static int smu_v14_0_2_send_bad_mem_channel_flag(struct smu_context *smu,
		uint32_t size)
{}

static ssize_t smu_v14_0_2_get_ecc_info(struct smu_context *smu,
					void *table)
{}

static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu,
					   void **table)
{}

static const struct pptable_funcs smu_v14_0_2_ppt_funcs =;

void smu_v14_0_2_set_ppt_funcs(struct smu_context *smu)
{}