#ifndef MDP5_XML #define MDP5_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/display/mdp5.xml ( 37474 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/display/mdp_common.xml ( 3067 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif enum mdp5_intf_type { … }; enum mdp5_intfnum { … }; enum mdp5_pipe { … }; enum mdp5_format { … }; enum mdp5_ctl_mode { … }; enum mdp5_pack_3d { … }; enum mdp5_scale_filter { … }; enum mdp5_pipe_bwc { … }; enum mdp5_cursor_format { … }; enum mdp5_cursor_alpha { … }; enum mdp5_igc_type { … }; enum mdp5_data_format { … }; enum mdp5_block_size { … }; enum mdp5_rotate_mode { … }; enum mdp5_chroma_downsample_method { … }; #define MDP5_IRQ_WB_0_DONE … #define MDP5_IRQ_WB_1_DONE … #define MDP5_IRQ_WB_2_DONE … #define MDP5_IRQ_PING_PONG_0_DONE … #define MDP5_IRQ_PING_PONG_1_DONE … #define MDP5_IRQ_PING_PONG_2_DONE … #define MDP5_IRQ_PING_PONG_3_DONE … #define MDP5_IRQ_PING_PONG_0_RD_PTR … #define MDP5_IRQ_PING_PONG_1_RD_PTR … #define MDP5_IRQ_PING_PONG_2_RD_PTR … #define MDP5_IRQ_PING_PONG_3_RD_PTR … #define MDP5_IRQ_PING_PONG_0_WR_PTR … #define MDP5_IRQ_PING_PONG_1_WR_PTR … #define MDP5_IRQ_PING_PONG_2_WR_PTR … #define MDP5_IRQ_PING_PONG_3_WR_PTR … #define MDP5_IRQ_PING_PONG_0_AUTO_REF … #define MDP5_IRQ_PING_PONG_1_AUTO_REF … #define MDP5_IRQ_PING_PONG_2_AUTO_REF … #define MDP5_IRQ_PING_PONG_3_AUTO_REF … #define MDP5_IRQ_INTF0_UNDER_RUN … #define MDP5_IRQ_INTF0_VSYNC … #define MDP5_IRQ_INTF1_UNDER_RUN … #define MDP5_IRQ_INTF1_VSYNC … #define MDP5_IRQ_INTF2_UNDER_RUN … #define MDP5_IRQ_INTF2_VSYNC … #define MDP5_IRQ_INTF3_UNDER_RUN … #define MDP5_IRQ_INTF3_VSYNC … #define REG_MDSS_HW_VERSION … #define MDSS_HW_VERSION_STEP__MASK … #define MDSS_HW_VERSION_STEP__SHIFT … static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) { … } #define MDSS_HW_VERSION_MINOR__MASK … #define MDSS_HW_VERSION_MINOR__SHIFT … static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) { … } #define MDSS_HW_VERSION_MAJOR__MASK … #define MDSS_HW_VERSION_MAJOR__SHIFT … static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) { … } #define REG_MDSS_HW_INTR_STATUS … #define MDSS_HW_INTR_STATUS_INTR_MDP … #define MDSS_HW_INTR_STATUS_INTR_DSI0 … #define MDSS_HW_INTR_STATUS_INTR_DSI1 … #define MDSS_HW_INTR_STATUS_INTR_HDMI … #define MDSS_HW_INTR_STATUS_INTR_EDP … #define REG_MDP5_HW_VERSION … #define MDP5_HW_VERSION_STEP__MASK … #define MDP5_HW_VERSION_STEP__SHIFT … static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) { … } #define MDP5_HW_VERSION_MINOR__MASK … #define MDP5_HW_VERSION_MINOR__SHIFT … static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) { … } #define MDP5_HW_VERSION_MAJOR__MASK … #define MDP5_HW_VERSION_MAJOR__SHIFT … static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) { … } #define REG_MDP5_DISP_INTF_SEL … #define MDP5_DISP_INTF_SEL_INTF0__MASK … #define MDP5_DISP_INTF_SEL_INTF0__SHIFT … static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) { … } #define MDP5_DISP_INTF_SEL_INTF1__MASK … #define MDP5_DISP_INTF_SEL_INTF1__SHIFT … static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) { … } #define MDP5_DISP_INTF_SEL_INTF2__MASK … #define MDP5_DISP_INTF_SEL_INTF2__SHIFT … static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) { … } #define MDP5_DISP_INTF_SEL_INTF3__MASK … #define MDP5_DISP_INTF_SEL_INTF3__SHIFT … static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) { … } #define REG_MDP5_INTR_EN … #define REG_MDP5_INTR_STATUS … #define REG_MDP5_INTR_CLEAR … #define REG_MDP5_HIST_INTR_EN … #define REG_MDP5_HIST_INTR_STATUS … #define REG_MDP5_HIST_INTR_CLEAR … #define REG_MDP5_SPARE_0 … #define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN … #define REG_MDP5_SMP_ALLOC_W(i0) … static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { … } #define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK … #define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT … static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val) { … } #define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK … #define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT … static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val) { … } #define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK … #define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT … static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val) { … } #define REG_MDP5_SMP_ALLOC_R(i0) … static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { … } #define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK … #define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT … static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val) { … } #define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK … #define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT … static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val) { … } #define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK … #define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT … static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val) { … } static inline uint32_t __offset_IGC(enum mdp5_igc_type idx) { … } #define REG_MDP5_IGC(i0) … #define REG_MDP5_IGC_LUT(i0, i1) … static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { … } #define MDP5_IGC_LUT_REG_VAL__MASK … #define MDP5_IGC_LUT_REG_VAL__SHIFT … static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val) { … } #define MDP5_IGC_LUT_REG_INDEX_UPDATE … #define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 … #define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 … #define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 … #define REG_MDP5_SPLIT_DPL_EN … #define REG_MDP5_SPLIT_DPL_UPPER … #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL … #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN … #define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX … #define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX … #define REG_MDP5_SPLIT_DPL_LOWER … #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL … #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN … #define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC … #define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC … static inline uint32_t __offset_CTL(uint32_t idx) { … } #define REG_MDP5_CTL(i0) … static inline uint32_t __offset_LAYER(uint32_t idx) { … } #define REG_MDP5_CTL_LAYER(i0, i1) … static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { … } #define MDP5_CTL_LAYER_REG_VIG0__MASK … #define MDP5_CTL_LAYER_REG_VIG0__SHIFT … static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val) { … } #define MDP5_CTL_LAYER_REG_VIG1__MASK … #define MDP5_CTL_LAYER_REG_VIG1__SHIFT … static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val) { … } #define MDP5_CTL_LAYER_REG_VIG2__MASK … #define MDP5_CTL_LAYER_REG_VIG2__SHIFT … static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val) { … } #define MDP5_CTL_LAYER_REG_RGB0__MASK … #define MDP5_CTL_LAYER_REG_RGB0__SHIFT … static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val) { … } #define MDP5_CTL_LAYER_REG_RGB1__MASK … #define MDP5_CTL_LAYER_REG_RGB1__SHIFT … static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val) { … } #define MDP5_CTL_LAYER_REG_RGB2__MASK … #define MDP5_CTL_LAYER_REG_RGB2__SHIFT … static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val) { … } #define MDP5_CTL_LAYER_REG_DMA0__MASK … #define MDP5_CTL_LAYER_REG_DMA0__SHIFT … static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val) { … } #define MDP5_CTL_LAYER_REG_DMA1__MASK … #define MDP5_CTL_LAYER_REG_DMA1__SHIFT … static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val) { … } #define MDP5_CTL_LAYER_REG_BORDER_COLOR … #define MDP5_CTL_LAYER_REG_CURSOR_OUT … #define MDP5_CTL_LAYER_REG_VIG3__MASK … #define MDP5_CTL_LAYER_REG_VIG3__SHIFT … static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val) { … } #define MDP5_CTL_LAYER_REG_RGB3__MASK … #define MDP5_CTL_LAYER_REG_RGB3__SHIFT … static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val) { … } static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { … } #define MDP5_CTL_OP_MODE__MASK … #define MDP5_CTL_OP_MODE__SHIFT … static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val) { … } #define MDP5_CTL_OP_INTF_NUM__MASK … #define MDP5_CTL_OP_INTF_NUM__SHIFT … static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val) { … } #define MDP5_CTL_OP_CMD_MODE … #define MDP5_CTL_OP_PACK_3D_ENABLE … #define MDP5_CTL_OP_PACK_3D__MASK … #define MDP5_CTL_OP_PACK_3D__SHIFT … static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val) { … } static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { … } #define MDP5_CTL_FLUSH_VIG0 … #define MDP5_CTL_FLUSH_VIG1 … #define MDP5_CTL_FLUSH_VIG2 … #define MDP5_CTL_FLUSH_RGB0 … #define MDP5_CTL_FLUSH_RGB1 … #define MDP5_CTL_FLUSH_RGB2 … #define MDP5_CTL_FLUSH_LM0 … #define MDP5_CTL_FLUSH_LM1 … #define MDP5_CTL_FLUSH_LM2 … #define MDP5_CTL_FLUSH_LM3 … #define MDP5_CTL_FLUSH_LM4 … #define MDP5_CTL_FLUSH_DMA0 … #define MDP5_CTL_FLUSH_DMA1 … #define MDP5_CTL_FLUSH_DSPP0 … #define MDP5_CTL_FLUSH_DSPP1 … #define MDP5_CTL_FLUSH_DSPP2 … #define MDP5_CTL_FLUSH_WB … #define MDP5_CTL_FLUSH_CTL … #define MDP5_CTL_FLUSH_VIG3 … #define MDP5_CTL_FLUSH_RGB3 … #define MDP5_CTL_FLUSH_LM5 … #define MDP5_CTL_FLUSH_DSPP3 … #define MDP5_CTL_FLUSH_CURSOR_0 … #define MDP5_CTL_FLUSH_CURSOR_1 … #define MDP5_CTL_FLUSH_CHROMADOWN_0 … #define MDP5_CTL_FLUSH_TIMING_3 … #define MDP5_CTL_FLUSH_TIMING_2 … #define MDP5_CTL_FLUSH_TIMING_1 … #define MDP5_CTL_FLUSH_TIMING_0 … static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { … } static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { … } static inline uint32_t __offset_LAYER_EXT(uint32_t idx) { … } #define REG_MDP5_CTL_LAYER_EXT(i0, i1) … static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { … } #define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3 … #define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3 … #define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3 … #define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3 … #define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3 … #define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3 … #define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3 … #define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3 … #define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3 … #define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3 … #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK … #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT … static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val) { … } #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK … #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT … static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val) { … } static inline uint32_t __offset_PIPE(enum mdp5_pipe idx) { … } #define REG_MDP5_PIPE(i0) … static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { … } #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK … #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT … static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val) { … } #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK … #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT … static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val) { … } #define MDP5_PIPE_OP_MODE_CSC_1_EN … static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { … } #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK … #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val) { … } #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK … #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { … } #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK … #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val) { … } #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK … #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { … } #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK … #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val) { … } #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK … #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { … } #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK … #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val) { … } #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK … #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { … } #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK … #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val) { … } #define REG_MDP5_PIPE_CSC_1_PRE_CLAMP(i0, i1) … static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { … } #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK … #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val) { … } #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK … #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val) { … } #define REG_MDP5_PIPE_CSC_1_POST_CLAMP(i0, i1) … static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { … } #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK … #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val) { … } #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK … #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val) { … } #define REG_MDP5_PIPE_CSC_1_PRE_BIAS(i0, i1) … static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { … } #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK … #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val) { … } #define REG_MDP5_PIPE_CSC_1_POST_BIAS(i0, i1) … static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { … } #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK … #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT … static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { … } #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK … #define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT … static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val) { … } #define MDP5_PIPE_SRC_SIZE_WIDTH__MASK … #define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT … static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { … } #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK … #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT … static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val) { … } #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK … #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT … static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { … } #define MDP5_PIPE_SRC_XY_Y__MASK … #define MDP5_PIPE_SRC_XY_Y__SHIFT … static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val) { … } #define MDP5_PIPE_SRC_XY_X__MASK … #define MDP5_PIPE_SRC_XY_X__SHIFT … static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { … } #define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK … #define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT … static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val) { … } #define MDP5_PIPE_OUT_SIZE_WIDTH__MASK … #define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT … static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { … } #define MDP5_PIPE_OUT_XY_Y__MASK … #define MDP5_PIPE_OUT_XY_Y__SHIFT … static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val) { … } #define MDP5_PIPE_OUT_XY_X__MASK … #define MDP5_PIPE_OUT_XY_X__SHIFT … static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { … } #define MDP5_PIPE_SRC_STRIDE_A_P0__MASK … #define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT … static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val) { … } #define MDP5_PIPE_SRC_STRIDE_A_P1__MASK … #define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT … static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { … } #define MDP5_PIPE_SRC_STRIDE_B_P2__MASK … #define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT … static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val) { … } #define MDP5_PIPE_SRC_STRIDE_B_P3__MASK … #define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT … static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { … } #define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK … #define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT … static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) { … } #define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK … #define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT … static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) { … } #define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK … #define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT … static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) { … } #define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK … #define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT … static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) { … } #define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE … #define MDP5_PIPE_SRC_FORMAT_CPP__MASK … #define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT … static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val) { … } #define MDP5_PIPE_SRC_FORMAT_ROT90 … #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK … #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT … static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) { … } #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT … #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB … #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK … #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT … static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val) { … } #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK … #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT … static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val) { … } static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { … } #define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK … #define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT … static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val) { … } #define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK … #define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT … static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val) { … } #define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK … #define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT … static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val) { … } #define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK … #define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT … static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { … } #define MDP5_PIPE_SRC_OP_MODE_BWC_EN … #define MDP5_PIPE_SRC_OP_MODE_BWC__MASK … #define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT … static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val) { … } #define MDP5_PIPE_SRC_OP_MODE_FLIP_LR … #define MDP5_PIPE_SRC_OP_MODE_FLIP_UD … #define MDP5_PIPE_SRC_OP_MODE_IGC_EN … #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 … #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 … #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE … #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD … #define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE … static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { … } #define MDP5_PIPE_DECIMATION_VERT__MASK … #define MDP5_PIPE_DECIMATION_VERT__SHIFT … static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val) { … } #define MDP5_PIPE_DECIMATION_HORZ__MASK … #define MDP5_PIPE_DECIMATION_HORZ__SHIFT … static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val) { … } static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx) { … } #define REG_MDP5_PIPE_SW_PIX_EXT(i0, i1) … static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { … } #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK … #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT … static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val) { … } #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK … #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT … static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val) { … } #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK … #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT … static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val) { … } #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK … #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT … static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val) { … } static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { … } #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK … #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT … static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val) { … } #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK … #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT … static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val) { … } #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK … #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT … static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val) { … } #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK … #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT … static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val) { … } static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { … } #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK … #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT … static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val) { … } #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK … #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT … static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val) { … } static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { … } #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN … #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN … #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK … #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT … static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val) { … } #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK … #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT … static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val) { … } #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK … #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT … static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val) { … } #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK … #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT … static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val) { … } #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK … #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT … static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val) { … } #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK … #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT … static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val) { … } static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { … } static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { … } static inline uint32_t __offset_LM(uint32_t idx) { … } #define REG_MDP5_LM(i0) … static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { … } #define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA … #define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA … #define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA … #define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA … #define MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA … #define MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA … #define MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA … #define MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT … static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { … } #define MDP5_LM_OUT_SIZE_HEIGHT__MASK … #define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT … static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val) { … } #define MDP5_LM_OUT_SIZE_WIDTH__MASK … #define MDP5_LM_OUT_SIZE_WIDTH__SHIFT … static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val) { … } static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { … } static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { … } static inline uint32_t __offset_BLEND(uint32_t idx) { … } #define REG_MDP5_LM_BLEND(i0, i1) … static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { … } #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK … #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT … static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val) { … } #define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA … #define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA … #define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA … #define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN … #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK … #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT … static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val) { … } #define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA … #define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA … #define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA … #define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN … static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { … } static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { … } #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK … #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT … static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val) { … } #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK … #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT … static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val) { … } static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { … } #define MDP5_LM_CURSOR_SIZE_ROI_W__MASK … #define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT … static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val) { … } #define MDP5_LM_CURSOR_SIZE_ROI_H__MASK … #define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT … static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val) { … } static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { … } #define MDP5_LM_CURSOR_XY_SRC_X__MASK … #define MDP5_LM_CURSOR_XY_SRC_X__SHIFT … static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val) { … } #define MDP5_LM_CURSOR_XY_SRC_Y__MASK … #define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT … static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val) { … } static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { … } #define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK … #define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT … static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val) { … } static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { … } #define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK … #define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT … static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val) { … } static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { … } static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { … } #define MDP5_LM_CURSOR_START_XY_X_START__MASK … #define MDP5_LM_CURSOR_START_XY_X_START__SHIFT … static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val) { … } #define MDP5_LM_CURSOR_START_XY_Y_START__MASK … #define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT … static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val) { … } static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { … } #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN … #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK … #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT … static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val) { … } #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN … static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { … } static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { … } static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { … } static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { … } static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { … } static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { … } static inline uint32_t __offset_DSPP(uint32_t idx) { … } #define REG_MDP5_DSPP(i0) … static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { … } #define MDP5_DSPP_OP_MODE_IGC_LUT_EN … #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK … #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT … static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val) { … } #define MDP5_DSPP_OP_MODE_PCC_EN … #define MDP5_DSPP_OP_MODE_DITHER_EN … #define MDP5_DSPP_OP_MODE_HIST_EN … #define MDP5_DSPP_OP_MODE_AUTO_CLEAR … #define MDP5_DSPP_OP_MODE_HIST_LUT_EN … #define MDP5_DSPP_OP_MODE_PA_EN … #define MDP5_DSPP_OP_MODE_GAMUT_EN … #define MDP5_DSPP_OP_MODE_GAMUT_ORDER … static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { … } static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { … } static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { … } static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { … } static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { … } static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { … } static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { … } static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { … } static inline uint32_t __offset_PP(uint32_t idx) { … } #define REG_MDP5_PP(i0) … static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { … } static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { … } #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK … #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT … static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val) { … } #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN … #define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN … static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { … } static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { … } #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK … #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT … static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val) { … } #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK … #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT … static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val) { … } static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { … } static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { … } #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK … #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT … static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val) { … } #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK … #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT … static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val) { … } static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { … } #define MDP5_PP_SYNC_THRESH_START__MASK … #define MDP5_PP_SYNC_THRESH_START__SHIFT … static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val) { … } #define MDP5_PP_SYNC_THRESH_CONTINUE__MASK … #define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT … static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val) { … } static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { … } static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { … } static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { … } static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { … } static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { … } static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { … } static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { … } static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { … } static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { … } static inline uint32_t __offset_WB(uint32_t idx) { … } #define REG_MDP5_WB(i0) … static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { … } #define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK … #define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT … static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val) { … } #define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK … #define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT … static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val) { … } #define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK … #define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT … static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val) { … } #define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK … #define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT … static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val) { … } #define MDP5_WB_DST_FORMAT_DSTC3_EN … #define MDP5_WB_DST_FORMAT_DST_BPP__MASK … #define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT … static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val) { … } #define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK … #define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT … static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val) { … } #define MDP5_WB_DST_FORMAT_DST_ALPHA_X … #define MDP5_WB_DST_FORMAT_PACK_TIGHT … #define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB … #define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK … #define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT … static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val) { … } #define MDP5_WB_DST_FORMAT_DST_DITHER_EN … #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK … #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT … static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val) { … } #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK … #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT … static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val) { … } #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK … #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT … static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val) { … } static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { … } #define MDP5_WB_DST_OP_MODE_BWC_ENC_EN … #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK … #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT … static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val) { … } #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK … #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT … static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val) { … } #define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK … #define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT … static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val) { … } #define MDP5_WB_DST_OP_MODE_ROT_EN … #define MDP5_WB_DST_OP_MODE_CSC_EN … #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK … #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT … static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val) { … } #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK … #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT … static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val) { … } #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN … #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK … #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT … static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val) { … } #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK … #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT … static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val) { … } #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK … #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT … static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val) { … } static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { … } #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK … #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT … static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val) { … } #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK … #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT … static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val) { … } #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK … #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT … static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val) { … } #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK … #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT … static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val) { … } static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { … } #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK … #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT … static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val) { … } #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK … #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT … static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val) { … } static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { … } #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK … #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT … static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val) { … } #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK … #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT … static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val) { … } static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { … } #define MDP5_WB_OUT_SIZE_DST_W__MASK … #define MDP5_WB_OUT_SIZE_DST_W__SHIFT … static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val) { … } #define MDP5_WB_OUT_SIZE_DST_H__MASK … #define MDP5_WB_OUT_SIZE_DST_H__SHIFT … static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val) { … } static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { … } static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { … } #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK … #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT … static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val) { … } #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK … #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT … static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val) { … } static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { … } #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK … #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT … static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val) { … } #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK … #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT … static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val) { … } static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { … } #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK … #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT … static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val) { … } #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK … #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT … static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val) { … } static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { … } #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK … #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT … static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val) { … } #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK … #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT … static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val) { … } static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { … } #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK … #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT … static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val) { … } #define REG_MDP5_WB_CSC_COMP_PRECLAMP(i0, i1) … static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { … } #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK … #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT … static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val) { … } #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK … #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT … static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val) { … } #define REG_MDP5_WB_CSC_COMP_POSTCLAMP(i0, i1) … static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { … } #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK … #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT … static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val) { … } #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK … #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT … static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val) { … } #define REG_MDP5_WB_CSC_COMP_PREBIAS(i0, i1) … static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { … } #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK … #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT … static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val) { … } #define REG_MDP5_WB_CSC_COMP_POSTBIAS(i0, i1) … static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { … } #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK … #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT … static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val) { … } static inline uint32_t __offset_INTF(uint32_t idx) { … } #define REG_MDP5_INTF(i0) … static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { … } #define MDP5_INTF_HSYNC_CTL_PULSEW__MASK … #define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT … static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val) { … } #define MDP5_INTF_HSYNC_CTL_PERIOD__MASK … #define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT … static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val) { … } static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { … } #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK … #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT … static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val) { … } #define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE … static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { … } #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK … #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT … static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val) { … } static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { … } #define MDP5_INTF_DISPLAY_HCTL_START__MASK … #define MDP5_INTF_DISPLAY_HCTL_START__SHIFT … static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val) { … } #define MDP5_INTF_DISPLAY_HCTL_END__MASK … #define MDP5_INTF_DISPLAY_HCTL_END__SHIFT … static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val) { … } static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { … } #define MDP5_INTF_ACTIVE_HCTL_START__MASK … #define MDP5_INTF_ACTIVE_HCTL_START__SHIFT … static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val) { … } #define MDP5_INTF_ACTIVE_HCTL_END__MASK … #define MDP5_INTF_ACTIVE_HCTL_END__SHIFT … static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val) { … } #define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE … static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { … } #define MDP5_INTF_POLARITY_CTL_HSYNC_LOW … #define MDP5_INTF_POLARITY_CTL_VSYNC_LOW … #define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW … static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { … } static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { … } static inline uint32_t __offset_AD(uint32_t idx) { … } #define REG_MDP5_AD(i0) … static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { … } static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { … } #ifdef __cplusplus #endif #endif /* MDP5_XML */
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