#ifndef DSI_XML #define DSI_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/display/dsi.xml ( 18874 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif enum dsi_traffic_mode { … }; enum dsi_vid_dst_format { … }; enum dsi_rgb_swap { … }; enum dsi_cmd_trigger { … }; enum dsi_cmd_dst_format { … }; enum dsi_lane_swap { … }; enum video_config_bpp { … }; enum video_pattern_sel { … }; enum cmd_mdp_stream0_pattern_sel { … }; enum cmd_dma_pattern_sel { … }; #define DSI_IRQ_CMD_DMA_DONE … #define DSI_IRQ_MASK_CMD_DMA_DONE … #define DSI_IRQ_CMD_MDP_DONE … #define DSI_IRQ_MASK_CMD_MDP_DONE … #define DSI_IRQ_VIDEO_DONE … #define DSI_IRQ_MASK_VIDEO_DONE … #define DSI_IRQ_BTA_DONE … #define DSI_IRQ_MASK_BTA_DONE … #define DSI_IRQ_ERROR … #define DSI_IRQ_MASK_ERROR … #define REG_DSI_6G_HW_VERSION … #define DSI_6G_HW_VERSION_MAJOR__MASK … #define DSI_6G_HW_VERSION_MAJOR__SHIFT … static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) { … } #define DSI_6G_HW_VERSION_MINOR__MASK … #define DSI_6G_HW_VERSION_MINOR__SHIFT … static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) { … } #define DSI_6G_HW_VERSION_STEP__MASK … #define DSI_6G_HW_VERSION_STEP__SHIFT … static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) { … } #define REG_DSI_CTRL … #define DSI_CTRL_ENABLE … #define DSI_CTRL_VID_MODE_EN … #define DSI_CTRL_CMD_MODE_EN … #define DSI_CTRL_LANE0 … #define DSI_CTRL_LANE1 … #define DSI_CTRL_LANE2 … #define DSI_CTRL_LANE3 … #define DSI_CTRL_CLK_EN … #define DSI_CTRL_ECC_CHECK … #define DSI_CTRL_CRC_CHECK … #define REG_DSI_STATUS0 … #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY … #define DSI_STATUS0_CMD_MODE_DMA_BUSY … #define DSI_STATUS0_CMD_MODE_MDP_BUSY … #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY … #define DSI_STATUS0_DSI_BUSY … #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION … #define REG_DSI_FIFO_STATUS … #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW … #define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW … #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW … #define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH … #define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH … #define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW … #define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY … #define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL … #define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW … #define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY … #define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL … #define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW … #define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW … #define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY … #define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL … #define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW … #define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW … #define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY … #define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL … #define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW … #define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW … #define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY … #define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL … #define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW … #define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW … #define REG_DSI_VID_CFG0 … #define DSI_VID_CFG0_VIRT_CHANNEL__MASK … #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT … static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) { … } #define DSI_VID_CFG0_DST_FORMAT__MASK … #define DSI_VID_CFG0_DST_FORMAT__SHIFT … static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) { … } #define DSI_VID_CFG0_TRAFFIC_MODE__MASK … #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT … static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) { … } #define DSI_VID_CFG0_BLLP_POWER_STOP … #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP … #define DSI_VID_CFG0_HSA_POWER_STOP … #define DSI_VID_CFG0_HBP_POWER_STOP … #define DSI_VID_CFG0_HFP_POWER_STOP … #define DSI_VID_CFG0_DATABUS_WIDEN … #define DSI_VID_CFG0_PULSE_MODE_HSA_HE … #define REG_DSI_VID_CFG1 … #define DSI_VID_CFG1_R_SEL … #define DSI_VID_CFG1_G_SEL … #define DSI_VID_CFG1_B_SEL … #define DSI_VID_CFG1_RGB_SWAP__MASK … #define DSI_VID_CFG1_RGB_SWAP__SHIFT … static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) { … } #define REG_DSI_ACTIVE_H … #define DSI_ACTIVE_H_START__MASK … #define DSI_ACTIVE_H_START__SHIFT … static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) { … } #define DSI_ACTIVE_H_END__MASK … #define DSI_ACTIVE_H_END__SHIFT … static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) { … } #define REG_DSI_ACTIVE_V … #define DSI_ACTIVE_V_START__MASK … #define DSI_ACTIVE_V_START__SHIFT … static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) { … } #define DSI_ACTIVE_V_END__MASK … #define DSI_ACTIVE_V_END__SHIFT … static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) { … } #define REG_DSI_TOTAL … #define DSI_TOTAL_H_TOTAL__MASK … #define DSI_TOTAL_H_TOTAL__SHIFT … static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) { … } #define DSI_TOTAL_V_TOTAL__MASK … #define DSI_TOTAL_V_TOTAL__SHIFT … static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) { … } #define REG_DSI_ACTIVE_HSYNC … #define DSI_ACTIVE_HSYNC_START__MASK … #define DSI_ACTIVE_HSYNC_START__SHIFT … static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) { … } #define DSI_ACTIVE_HSYNC_END__MASK … #define DSI_ACTIVE_HSYNC_END__SHIFT … static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) { … } #define REG_DSI_ACTIVE_VSYNC_HPOS … #define DSI_ACTIVE_VSYNC_HPOS_START__MASK … #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT … static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) { … } #define DSI_ACTIVE_VSYNC_HPOS_END__MASK … #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT … static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) { … } #define REG_DSI_ACTIVE_VSYNC_VPOS … #define DSI_ACTIVE_VSYNC_VPOS_START__MASK … #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT … static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) { … } #define DSI_ACTIVE_VSYNC_VPOS_END__MASK … #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT … static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) { … } #define REG_DSI_CMD_DMA_CTRL … #define DSI_CMD_DMA_CTRL_BROADCAST_EN … #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER … #define DSI_CMD_DMA_CTRL_LOW_POWER … #define REG_DSI_CMD_CFG0 … #define DSI_CMD_CFG0_DST_FORMAT__MASK … #define DSI_CMD_CFG0_DST_FORMAT__SHIFT … static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) { … } #define DSI_CMD_CFG0_R_SEL … #define DSI_CMD_CFG0_G_SEL … #define DSI_CMD_CFG0_B_SEL … #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK … #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT … static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) { … } #define DSI_CMD_CFG0_RGB_SWAP__MASK … #define DSI_CMD_CFG0_RGB_SWAP__SHIFT … static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) { … } #define REG_DSI_CMD_CFG1 … #define DSI_CMD_CFG1_WR_MEM_START__MASK … #define DSI_CMD_CFG1_WR_MEM_START__SHIFT … static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) { … } #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK … #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT … static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) { … } #define DSI_CMD_CFG1_INSERT_DCS_COMMAND … #define REG_DSI_DMA_BASE … #define REG_DSI_DMA_LEN … #define REG_DSI_CMD_MDP_STREAM0_CTRL … #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK … #define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT … static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val) { … } #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK … #define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT … static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val) { … } #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK … #define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT … static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val) { … } #define REG_DSI_CMD_MDP_STREAM0_TOTAL … #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK … #define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT … static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val) { … } #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK … #define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT … static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val) { … } #define REG_DSI_CMD_MDP_STREAM1_CTRL … #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK … #define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT … static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val) { … } #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK … #define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT … static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val) { … } #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK … #define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT … static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val) { … } #define REG_DSI_CMD_MDP_STREAM1_TOTAL … #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK … #define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT … static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val) { … } #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK … #define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT … static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val) { … } #define REG_DSI_ACK_ERR_STATUS … #define REG_DSI_RDBK(i0) … static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { … } #define REG_DSI_TRIG_CTRL … #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK … #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT … static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) { … } #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK … #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT … static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) { … } #define DSI_TRIG_CTRL_STREAM__MASK … #define DSI_TRIG_CTRL_STREAM__SHIFT … static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) { … } #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME … #define DSI_TRIG_CTRL_TE … #define REG_DSI_TRIG_DMA … #define REG_DSI_DLN0_PHY_ERR … #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC … #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC … #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL … #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 … #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 … #define REG_DSI_LP_TIMER_CTRL … #define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK … #define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT … static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val) { … } #define DSI_LP_TIMER_CTRL_BTA_TO__MASK … #define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT … static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val) { … } #define REG_DSI_HS_TIMER_CTRL … #define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK … #define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT … static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val) { … } #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK … #define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT … static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val) { … } #define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN … #define REG_DSI_TIMEOUT_STATUS … #define REG_DSI_CLKOUT_TIMING_CTRL … #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK … #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT … static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) { … } #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK … #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT … static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) { … } #define REG_DSI_EOT_PACKET_CTRL … #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND … #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE … #define REG_DSI_LANE_STATUS … #define DSI_LANE_STATUS_DLN0_STOPSTATE … #define DSI_LANE_STATUS_DLN1_STOPSTATE … #define DSI_LANE_STATUS_DLN2_STOPSTATE … #define DSI_LANE_STATUS_DLN3_STOPSTATE … #define DSI_LANE_STATUS_CLKLN_STOPSTATE … #define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT … #define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT … #define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT … #define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT … #define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT … #define DSI_LANE_STATUS_DLN0_DIRECTION … #define REG_DSI_LANE_CTRL … #define DSI_LANE_CTRL_HS_REQ_SEL_PHY … #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST … #define REG_DSI_LANE_SWAP_CTRL … #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK … #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT … static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) { … } #define REG_DSI_ERR_INT_MASK0 … #define REG_DSI_INTR_CTRL … #define REG_DSI_RESET … #define REG_DSI_CLK_CTRL … #define DSI_CLK_CTRL_AHBS_HCLK_ON … #define DSI_CLK_CTRL_AHBM_SCLK_ON … #define DSI_CLK_CTRL_PCLK_ON … #define DSI_CLK_CTRL_DSICLK_ON … #define DSI_CLK_CTRL_BYTECLK_ON … #define DSI_CLK_CTRL_ESCCLK_ON … #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK … #define REG_DSI_CLK_STATUS … #define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE … #define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE … #define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE … #define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE … #define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE … #define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE … #define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE … #define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE … #define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE … #define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE … #define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE … #define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE … #define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE … #define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE … #define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT … #define DSI_CLK_STATUS_PLL_UNLOCKED … #define REG_DSI_PHY_RESET … #define DSI_PHY_RESET_RESET … #define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL … #define REG_DSI_TPG_MAIN_CONTROL … #define DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN … #define REG_DSI_TPG_VIDEO_CONFIG … #define DSI_TPG_VIDEO_CONFIG_BPP__MASK … #define DSI_TPG_VIDEO_CONFIG_BPP__SHIFT … static inline uint32_t DSI_TPG_VIDEO_CONFIG_BPP(enum video_config_bpp val) { … } #define DSI_TPG_VIDEO_CONFIG_RGB … #define REG_DSI_TEST_PATTERN_GEN_CTRL … #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK … #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT … static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL(enum cmd_dma_pattern_sel val) { … } #define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK … #define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT … static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(enum cmd_mdp_stream0_pattern_sel val) { … } #define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK … #define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT … static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(enum video_pattern_sel val) { … } #define DSI_TEST_PATTERN_GEN_CTRL_TPG_DMA_FIFO_MODE … #define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_TPG_EN … #define DSI_TEST_PATTERN_GEN_CTRL_EN … #define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 … #define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER … #define DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER … #define REG_DSI_TPG_MAIN_CONTROL2 … #define DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN … #define DSI_TPG_MAIN_CONTROL2_CMD_MDP1_CHECKERED_RECTANGLE_PATTERN … #define DSI_TPG_MAIN_CONTROL2_CMD_MDP2_CHECKERED_RECTANGLE_PATTERN … #define REG_DSI_T_CLK_PRE_EXTEND … #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK … #define REG_DSI_CMD_MODE_MDP_CTRL2 … #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK … #define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT … static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val) { … } #define DSI_CMD_MODE_MDP_CTRL2_R_SEL … #define DSI_CMD_MODE_MDP_CTRL2_G_SEL … #define DSI_CMD_MODE_MDP_CTRL2_B_SEL … #define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP … #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK … #define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT … static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val) { … } #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK … #define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT … static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val) { … } #define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE … #define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN … #define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL … #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK … #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT … static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val) { … } #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK … #define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT … static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val) { … } #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK … #define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT … static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val) { … } #define REG_DSI_RDBK_DATA_CTRL … #define DSI_RDBK_DATA_CTRL_COUNT__MASK … #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT … static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) { … } #define DSI_RDBK_DATA_CTRL_CLR … #define REG_DSI_VERSION … #define DSI_VERSION_MAJOR__MASK … #define DSI_VERSION_MAJOR__SHIFT … static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) { … } #define REG_DSI_CPHY_MODE_CTRL … #define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL … #define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK … #define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT … static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(uint32_t val) { … } #define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK … #define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT … static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(uint32_t val) { … } #define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK … #define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT … static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(uint32_t val) { … } #define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK … #define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT … static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(uint32_t val) { … } #define DSI_VIDEO_COMPRESSION_MODE_CTRL_EN … #define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL … #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK … #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT … static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE(uint32_t val) { … } #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK … #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT … static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE(uint32_t val) { … } #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK … #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT … static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM(uint32_t val) { … } #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EN … #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK … #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT … static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(uint32_t val) { … } #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK … #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT … static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE(uint32_t val) { … } #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK … #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT … static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM(uint32_t val) { … } #define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EN … #define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 … #define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK … #define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT … static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH(uint32_t val) { … } #define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK … #define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT … static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(uint32_t val) { … } #ifdef __cplusplus #endif #endif /* DSI_XML */
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