#ifndef DSI_PHY_20NM_XML #define DSI_PHY_20NM_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/display/dsi_phy_20nm.xml ( 3722 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif #define REG_DSI_20nm_PHY_LN(i0) … static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { … } static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { … } static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { … } static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { … } static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { … } static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { … } static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { … } static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { … } static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { … } #define REG_DSI_20nm_PHY_LNCK_CFG_0 … #define REG_DSI_20nm_PHY_LNCK_CFG_1 … #define REG_DSI_20nm_PHY_LNCK_CFG_2 … #define REG_DSI_20nm_PHY_LNCK_CFG_3 … #define REG_DSI_20nm_PHY_LNCK_CFG_4 … #define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH … #define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL … #define REG_DSI_20nm_PHY_LNCK_TEST_STR0 … #define REG_DSI_20nm_PHY_LNCK_TEST_STR1 … #define REG_DSI_20nm_PHY_TIMING_CTRL_0 … #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK … #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) { … } #define REG_DSI_20nm_PHY_TIMING_CTRL_1 … #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK … #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) { … } #define REG_DSI_20nm_PHY_TIMING_CTRL_2 … #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK … #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) { … } #define REG_DSI_20nm_PHY_TIMING_CTRL_3 … #define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 … #define REG_DSI_20nm_PHY_TIMING_CTRL_4 … #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK … #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) { … } #define REG_DSI_20nm_PHY_TIMING_CTRL_5 … #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK … #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) { … } #define REG_DSI_20nm_PHY_TIMING_CTRL_6 … #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK … #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) { … } #define REG_DSI_20nm_PHY_TIMING_CTRL_7 … #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK … #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) { … } #define REG_DSI_20nm_PHY_TIMING_CTRL_8 … #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK … #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) { … } #define REG_DSI_20nm_PHY_TIMING_CTRL_9 … #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK … #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) { … } #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK … #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) { … } #define REG_DSI_20nm_PHY_TIMING_CTRL_10 … #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK … #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) { … } #define REG_DSI_20nm_PHY_TIMING_CTRL_11 … #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK … #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT … static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) { … } #define REG_DSI_20nm_PHY_CTRL_0 … #define REG_DSI_20nm_PHY_CTRL_1 … #define REG_DSI_20nm_PHY_CTRL_2 … #define REG_DSI_20nm_PHY_CTRL_3 … #define REG_DSI_20nm_PHY_CTRL_4 … #define REG_DSI_20nm_PHY_STRENGTH_0 … #define REG_DSI_20nm_PHY_STRENGTH_1 … #define REG_DSI_20nm_PHY_BIST_CTRL_0 … #define REG_DSI_20nm_PHY_BIST_CTRL_1 … #define REG_DSI_20nm_PHY_BIST_CTRL_2 … #define REG_DSI_20nm_PHY_BIST_CTRL_3 … #define REG_DSI_20nm_PHY_BIST_CTRL_4 … #define REG_DSI_20nm_PHY_BIST_CTRL_5 … #define REG_DSI_20nm_PHY_GLBL_TEST_CTRL … #define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL … #define REG_DSI_20nm_PHY_LDO_CNTRL … #define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 … #define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 … #define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 … #define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 … #define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 … #define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 … #define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG … #ifdef __cplusplus #endif #endif /* DSI_PHY_20NM_XML */
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