#ifndef DSI_PHY_14NM_XML #define DSI_PHY_14NM_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml ( 5391 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif #define REG_DSI_14nm_PHY_CMN_REVISION_ID0 … #define REG_DSI_14nm_PHY_CMN_REVISION_ID1 … #define REG_DSI_14nm_PHY_CMN_REVISION_ID2 … #define REG_DSI_14nm_PHY_CMN_REVISION_ID3 … #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 … #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK … #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT … static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val) { … } #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK … #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT … static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val) { … } #define REG_DSI_14nm_PHY_CMN_CLK_CFG1 … #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL … #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL … #define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL … #define REG_DSI_14nm_PHY_CMN_CTRL_0 … #define REG_DSI_14nm_PHY_CMN_CTRL_1 … #define REG_DSI_14nm_PHY_CMN_HW_TRIGGER … #define REG_DSI_14nm_PHY_CMN_SW_CFG0 … #define REG_DSI_14nm_PHY_CMN_SW_CFG1 … #define REG_DSI_14nm_PHY_CMN_SW_CFG2 … #define REG_DSI_14nm_PHY_CMN_HW_CFG0 … #define REG_DSI_14nm_PHY_CMN_HW_CFG1 … #define REG_DSI_14nm_PHY_CMN_HW_CFG2 … #define REG_DSI_14nm_PHY_CMN_HW_CFG3 … #define REG_DSI_14nm_PHY_CMN_HW_CFG4 … #define REG_DSI_14nm_PHY_CMN_PLL_CNTRL … #define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START … #define REG_DSI_14nm_PHY_CMN_LDO_CNTRL … #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK … #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT … static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val) { … } #define REG_DSI_14nm_PHY_LN(i0) … static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { … } #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK … #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT … static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { … } #define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN … static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { … } #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK … #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT … static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { … } #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK … #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT … static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { … } #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK … #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT … static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { … } #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK … #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT … static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { … } #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK … #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT … static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { … } #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK … #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT … static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val) { … } #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK … #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT … static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { … } #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK … #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT … static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { … } #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK … #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT … static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { … } static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { … } #define REG_DSI_14nm_PHY_PLL_IE_TRIM … #define REG_DSI_14nm_PHY_PLL_IP_TRIM … #define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM … #define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN … #define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET … #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL … #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 … #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 … #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 … #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 … #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 … #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 … #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 … #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 … #define REG_DSI_14nm_PHY_PLL_VREF_CFG1 … #define REG_DSI_14nm_PHY_PLL_KVCO_CODE … #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 … #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 … #define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 … #define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 … #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 … #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 … #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 … #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN … #define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE … #define REG_DSI_14nm_PHY_PLL_DEC_START … #define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER … #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 … #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 … #define REG_DSI_14nm_PHY_PLL_SSC_PER1 … #define REG_DSI_14nm_PHY_PLL_SSC_PER2 … #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 … #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 … #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 … #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 … #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 … #define REG_DSI_14nm_PHY_PLL_TXCLK_EN … #define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL … #define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS … #define REG_DSI_14nm_PHY_PLL_PLL_MISC1 … #define REG_DSI_14nm_PHY_PLL_CP_SET_CUR … #define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET … #define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET … #define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET … #define REG_DSI_14nm_PHY_PLL_PLL_LPF1 … #define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV … #define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP … #ifdef __cplusplus #endif #endif /* DSI_PHY_14NM_XML */
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