#ifndef DSI_PHY_7NM_XML #define DSI_PHY_7NM_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml ( 11017 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif #define REG_DSI_7nm_PHY_CMN_REVISION_ID0 … #define REG_DSI_7nm_PHY_CMN_REVISION_ID1 … #define REG_DSI_7nm_PHY_CMN_REVISION_ID2 … #define REG_DSI_7nm_PHY_CMN_REVISION_ID3 … #define REG_DSI_7nm_PHY_CMN_CLK_CFG0 … #define REG_DSI_7nm_PHY_CMN_CLK_CFG1 … #define REG_DSI_7nm_PHY_CMN_GLBL_CTRL … #define REG_DSI_7nm_PHY_CMN_RBUF_CTRL … #define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 … #define REG_DSI_7nm_PHY_CMN_CTRL_0 … #define REG_DSI_7nm_PHY_CMN_CTRL_1 … #define REG_DSI_7nm_PHY_CMN_CTRL_2 … #define REG_DSI_7nm_PHY_CMN_CTRL_3 … #define REG_DSI_7nm_PHY_CMN_LANE_CFG0 … #define REG_DSI_7nm_PHY_CMN_LANE_CFG1 … #define REG_DSI_7nm_PHY_CMN_PLL_CNTRL … #define REG_DSI_7nm_PHY_CMN_DPHY_SOT … #define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 … #define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 … #define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 … #define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 … #define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 … #define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 … #define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 … #define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 … #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL … #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL … #define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL … #define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL … #define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 … #define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 … #define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL … #define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 … #define REG_DSI_7nm_PHY_CMN_CTRL_4 … #define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 … #define REG_DSI_7nm_PHY_CMN_PHY_STATUS … #define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 … #define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 … #define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10 … #define REG_DSI_7nm_PHY_LN(i0) … static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { … } static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { … } static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { … } static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { … } static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { … } static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { … } static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { … } #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE … #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO … #define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS … #define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO … #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE … #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR … #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE … #define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS … #define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER … #define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER … #define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES … #define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES … #define REG_DSI_7nm_PHY_PLL_CMODE … #define REG_DSI_7nm_PHY_PLL_PSM_CTRL … #define REG_DSI_7nm_PHY_PLL_RSM_CTRL … #define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP … #define REG_DSI_7nm_PHY_PLL_PLL_CNTRL … #define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW … #define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE … #define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH … #define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH … #define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW … #define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH … #define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW … #define REG_DSI_7nm_PHY_PLL_PFILT … #define REG_DSI_7nm_PHY_PLL_IFILT … #define REG_DSI_7nm_PHY_PLL_PLL_GAIN … #define REG_DSI_7nm_PHY_PLL_ICODE_LOW … #define REG_DSI_7nm_PHY_PLL_ICODE_HIGH … #define REG_DSI_7nm_PHY_PLL_LOCKDET … #define REG_DSI_7nm_PHY_PLL_OUTDIV … #define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL … #define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE … #define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO … #define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE … #define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE … #define REG_DSI_7nm_PHY_PLL_RATE_CHANGE … #define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS … #define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO … #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START … #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW … #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID … #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH … #define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES … #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 … #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 … #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 … #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 … #define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 … #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 … #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 … #define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 … #define REG_DSI_7nm_PHY_PLL_MASH_CONTROL … #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW … #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH … #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW … #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH … #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW … #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH … #define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL … #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 … #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 … #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 … #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 … #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 … #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 … #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 … #define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 … #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 … #define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 … #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 … #define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 … #define REG_DSI_7nm_PHY_PLL_SSC_CONTROL … #define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE … #define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 … #define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 … #define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 … #define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 … #define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 … #define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 … #define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 … #define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 … #define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 … #define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 … #define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND … #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID … #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH … #define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX … #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE … #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY … #define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY … #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS … #define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES … #define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 … #define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 … #define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 … #define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE … #define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO … #define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL … #define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW … #define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH … #define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW … #define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH … #define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 … #define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG … #define REG_DSI_7nm_PHY_PLL_FLL_CONFIG … #define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME … #define REG_DSI_7nm_PHY_PLL_FLL_CODE0 … #define REG_DSI_7nm_PHY_PLL_FLL_CODE1 … #define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 … #define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 … #define REG_DSI_7nm_PHY_PLL_SW_RESET … #define REG_DSI_7nm_PHY_PLL_FAST_PWRUP … #define REG_DSI_7nm_PHY_PLL_LOCKTIME0 … #define REG_DSI_7nm_PHY_PLL_LOCKTIME1 … #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL … #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 … #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 … #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 … #define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 … #define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES … #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG … #define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS … #define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS … #define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS … #define REG_DSI_7nm_PHY_PLL_TDC_OFFSET … #define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS … #define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS … #define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS … #define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS … #define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS … #define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 … #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 … #define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 … #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 … #define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 … #define REG_DSI_7nm_PHY_PLL_CMODE_1 … #define REG_DSI_7nm_PHY_PLL_CMODE_2 … #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 … #define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 … #define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE … #ifdef __cplusplus #endif #endif /* DSI_PHY_7NM_XML */
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