/* SPDX-License-Identifier: GPL-2.0 or MIT */ /* Copyright 2018 Marty E. Plummer <[email protected]> */ /* Copyright 2019 Linaro, Ltd, Rob Herring <[email protected]> */ /* Copyright 2023 Collabora ltd. */ /* * Register definitions based on mali_kbase_gpu_regmap.h and * mali_kbase_gpu_regmap_csf.h * (C) COPYRIGHT 2010-2022 ARM Limited. All rights reserved. */ #ifndef __PANTHOR_REGS_H__ #define __PANTHOR_REGS_H__ #define GPU_ID … #define GPU_ARCH_MAJOR(x) … #define GPU_ARCH_MINOR(x) … #define GPU_ARCH_REV(x) … #define GPU_PROD_MAJOR(x) … #define GPU_VER_MAJOR(x) … #define GPU_VER_MINOR(x) … #define GPU_VER_STATUS(x) … #define GPU_L2_FEATURES … #define GPU_L2_FEATURES_LINE_SIZE(x) … #define GPU_CORE_FEATURES … #define GPU_TILER_FEATURES … #define GPU_MEM_FEATURES … #define GROUPS_L2_COHERENT … #define GPU_MMU_FEATURES … #define GPU_MMU_FEATURES_VA_BITS(x) … #define GPU_MMU_FEATURES_PA_BITS(x) … #define GPU_AS_PRESENT … #define GPU_CSF_ID … #define GPU_INT_RAWSTAT … #define GPU_INT_CLEAR … #define GPU_INT_MASK … #define GPU_INT_STAT … #define GPU_IRQ_FAULT … #define GPU_IRQ_PROTM_FAULT … #define GPU_IRQ_RESET_COMPLETED … #define GPU_IRQ_POWER_CHANGED … #define GPU_IRQ_POWER_CHANGED_ALL … #define GPU_IRQ_CLEAN_CACHES_COMPLETED … #define GPU_IRQ_DOORBELL_MIRROR … #define GPU_IRQ_MCU_STATUS_CHANGED … #define GPU_CMD … #define GPU_CMD_DEF(type, payload) … #define GPU_SOFT_RESET … #define GPU_HARD_RESET … #define CACHE_CLEAN … #define CACHE_INV … #define GPU_FLUSH_CACHES(l2, lsc, oth) … #define GPU_STATUS … #define GPU_STATUS_ACTIVE … #define GPU_STATUS_PWR_ACTIVE … #define GPU_STATUS_PAGE_FAULT … #define GPU_STATUS_PROTM_ACTIVE … #define GPU_STATUS_DBG_ENABLED … #define GPU_FAULT_STATUS … #define GPU_FAULT_ADDR_LO … #define GPU_FAULT_ADDR_HI … #define GPU_PWR_KEY … #define GPU_PWR_KEY_UNLOCK … #define GPU_PWR_OVERRIDE0 … #define GPU_PWR_OVERRIDE1 … #define GPU_TIMESTAMP_OFFSET_LO … #define GPU_TIMESTAMP_OFFSET_HI … #define GPU_CYCLE_COUNT_LO … #define GPU_CYCLE_COUNT_HI … #define GPU_TIMESTAMP_LO … #define GPU_TIMESTAMP_HI … #define GPU_THREAD_MAX_THREADS … #define GPU_THREAD_MAX_WORKGROUP_SIZE … #define GPU_THREAD_MAX_BARRIER_SIZE … #define GPU_THREAD_FEATURES … #define GPU_TEXTURE_FEATURES(n) … #define GPU_SHADER_PRESENT_LO … #define GPU_SHADER_PRESENT_HI … #define GPU_TILER_PRESENT_LO … #define GPU_TILER_PRESENT_HI … #define GPU_L2_PRESENT_LO … #define GPU_L2_PRESENT_HI … #define SHADER_READY_LO … #define SHADER_READY_HI … #define TILER_READY_LO … #define TILER_READY_HI … #define L2_READY_LO … #define L2_READY_HI … #define SHADER_PWRON_LO … #define SHADER_PWRON_HI … #define TILER_PWRON_LO … #define TILER_PWRON_HI … #define L2_PWRON_LO … #define L2_PWRON_HI … #define SHADER_PWROFF_LO … #define SHADER_PWROFF_HI … #define TILER_PWROFF_LO … #define TILER_PWROFF_HI … #define L2_PWROFF_LO … #define L2_PWROFF_HI … #define SHADER_PWRTRANS_LO … #define SHADER_PWRTRANS_HI … #define TILER_PWRTRANS_LO … #define TILER_PWRTRANS_HI … #define L2_PWRTRANS_LO … #define L2_PWRTRANS_HI … #define SHADER_PWRACTIVE_LO … #define SHADER_PWRACTIVE_HI … #define TILER_PWRACTIVE_LO … #define TILER_PWRACTIVE_HI … #define L2_PWRACTIVE_LO … #define L2_PWRACTIVE_HI … #define GPU_REVID … #define GPU_COHERENCY_FEATURES … #define GPU_COHERENCY_PROT_BIT(name) … #define GPU_COHERENCY_PROTOCOL … #define GPU_COHERENCY_ACE … #define GPU_COHERENCY_ACE_LITE … #define GPU_COHERENCY_NONE … #define MCU_CONTROL … #define MCU_CONTROL_ENABLE … #define MCU_CONTROL_AUTO … #define MCU_CONTROL_DISABLE … #define MCU_STATUS … #define MCU_STATUS_DISABLED … #define MCU_STATUS_ENABLED … #define MCU_STATUS_HALT … #define MCU_STATUS_FATAL … /* Job Control regs */ #define JOB_INT_RAWSTAT … #define JOB_INT_CLEAR … #define JOB_INT_MASK … #define JOB_INT_STAT … #define JOB_INT_GLOBAL_IF … #define JOB_INT_CSG_IF(x) … /* MMU regs */ #define MMU_INT_RAWSTAT … #define MMU_INT_CLEAR … #define MMU_INT_MASK … #define MMU_INT_STAT … /* AS_COMMAND register commands */ #define MMU_BASE … #define MMU_AS_SHIFT … #define MMU_AS(as) … #define AS_TRANSTAB_LO(as) … #define AS_TRANSTAB_HI(as) … #define AS_MEMATTR_LO(as) … #define AS_MEMATTR_HI(as) … #define AS_MEMATTR_AARCH64_INNER_ALLOC_IMPL … #define AS_MEMATTR_AARCH64_INNER_ALLOC_EXPL(w, r) … #define AS_MEMATTR_AARCH64_SH_MIDGARD_INNER … #define AS_MEMATTR_AARCH64_SH_CPU_INNER … #define AS_MEMATTR_AARCH64_SH_CPU_INNER_SHADER_COH … #define AS_MEMATTR_AARCH64_SHARED … #define AS_MEMATTR_AARCH64_INNER_OUTER_NC … #define AS_MEMATTR_AARCH64_INNER_OUTER_WB … #define AS_MEMATTR_AARCH64_FAULT … #define AS_LOCKADDR_LO(as) … #define AS_LOCKADDR_HI(as) … #define AS_COMMAND(as) … #define AS_COMMAND_NOP … #define AS_COMMAND_UPDATE … #define AS_COMMAND_LOCK … #define AS_COMMAND_UNLOCK … #define AS_COMMAND_FLUSH_PT … #define AS_COMMAND_FLUSH_MEM … #define AS_LOCK_REGION_MIN_SIZE … #define AS_FAULTSTATUS(as) … #define AS_FAULTSTATUS_ACCESS_TYPE_MASK … #define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC … #define AS_FAULTSTATUS_ACCESS_TYPE_EX … #define AS_FAULTSTATUS_ACCESS_TYPE_READ … #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE … #define AS_FAULTADDRESS_LO(as) … #define AS_FAULTADDRESS_HI(as) … #define AS_STATUS(as) … #define AS_STATUS_AS_ACTIVE … #define AS_TRANSCFG_LO(as) … #define AS_TRANSCFG_HI(as) … #define AS_TRANSCFG_ADRMODE_UNMAPPED … #define AS_TRANSCFG_ADRMODE_IDENTITY … #define AS_TRANSCFG_ADRMODE_AARCH64_4K … #define AS_TRANSCFG_ADRMODE_AARCH64_64K … #define AS_TRANSCFG_INA_BITS(x) … #define AS_TRANSCFG_OUTA_BITS(x) … #define AS_TRANSCFG_SL_CONCAT … #define AS_TRANSCFG_PTW_MEMATTR_NC … #define AS_TRANSCFG_PTW_MEMATTR_WB … #define AS_TRANSCFG_PTW_SH_NS … #define AS_TRANSCFG_PTW_SH_OS … #define AS_TRANSCFG_PTW_SH_IS … #define AS_TRANSCFG_PTW_RA … #define AS_TRANSCFG_DISABLE_HIER_AP … #define AS_TRANSCFG_DISABLE_AF_FAULT … #define AS_TRANSCFG_WXN … #define AS_TRANSCFG_XREADABLE … #define AS_FAULTEXTRA_LO(as) … #define AS_FAULTEXTRA_HI(as) … #define CSF_GPU_LATEST_FLUSH_ID … #define CSF_DOORBELL(i) … #define CSF_GLB_DOORBELL_ID … #define gpu_write(dev, reg, data) … #define gpu_read(dev, reg) … #endif
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