dcn30_dpp.h | Explore in Territory

/* Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DCN30_DPP_H__
#define __DCN30_DPP_H__

#include "dcn20/dcn20_dpp.h"

#define TO_DCN30_DPP(dpp) …

#define DPP_REG_LIST_DCN30_COMMON(id) …

#define DPP_REG_LIST_DCN30(id) …

#define DPP_REG_LIST_SH_MASK_DCN30_COMMON(mask_sh) …

#define DPP_REG_LIST_SH_MASK_DCN30_UPDATED(mask_sh) …


#define DPP_REG_LIST_SH_MASK_DCN30(mask_sh) …

#define DPP_REG_FIELD_LIST_DCN3(type) …

struct dcn3_dpp_shift { … };

struct dcn3_dpp_mask { … };

#define DPP_DCN3_REG_VARIABLE_LIST_COMMON …


struct dcn3_dpp_registers { … };


struct dcn3_dpp { … };

bool dpp3_construct(struct dcn3_dpp *dpp3,
	struct dc_context *ctx,
	uint32_t inst,
	const struct dcn3_dpp_registers *tf_regs,
	const struct dcn3_dpp_shift *tf_shift,
	const struct dcn3_dpp_mask *tf_mask);

bool dpp3_program_gamcor_lut(
	struct dpp *dpp_base, const struct pwl_params *params);

void dpp3_program_CM_dealpha(
		struct dpp *dpp_base,
		uint32_t enable, uint32_t additive_blending);

void dpp30_read_state(struct dpp *dpp_base,
		struct dcn_dpp_state *s);

bool dpp3_get_optimal_number_of_taps(
		struct dpp *dpp,
		struct scaler_data *scl_data,
		const struct scaling_taps *in_taps);

void dpp3_cnv_setup(
		struct dpp *dpp_base,
		enum surface_pixel_format format,
		enum expansion_mode mode,
		struct dc_csc_transform input_csc_color_matrix,
		enum dc_color_space input_color_space,
		struct cnv_alpha_2bit_lut *alpha_2bit_lut);

void dpp3_program_CM_bias(
		struct dpp *dpp_base,
		struct CM_bias_params *bias_params);

void dpp3_set_hdr_multiplier(
		struct dpp *dpp_base,
		uint32_t multiplier);

void dpp3_cm_set_gamut_remap(
		struct dpp *dpp_base,
		const struct dpp_grph_csc_adjustment *adjust);

void dpp3_set_pre_degam(struct dpp *dpp_base,
		enum dc_transfer_func_predefined tr);

void dpp3_set_cursor_attributes(
		struct dpp *dpp_base,
		struct dc_cursor_attributes *cursor_attributes);

void dpp3_program_post_csc(
		struct dpp *dpp_base,
		enum dc_color_space color_space,
		enum dcn10_input_csc_select input_select,
		const struct out_csc_color_matrix *tbl_entry);

void dpp3_program_cm_bias(
	struct dpp *dpp_base,
	struct CM_bias_params *bias_params);

void dpp3_program_cm_dealpha(
		struct dpp *dpp_base,
	uint32_t enable, uint32_t additive_blending);

void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,
			     struct dpp_grph_csc_adjustment *adjust);
#endif /* __DC_HWSS_DCN30_H__ */
linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
