/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/delay.h> #include <linux/module.h> #include <linux/slab.h> #include "hwmgr.h" #include "amd_powerplay.h" #include "vega20_smumgr.h" #include "hardwaremanager.h" #include "ppatomfwctrl.h" #include "atomfirmware.h" #include "cgs_common.h" #include "vega20_powertune.h" #include "vega20_inc.h" #include "pppcielanes.h" #include "vega20_hwmgr.h" #include "vega20_processpptables.h" #include "vega20_pptable.h" #include "vega20_thermal.h" #include "vega20_ppsmc.h" #include "pp_debug.h" #include "amd_pcie_helpers.h" #include "ppinterrupt.h" #include "pp_overdriver.h" #include "pp_thermal.h" #include "soc15_common.h" #include "vega20_baco.h" #include "smuio/smuio_9_0_offset.h" #include "smuio/smuio_9_0_sh_mask.h" #include "nbio/nbio_7_4_sh_mask.h" #define smnPCIE_LC_SPEED_CNTL … #define smnPCIE_LC_LINK_WIDTH_CNTL … #define LINK_WIDTH_MAX … #define LINK_SPEED_MAX … static const int link_width[] = …; static const int link_speed[] = …; static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr) { … } static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr) { … } static int vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr) { … } static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) { … } static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) { … } static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr) { … } static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr) { … } static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr) { … } /* * @fn vega20_init_dpm_state * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. * * @param dpm_state - the address of the DPM Table to initiailize. * @return None. */ static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state) { … } static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, PPCLK_e clk_id, uint32_t *num_of_levels) { … } static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, PPCLK_e clk_id, uint32_t index, uint32_t *clk) { … } static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) { … } static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr) { … } static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr) { … } /* * This function is to initialize all DPM state tables * for SMU based on the dependency table. * Dynamic state patching function will then trim these * state tables to the allowed range based * on the power policy or external client requests, * such as UVD request, etc. */ static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) { … } /** * vega20_init_smc_table - Initializes the SMC table and uploads it * * @hwmgr: the address of the powerplay hardware manager. * return: always 0 */ static int vega20_init_smc_table(struct pp_hwmgr *hwmgr) { … } /* * Override PCIe link speed and link width for DPM Level 1. PPTable entries * reflect the ASIC capabilities and not the system capabilities. For e.g. * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch * to DPM1, it fails as system doesn't support Gen4. */ static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr) { … } static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr) { … } static int vega20_run_btc(struct pp_hwmgr *hwmgr) { … } static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr) { … } static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr) { … } static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr) { … } static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr) { … } static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr) { … } static int vega20_od8_set_feature_capabilities( struct pp_hwmgr *hwmgr) { … } static int vega20_od8_set_feature_id( struct pp_hwmgr *hwmgr) { … } static int vega20_od8_get_gfx_clock_base_voltage( struct pp_hwmgr *hwmgr, uint32_t *voltage, uint32_t freq) { … } static int vega20_od8_initialize_default_settings( struct pp_hwmgr *hwmgr) { … } static int vega20_od8_set_settings( struct pp_hwmgr *hwmgr, uint32_t index, uint32_t value) { … } static int vega20_get_sclk_od( struct pp_hwmgr *hwmgr) { … } static int vega20_set_sclk_od( struct pp_hwmgr *hwmgr, uint32_t value) { … } static int vega20_get_mclk_od( struct pp_hwmgr *hwmgr) { … } static int vega20_set_mclk_od( struct pp_hwmgr *hwmgr, uint32_t value) { … } static void vega20_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) { … } static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr, PP_Clock *clock, PPCLK_e clock_select) { … } static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr) { … } static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr) { … } static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr) { … } static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr) { … } static uint32_t vega20_find_lowest_dpm_level( struct vega20_single_dpm_table *table) { … } static uint32_t vega20_find_highest_dpm_level( struct vega20_single_dpm_table *table) { … } static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) { … } static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) { … } static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) { … } static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr, uint32_t *clock, PPCLK_e clock_select, bool max) { … } static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) { … } static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) { … } static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t *metrics_table, bool bypass_cache) { … } static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr, int idx, uint32_t *query) { … } static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr, PPCLK_e clk_id, uint32_t *clk_freq) { … } static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr, int idx, uint32_t *activity_percent) { … } static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx, void *value, int *size) { … } static int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr, struct pp_display_clock_request *clock_req) { … } static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, PHM_PerformanceLevelDesignation designation, uint32_t index, PHM_PerformanceLevel *level) { … } static int vega20_notify_smc_display_config_after_ps_adjustment( struct pp_hwmgr *hwmgr) { … } static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr) { … } static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr) { … } static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr) { … } static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) { … } static int vega20_force_clock_level(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask) { … } static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level) { … } static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr) { … } static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) { … } static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *info) { … } static int vega20_get_sclks(struct pp_hwmgr *hwmgr, struct pp_clock_levels_with_latency *clocks) { … } static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clock) { … } static int vega20_get_memclocks(struct pp_hwmgr *hwmgr, struct pp_clock_levels_with_latency *clocks) { … } static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr, struct pp_clock_levels_with_latency *clocks) { … } static int vega20_get_socclocks(struct pp_hwmgr *hwmgr, struct pp_clock_levels_with_latency *clocks) { … } static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct pp_clock_levels_with_latency *clocks) { … } static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct pp_clock_levels_with_voltage *clocks) { … } static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, void *clock_ranges) { … } static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, enum PP_OD_DPM_TABLE_COMMAND type, long *input, uint32_t size) { … } static int vega20_set_mp1_state(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state) { … } static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) { … } static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) { … } static int vega20_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) { … } static int vega20_get_current_pcie_link_width(struct pp_hwmgr *hwmgr) { … } static int vega20_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) { … } static int vega20_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) { … } static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf) { … } static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, struct vega20_single_dpm_table *dpm_table) { … } static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr) { … } static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr) { … } static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr) { … } static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) { … } static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) { … } static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) { … } static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) { … } static bool vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) { … } static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr) { … } static int vega20_power_off_asic(struct pp_hwmgr *hwmgr) { … } static int conv_power_profile_to_pplib_workload(int power_profile) { … } static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) { … } static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) { … } static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, uint32_t virtual_addr_low, uint32_t virtual_addr_hi, uint32_t mc_addr_low, uint32_t mc_addr_hi, uint32_t size) { … } static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *thermal_data) { … } static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire) { … } static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr, enum pp_df_cstate state) { … } static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr, uint32_t pstate) { … } static void vega20_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) { … } static ssize_t vega20_get_gpu_metrics(struct pp_hwmgr *hwmgr, void **table) { … } static const struct pp_hwmgr_func vega20_hwmgr_funcs = …; int vega20_hwmgr_init(struct pp_hwmgr *hwmgr) { … }
Codebase Browser
linux