/* * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Rafał Miłecki <[email protected]> * Alex Deucher <[email protected]> */ #include "amdgpu.h" #include "amdgpu_drv.h" #include "amdgpu_pm.h" #include "amdgpu_dpm.h" #include "atom.h" #include <linux/pci.h> #include <linux/hwmon.h> #include <linux/hwmon-sysfs.h> #include <linux/nospec.h> #include <linux/pm_runtime.h> #include <asm/processor.h> #define MAX_NUM_OF_FEATURES_PER_SUBSET … #define MAX_NUM_OF_SUBSETS … #define DEVICE_ATTR_IS(_name) … struct od_attribute { … }; struct od_kobj { … }; struct od_feature_ops { … }; struct od_feature_item { … }; struct od_feature_container { … }; struct od_feature_set { … }; static const struct hwmon_temp_label { … } temp_label[] = …; const char * const amdgpu_pp_profile_name[] = …; /** * DOC: power_dpm_state * * The power_dpm_state file is a legacy interface and is only provided for * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting * certain power related parameters. The file power_dpm_state is used for this. * It accepts the following arguments: * * - battery * * - balanced * * - performance * * battery * * On older GPUs, the vbios provided a special power state for battery * operation. Selecting battery switched to this state. This is no * longer provided on newer GPUs so the option does nothing in that case. * * balanced * * On older GPUs, the vbios provided a special power state for balanced * operation. Selecting balanced switched to this state. This is no * longer provided on newer GPUs so the option does nothing in that case. * * performance * * On older GPUs, the vbios provided a special power state for performance * operation. Selecting performance switched to this state. This is no * longer provided on newer GPUs so the option does nothing in that case. * */ static ssize_t amdgpu_get_power_dpm_state(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_power_dpm_state(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } /** * DOC: power_dpm_force_performance_level * * The amdgpu driver provides a sysfs API for adjusting certain power * related parameters. The file power_dpm_force_performance_level is * used for this. It accepts the following arguments: * * - auto * * - low * * - high * * - manual * * - profile_standard * * - profile_min_sclk * * - profile_min_mclk * * - profile_peak * * auto * * When auto is selected, the driver will attempt to dynamically select * the optimal power profile for current conditions in the driver. * * low * * When low is selected, the clocks are forced to the lowest power state. * * high * * When high is selected, the clocks are forced to the highest power state. * * manual * * When manual is selected, the user can manually adjust which power states * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, * and pp_dpm_pcie files and adjust the power state transition heuristics * via the pp_power_profile_mode sysfs file. * * profile_standard * profile_min_sclk * profile_min_mclk * profile_peak * * When the profiling modes are selected, clock and power gating are * disabled and the clocks are set for different profiling cases. This * mode is recommended for profiling specific work loads where you do * not want clock or power gating for clock fluctuation to interfere * with your results. profile_standard sets the clocks to a fixed clock * level which varies from asic to asic. profile_min_sclk forces the sclk * to the lowest level. profile_min_mclk forces the mclk to the lowest level. * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. * */ static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_num_states(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_get_pp_cur_state(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_get_pp_force_state(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_force_state(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } /** * DOC: pp_table * * The amdgpu driver provides a sysfs API for uploading new powerplay * tables. The file pp_table is used for this. Reading the file * will dump the current power play table. Writing to the file * will attempt to upload a new powerplay table and re-initialize * powerplay using that new table. * */ static ssize_t amdgpu_get_pp_table(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_table(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } /** * DOC: pp_od_clk_voltage * * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages * in each power level within a power state. The pp_od_clk_voltage is used for * this. * * Note that the actual memory controller clock rate are exposed, not * the effective memory clock of the DRAMs. To translate it, use the * following formula: * * Clock conversion (Mhz): * * HBM: effective_memory_clock = memory_controller_clock * 1 * * G5: effective_memory_clock = memory_controller_clock * 1 * * G6: effective_memory_clock = memory_controller_clock * 2 * * DRAM data rate (MT/s): * * HBM: effective_memory_clock * 2 = data_rate * * G5: effective_memory_clock * 4 = data_rate * * G6: effective_memory_clock * 8 = data_rate * * Bandwidth (MB/s): * * data_rate * vram_bit_width / 8 = memory_bandwidth * * Some examples: * * G5 on RX460: * * memory_controller_clock = 1750 Mhz * * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz * * data rate = 1750 * 4 = 7000 MT/s * * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s * * G6 on RX5700: * * memory_controller_clock = 875 Mhz * * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz * * data rate = 1750 * 8 = 14000 MT/s * * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s * * < For Vega10 and previous ASICs > * * Reading the file will display: * * - a list of engine clock levels and voltages labeled OD_SCLK * * - a list of memory clock levels and voltages labeled OD_MCLK * * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE * * To manually adjust these settings, first select manual using * power_dpm_force_performance_level. Enter a new value for each * level by writing a string that contains "s/m level clock voltage" to * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at * 810 mV. When you have edited all of the states as needed, write * "c" (commit) to the file to commit your changes. If you want to reset to the * default power levels, write "r" (reset) to the file to reset them. * * * < For Vega20 and newer ASICs > * * Reading the file will display: * * - minimum and maximum engine clock labeled OD_SCLK * * - minimum(not available for Vega20 and Navi1x) and maximum memory * clock labeled OD_MCLK * * - three <frequency, voltage> points labeled OD_VDDC_CURVE. * They can be used to calibrate the sclk voltage curve. This is * available for Vega20 and NV1X. * * - voltage offset(in mV) applied on target voltage calculation. * This is available for Sienna Cichlid, Navy Flounder, Dimgrey * Cavefish and some later SMU13 ASICs. For these ASICs, the target * voltage calculation can be illustrated by "voltage = voltage * calculated from v/f curve + overdrive vddgfx offset" * * - a list of valid ranges for sclk, mclk, voltage curve points * or voltage offset labeled OD_RANGE * * < For APUs > * * Reading the file will display: * * - minimum and maximum engine clock labeled OD_SCLK * * - a list of valid ranges for sclk labeled OD_RANGE * * < For VanGogh > * * Reading the file will display: * * - minimum and maximum engine clock labeled OD_SCLK * - minimum and maximum core clocks labeled OD_CCLK * * - a list of valid ranges for sclk and cclk labeled OD_RANGE * * To manually adjust these settings: * * - First select manual using power_dpm_force_performance_level * * - For clock frequency setting, enter a new value by writing a * string that contains "s/m index clock" to the file. The index * should be 0 if to set minimum clock. And 1 if to set maximum * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. * "m 1 800" will update maximum mclk to be 800Mhz. For core * clocks on VanGogh, the string contains "p core index clock". * E.g., "p 2 0 800" would set the minimum core clock on core * 2 to 800Mhz. * * For sclk voltage curve supported by Vega20 and NV1X, enter the new * values by writing a string that contains "vc point clock voltage" * to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300 * 600" will update point1 with clock set as 300Mhz and voltage as 600mV. * "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and * voltage 1000mV. * * For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey * Cavefish and some later SMU13 ASICs, enter the new value by writing a * string that contains "vo offset". E.g., "vo -10" will update the extra * voltage offset applied to the whole v/f curve line as -10mv. * * - When you have edited all of the states as needed, write "c" (commit) * to the file to commit your changes * * - If you want to reset to the default power levels, write "r" (reset) * to the file to reset them * */ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, struct device_attribute *attr, char *buf) { … } /** * DOC: pp_features * * The amdgpu driver provides a sysfs API for adjusting what powerplay * features to be enabled. The file pp_features is used for this. And * this is only available for Vega10 and later dGPUs. * * Reading back the file will show you the followings: * - Current ppfeature masks * - List of the all supported powerplay features with their naming, * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). * * To manually enable or disable a specific feature, just set or clear * the corresponding bit from original ppfeature masks and input the * new ppfeature masks. */ static ssize_t amdgpu_set_pp_features(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_features(struct device *dev, struct device_attribute *attr, char *buf) { … } /** * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie * * The amdgpu driver provides a sysfs API for adjusting what power levels * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for * this. * * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for * Vega10 and later ASICs. * pp_dpm_fclk interface is only available for Vega20 and later ASICs. * * Reading back the files will show you the available power levels within * the power state and the clock information for those levels. If deep sleep is * applied to a clock, the level will be denoted by a special level 'S:' * E.g., :: * * S: 19Mhz * * 0: 615Mhz * 1: 800Mhz * 2: 888Mhz * 3: 1000Mhz * * * To manually adjust these states, first select manual using * power_dpm_force_performance_level. * Secondly, enter a new value for each level by inputing a string that * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" * E.g., * * .. code-block:: bash * * echo "4 5 6" > pp_dpm_sclk * * will enable sclk levels 4, 5, and 6. * * NOTE: change to the dcefclk max dpm level is not supported now */ static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, enum pp_clock_type type, char *buf) { … } /* * Worst case: 32 bits individually specified, in octal at 12 characters * per line (+1 for \n). */ #define AMDGPU_MASK_BUF_MAX … static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) { … } static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, enum pp_clock_type type, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } /** * DOC: pp_power_profile_mode * * The amdgpu driver provides a sysfs API for adjusting the heuristics * related to switching between power levels in a power state. The file * pp_power_profile_mode is used for this. * * Reading this file outputs a list of all of the predefined power profiles * and the relevant heuristics settings for that profile. * * To select a profile or create a custom profile, first select manual using * power_dpm_force_performance_level. Writing the number of a predefined * profile to pp_power_profile_mode will enable those heuristics. To * create a custom set of heuristics, write a string of numbers to the file * starting with the number of the custom profile along with a setting * for each heuristic parameter. Due to differences across asic families * the heuristic parameters vary from family to family. * */ static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev, enum amd_pp_sensors sensor, void *query) { … } /** * DOC: gpu_busy_percent * * The amdgpu driver provides a sysfs API for reading how busy the GPU * is as a percentage. The file gpu_busy_percent is used for this. * The SMU firmware computes a percentage of load based on the * aggregate activity level in the IP cores. */ static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, struct device_attribute *attr, char *buf) { … } /** * DOC: mem_busy_percent * * The amdgpu driver provides a sysfs API for reading how busy the VRAM * is as a percentage. The file mem_busy_percent is used for this. * The SMU firmware computes a percentage of load based on the * aggregate activity level in the IP cores. */ static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, struct device_attribute *attr, char *buf) { … } /** * DOC: vcn_busy_percent * * The amdgpu driver provides a sysfs API for reading how busy the VCN * is as a percentage. The file vcn_busy_percent is used for this. * The SMU firmware computes a percentage of load based on the * aggregate activity level in the IP cores. */ static ssize_t amdgpu_get_vcn_busy_percent(struct device *dev, struct device_attribute *attr, char *buf) { … } /** * DOC: pcie_bw * * The amdgpu driver provides a sysfs API for estimating how much data * has been received and sent by the GPU in the last second through PCIe. * The file pcie_bw is used for this. * The Perf counters count the number of received and sent messages and return * those values, as well as the maximum payload size of a PCIe packet (mps). * Note that it is not possible to easily and quickly obtain the size of each * packet transmitted, so we output the max payload size (mps) to allow for * quick estimation of the PCIe bandwidth usage */ static ssize_t amdgpu_get_pcie_bw(struct device *dev, struct device_attribute *attr, char *buf) { … } /** * DOC: unique_id * * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU * The file unique_id is used for this. * This will provide a Unique ID that will persist from machine to machine * * NOTE: This will only work for GFX9 and newer. This file will be absent * on unsupported ASICs (GFX8 and older) */ static ssize_t amdgpu_get_unique_id(struct device *dev, struct device_attribute *attr, char *buf) { … } /** * DOC: thermal_throttling_logging * * Thermal throttling pulls down the clock frequency and thus the performance. * It's an useful mechanism to protect the chip from overheating. Since it * impacts performance, the user controls whether it is enabled and if so, * the log frequency. * * Reading back the file shows you the status(enabled or disabled) and * the interval(in seconds) between each thermal logging. * * Writing an integer to the file, sets a new logging interval, in seconds. * The value should be between 1 and 3600. If the value is less than 1, * thermal logging is disabled. Values greater than 3600 are ignored. */ static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } /** * DOC: apu_thermal_cap * * The amdgpu driver provides a sysfs API for retrieving/updating thermal * limit temperature in millidegrees Celsius * * Reading back the file shows you core limit value * * Writing an integer to the file, sets a new thermal limit. The value * should be between 0 and 100. If the value is less than 0 or greater * than 100, then the write request will be ignored. */ static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static int amdgpu_pm_metrics_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, uint32_t mask, enum amdgpu_device_attr_states *states) { … } static ssize_t amdgpu_get_pm_metrics(struct device *dev, struct device_attribute *attr, char *buf) { … } /** * DOC: gpu_metrics * * The amdgpu driver provides a sysfs API for retrieving current gpu * metrics data. The file gpu_metrics is used for this. Reading the * file will dump all the current gpu metrics data. * * These data include temperature, frequency, engines utilization, * power consume, throttler status, fan speed and cpu core statistics( * available for APU only). That's it will give a snapshot of all sensors * at the same time. */ static ssize_t amdgpu_get_gpu_metrics(struct device *dev, struct device_attribute *attr, char *buf) { … } static int amdgpu_show_powershift_percent(struct device *dev, char *buf, enum amd_pp_sensors sensor) { … } /** * DOC: smartshift_apu_power * * The amdgpu driver provides a sysfs API for reporting APU power * shift in percentage if platform supports smartshift. Value 0 means that * there is no powershift and values between [1-100] means that the power * is shifted to APU, the percentage of boost is with respect to APU power * limit on the platform. */ static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr, char *buf) { … } /** * DOC: smartshift_dgpu_power * * The amdgpu driver provides a sysfs API for reporting dGPU power * shift in percentage if platform supports smartshift. Value 0 means that * there is no powershift and values between [1-100] means that the power is * shifted to dGPU, the percentage of boost is with respect to dGPU power * limit on the platform. */ static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr, char *buf) { … } /** * DOC: smartshift_bias * * The amdgpu driver provides a sysfs API for reporting the * smartshift(SS2.0) bias level. The value ranges from -100 to 100 * and the default is 0. -100 sets maximum preference to APU * and 100 sets max perference to dGPU. */ static ssize_t amdgpu_get_smartshift_bias(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_smartshift_bias(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, uint32_t mask, enum amdgpu_device_attr_states *states) { … } static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, uint32_t mask, enum amdgpu_device_attr_states *states) { … } static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, uint32_t mask, enum amdgpu_device_attr_states *states) { … } static int pp_dpm_dcefclk_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, uint32_t mask, enum amdgpu_device_attr_states *states) { … } static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, uint32_t mask, enum amdgpu_device_attr_states *states) { … } /* pm policy attributes */ struct amdgpu_pm_policy_attr { … }; /** * DOC: pm_policy * * Certain SOCs can support different power policies to optimize application * performance. However, this policy is provided only at SOC level and not at a * per-process level. This is useful especially when entire SOC is utilized for * dedicated workload. * * The amdgpu driver provides a sysfs API for selecting the policy. Presently, * only two types of policies are supported through this interface. * * Pstate Policy Selection - This is to select different Pstate profiles which * decides clock/throttling preferences. * * XGMI PLPD Policy Selection - When multiple devices are connected over XGMI, * this helps to select policy to be applied for per link power down. * * The list of available policies and policy levels vary between SOCs. They can * be viewed under pm_policy node directory. If SOC doesn't support any policy, * this node won't be available. The different policies supported will be * available as separate nodes under pm_policy. * * cat /sys/bus/pci/devices/.../pm_policy/<policy_type> * * Reading the policy file shows the different levels supported. The level which * is applied presently is denoted by * (asterisk). E.g., * * .. code-block:: console * * cat /sys/bus/pci/devices/.../pm_policy/soc_pstate * 0 : soc_pstate_default * 1 : soc_pstate_0 * 2 : soc_pstate_1* * 3 : soc_pstate_2 * * cat /sys/bus/pci/devices/.../pm_policy/xgmi_plpd * 0 : plpd_disallow * 1 : plpd_default * 2 : plpd_optimized* * * To apply a specific policy * * "echo <level> > /sys/bus/pci/devices/.../pm_policy/<policy_type>" * * For the levels listed in the example above, to select "plpd_optimized" for * XGMI and "soc_pstate_2" for soc pstate policy - * * .. code-block:: console * * echo "2" > /sys/bus/pci/devices/.../pm_policy/xgmi_plpd * echo "3" > /sys/bus/pci/devices/.../pm_policy/soc_pstate * */ static ssize_t amdgpu_get_pm_policy_attr(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_set_pm_policy_attr(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } #define AMDGPU_PM_POLICY_ATTR(_name, _id) … #define AMDGPU_PM_POLICY_ATTR_VAR(_name) … AMDGPU_PM_POLICY_ATTR(…) AMDGPU_PM_POLICY_ATTR(…) static struct attribute *pm_policy_attrs[] = …; static umode_t amdgpu_pm_policy_attr_visible(struct kobject *kobj, struct attribute *attr, int n) { … } const struct attribute_group amdgpu_pm_policy_attr_group = …; static struct amdgpu_device_attr amdgpu_device_attrs[] = …; static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, uint32_t mask, enum amdgpu_device_attr_states *states) { … } static int amdgpu_device_attr_create(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, uint32_t mask, struct list_head *attr_list) { … } static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) { … } static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, struct list_head *attr_list); static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, struct amdgpu_device_attr *attrs, uint32_t counts, uint32_t mask, struct list_head *attr_list) { … } static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, struct list_head *attr_list) { … } static ssize_t amdgpu_hwmon_show_temp(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, struct device_attribute *attr, char *buf) { … } static int amdgpu_hwmon_get_power(struct device *dev, enum amd_pp_sensors sensor) { … } static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_power_input(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev, struct device_attribute *attr, char *buf, enum pp_power_limit_level pp_limit_level) { … } static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, struct device_attribute *attr, char *buf) { … } static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, struct device_attribute *attr, char *buf) { … } /** * DOC: hwmon * * The amdgpu driver exposes the following sensor interfaces: * * - GPU temperature (via the on-die sensor) * * - GPU voltage * * - Northbridge voltage (APUs only) * * - GPU power * * - GPU fan * * - GPU gfx/compute engine clock * * - GPU memory clock (dGPU only) * * hwmon interfaces for GPU temperature: * * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius * - temp2_input and temp3_input are supported on SOC15 dGPUs only * * - temp[1-3]_label: temperature channel label * - temp2_label and temp3_label are supported on SOC15 dGPUs only * * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only * * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only * * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius * - these are supported on SOC15 dGPUs only * * hwmon interfaces for GPU voltage: * * - in0_input: the voltage on the GPU in millivolts * * - in1_input: the voltage on the Northbridge in millivolts * * hwmon interfaces for GPU power: * * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU. * * - power1_input: instantaneous power used by the SoC in microWatts. On APUs this includes the CPU. * * - power1_cap_min: minimum cap supported in microWatts * * - power1_cap_max: maximum cap supported in microWatts * * - power1_cap: selected power cap in microWatts * * hwmon interfaces for GPU fan: * * - pwm1: pulse width modulation fan level (0-255) * * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) * * - pwm1_min: pulse width modulation fan control minimum level (0) * * - pwm1_max: pulse width modulation fan control maximum level (255) * * - fan1_min: a minimum value Unit: revolution/min (RPM) * * - fan1_max: a maximum value Unit: revolution/max (RPM) * * - fan1_input: fan speed in RPM * * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) * * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable * * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time. * That will get the former one overridden. * * hwmon interfaces for GPU clocks: * * - freq1_input: the gfx/compute clock in hertz * * - freq2_input: the memory clock in hertz * * You can use hwmon tools like sensors to view this information on your system. * */ static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0); static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); static struct attribute *hwmon_attributes[] = …; static umode_t hwmon_attributes_visible(struct kobject *kobj, struct attribute *attr, int index) { … } static const struct attribute_group hwmon_attrgroup = …; static const struct attribute_group *hwmon_groups[] = …; static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev, enum pp_clock_type od_type, char *buf) { … } static int parse_input_od_command_lines(const char *buf, size_t count, u32 *type, long *params, uint32_t *num_of_params) { … } static int amdgpu_distribute_custom_od_settings(struct amdgpu_device *adev, enum PP_OD_DPM_TABLE_COMMAND cmd_type, const char *in_buf, size_t count) { … } /** * DOC: fan_curve * * The amdgpu driver provides a sysfs API for checking and adjusting the fan * control curve line. * * Reading back the file shows you the current settings(temperature in Celsius * degree and fan speed in pwm) applied to every anchor point of the curve line * and their permitted ranges if changable. * * Writing a desired string(with the format like "anchor_point_index temperature * fan_speed_in_pwm") to the file, change the settings for the specific anchor * point accordingly. * * When you have finished the editing, write "c" (commit) to the file to commit * your changes. * * If you want to reset to the default value, write "r" (reset) to the file to * reset them * * There are two fan control modes supported: auto and manual. With auto mode, * PMFW handles the fan speed control(how fan speed reacts to ASIC temperature). * While with manual mode, users can set their own fan curve line as what * described here. Normally the ASIC is booted up with auto mode. Any * settings via this interface will switch the fan control to manual mode * implicitly. */ static ssize_t fan_curve_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { … } static ssize_t fan_curve_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) { … } static umode_t fan_curve_visible(struct amdgpu_device *adev) { … } /** * DOC: acoustic_limit_rpm_threshold * * The amdgpu driver provides a sysfs API for checking and adjusting the * acoustic limit in RPM for fan control. * * Reading back the file shows you the current setting and the permitted * ranges if changable. * * Writing an integer to the file, change the setting accordingly. * * When you have finished the editing, write "c" (commit) to the file to commit * your changes. * * If you want to reset to the default value, write "r" (reset) to the file to * reset them * * This setting works under auto fan control mode only. It adjusts the PMFW's * behavior about the maximum speed in RPM the fan can spin. Setting via this * interface will switch the fan control to auto mode implicitly. */ static ssize_t acoustic_limit_threshold_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { … } static ssize_t acoustic_limit_threshold_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) { … } static umode_t acoustic_limit_threshold_visible(struct amdgpu_device *adev) { … } /** * DOC: acoustic_target_rpm_threshold * * The amdgpu driver provides a sysfs API for checking and adjusting the * acoustic target in RPM for fan control. * * Reading back the file shows you the current setting and the permitted * ranges if changable. * * Writing an integer to the file, change the setting accordingly. * * When you have finished the editing, write "c" (commit) to the file to commit * your changes. * * If you want to reset to the default value, write "r" (reset) to the file to * reset them * * This setting works under auto fan control mode only. It can co-exist with * other settings which can work also under auto mode. It adjusts the PMFW's * behavior about the maximum speed in RPM the fan can spin when ASIC * temperature is not greater than target temperature. Setting via this * interface will switch the fan control to auto mode implicitly. */ static ssize_t acoustic_target_threshold_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { … } static ssize_t acoustic_target_threshold_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) { … } static umode_t acoustic_target_threshold_visible(struct amdgpu_device *adev) { … } /** * DOC: fan_target_temperature * * The amdgpu driver provides a sysfs API for checking and adjusting the * target tempeature in Celsius degree for fan control. * * Reading back the file shows you the current setting and the permitted * ranges if changable. * * Writing an integer to the file, change the setting accordingly. * * When you have finished the editing, write "c" (commit) to the file to commit * your changes. * * If you want to reset to the default value, write "r" (reset) to the file to * reset them * * This setting works under auto fan control mode only. It can co-exist with * other settings which can work also under auto mode. Paring with the * acoustic_target_rpm_threshold setting, they define the maximum speed in * RPM the fan can spin when ASIC temperature is not greater than target * temperature. Setting via this interface will switch the fan control to * auto mode implicitly. */ static ssize_t fan_target_temperature_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { … } static ssize_t fan_target_temperature_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) { … } static umode_t fan_target_temperature_visible(struct amdgpu_device *adev) { … } /** * DOC: fan_minimum_pwm * * The amdgpu driver provides a sysfs API for checking and adjusting the * minimum fan speed in PWM. * * Reading back the file shows you the current setting and the permitted * ranges if changable. * * Writing an integer to the file, change the setting accordingly. * * When you have finished the editing, write "c" (commit) to the file to commit * your changes. * * If you want to reset to the default value, write "r" (reset) to the file to * reset them * * This setting works under auto fan control mode only. It can co-exist with * other settings which can work also under auto mode. It adjusts the PMFW's * behavior about the minimum fan speed in PWM the fan should spin. Setting * via this interface will switch the fan control to auto mode implicitly. */ static ssize_t fan_minimum_pwm_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { … } static ssize_t fan_minimum_pwm_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count) { … } static umode_t fan_minimum_pwm_visible(struct amdgpu_device *adev) { … } static struct od_feature_set amdgpu_od_set = …; static void od_kobj_release(struct kobject *kobj) { … } static const struct kobj_type od_ktype = …; static void amdgpu_od_set_fini(struct amdgpu_device *adev) { … } static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev, struct od_feature_ops *feature_ops) { … } static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev, struct od_feature_container *container) { … } static int amdgpu_od_set_init(struct amdgpu_device *adev) { … } int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) { … } void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) { … } /* * Debugfs info */ #if defined(CONFIG_DEBUG_FS) static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m, struct amdgpu_device *adev) { … } static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) { … } static const struct cg_flag_name clocks[] = …; static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags) { … } static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) { … } DEFINE_SHOW_ATTRIBUTE(…); /* * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW * * Reads debug memory region allocated to PMFW */ static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { … } static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = …; #endif void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) { … }
Codebase Browser
linux