/* * Copyright 2013 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/module.h> #include <linux/pci.h> #include "amdgpu.h" #include "amdgpu_pm.h" #include "amdgpu_dpm.h" #include "amdgpu_atombios.h" #include "amdgpu_dpm_internal.h" #include "amd_pcie.h" #include "sid.h" #include "r600_dpm.h" #include "si_dpm.h" #include "atom.h" #include "../include/pptable.h" #include <linux/math64.h> #include <linux/seq_file.h> #include <linux/firmware.h> #include <legacy_dpm.h> #define MC_CG_ARB_FREQ_F0 … #define MC_CG_ARB_FREQ_F1 … #define MC_CG_ARB_FREQ_F2 … #define MC_CG_ARB_FREQ_F3 … #define SMC_RAM_END … #define SCLK_MIN_DEEPSLEEP_FREQ … /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */ #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 … #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 … #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 … #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 … #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 … #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 … #define BIOS_SCRATCH_4 … MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; MODULE_FIRMWARE(…) …; static const struct amd_pm_funcs si_dpm_funcs; power_info; fan_info; pplib_clock_info; enum si_dpm_auto_throttle_src { … }; enum si_dpm_event_src { … }; static const u32 r600_utc[R600_PM_NUMBER_OF_TC] = …; static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] = …; static const struct si_cac_config_reg cac_weights_tahiti[] = …; static const struct si_cac_config_reg lcac_tahiti[] = …; static const struct si_cac_config_reg cac_override_tahiti[] = …; static const struct si_powertune_data powertune_data_tahiti = …; static const struct si_dte_data dte_data_tahiti = …; static const struct si_dte_data dte_data_tahiti_pro = …; static const struct si_dte_data dte_data_new_zealand = …; static const struct si_dte_data dte_data_aruba_pro = …; static const struct si_dte_data dte_data_malta = …; static const struct si_cac_config_reg cac_weights_pitcairn[] = …; static const struct si_cac_config_reg lcac_pitcairn[] = …; static const struct si_cac_config_reg cac_override_pitcairn[] = …; static const struct si_powertune_data powertune_data_pitcairn = …; static const struct si_dte_data dte_data_pitcairn = …; static const struct si_dte_data dte_data_curacao_xt = …; static const struct si_dte_data dte_data_curacao_pro = …; static const struct si_dte_data dte_data_neptune_xt = …; static const struct si_cac_config_reg cac_weights_chelsea_pro[] = …; static const struct si_cac_config_reg cac_weights_chelsea_xt[] = …; static const struct si_cac_config_reg cac_weights_heathrow[] = …; static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = …; static const struct si_cac_config_reg cac_weights_cape_verde[] = …; static const struct si_cac_config_reg lcac_cape_verde[] = …; static const struct si_cac_config_reg cac_override_cape_verde[] = …; static const struct si_powertune_data powertune_data_cape_verde = …; static const struct si_dte_data dte_data_cape_verde = …; static const struct si_dte_data dte_data_venus_xtx = …; static const struct si_dte_data dte_data_venus_xt = …; static const struct si_dte_data dte_data_venus_pro = …; static const struct si_cac_config_reg cac_weights_oland[] = …; static const struct si_cac_config_reg cac_weights_mars_pro[] = …; static const struct si_cac_config_reg cac_weights_mars_xt[] = …; static const struct si_cac_config_reg cac_weights_oland_pro[] = …; static const struct si_cac_config_reg cac_weights_oland_xt[] = …; static const struct si_cac_config_reg lcac_oland[] = …; static const struct si_cac_config_reg lcac_mars_pro[] = …; static const struct si_cac_config_reg cac_override_oland[] = …; static const struct si_powertune_data powertune_data_oland = …; static const struct si_powertune_data powertune_data_mars_pro = …; static const struct si_dte_data dte_data_oland = …; static const struct si_dte_data dte_data_mars_pro = …; static const struct si_dte_data dte_data_sun_xt = …; static const struct si_cac_config_reg cac_weights_hainan[] = …; static const struct si_powertune_data powertune_data_hainan = …; static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev); static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev); static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev); static struct si_ps *si_get_ps(struct amdgpu_ps *rps); static int si_populate_voltage_value(struct amdgpu_device *adev, const struct atom_voltage_table *table, u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); static int si_get_std_voltage_value(struct amdgpu_device *adev, SISLANDS_SMC_VOLTAGE_VALUE *voltage, u16 *std_voltage); static int si_write_smc_soft_register(struct amdgpu_device *adev, u16 reg_offset, u32 value); static int si_convert_power_level_to_smc(struct amdgpu_device *adev, struct rv7xx_pl *pl, SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); static int si_calculate_sclk_params(struct amdgpu_device *adev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk); static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev); static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev); static void si_dpm_set_irq_funcs(struct amdgpu_device *adev); static struct si_power_info *si_get_pi(struct amdgpu_device *adev) { … } static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, u16 v, s32 t, u32 ileakage, u32 *leakage) { … } static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev, const struct ni_leakage_coeffients *coeff, u16 v, s32 t, u32 i_leakage, u32 *leakage) { … } static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, const u32 fixed_kt, u16 v, u32 ileakage, u32 *leakage) { … } static void si_calculate_leakage_for_v(struct amdgpu_device *adev, const struct ni_leakage_coeffients *coeff, const u32 fixed_kt, u16 v, u32 i_leakage, u32 *leakage) { … } static void si_update_dte_from_pl2(struct amdgpu_device *adev, struct si_dte_data *dte_data) { … } static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev) { … } static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev) { … } static struct si_ps *si_get_ps(struct amdgpu_ps *aps) { … } static void si_initialize_powertune_defaults(struct amdgpu_device *adev) { … } static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev) { … } static u32 si_calculate_cac_wintime(struct amdgpu_device *adev) { … } static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) { … } static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev, bool adjust_polarity, u32 tdp_adjustment, u32 *tdp_limit, u32 *near_tdp_limit) { … } static int si_populate_smc_tdp_limits(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) { … } static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) { … } static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev, const u16 prev_std_vddc, const u16 curr_std_vddc) { … } static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) { … } struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev) { … } static int si_populate_power_containment_values(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) { … } static int si_populate_sq_ramping_values(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) { … } static int si_enable_power_containment(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, bool enable) { … } static int si_initialize_smc_dte_tables(struct amdgpu_device *adev) { … } static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev, u16 *max, u16 *min) { … } static u16 si_get_cac_std_voltage_step(u16 max, u16 min) { … } static int si_init_dte_leakage_table(struct amdgpu_device *adev, PP_SIslands_CacConfig *cac_tables, u16 vddc_max, u16 vddc_min, u16 vddc_step, u16 t0, u16 t_step) { … } static int si_init_simplified_leakage_table(struct amdgpu_device *adev, PP_SIslands_CacConfig *cac_tables, u16 vddc_max, u16 vddc_min, u16 vddc_step) { … } static int si_initialize_smc_cac_tables(struct amdgpu_device *adev) { … } static int si_program_cac_config_registers(struct amdgpu_device *adev, const struct si_cac_config_reg *cac_config_regs) { … } static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev) { … } static int si_enable_smc_cac(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, bool enable) { … } static int si_init_smc_spll_table(struct amdgpu_device *adev) { … } static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev, u16 vce_voltage) { … } static int si_get_vce_clock_voltage(struct amdgpu_device *adev, u32 evclk, u32 ecclk, u16 *voltage) { … } static bool si_dpm_vblank_too_short(void *handle) { … } static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev, u32 arb_freq_src, u32 arb_freq_dest) { … } static void ni_update_current_ps(struct amdgpu_device *adev, struct amdgpu_ps *rps) { … } static void ni_update_requested_ps(struct amdgpu_device *adev, struct amdgpu_ps *rps) { … } static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev, struct amdgpu_ps *new_ps, struct amdgpu_ps *old_ps) { … } static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev, struct amdgpu_ps *new_ps, struct amdgpu_ps *old_ps) { … } static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage) { … } static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks, u32 max_clock, u32 requested_clock) { … } static u32 btc_get_valid_mclk(struct amdgpu_device *adev, u32 max_mclk, u32 requested_mclk) { … } static u32 btc_get_valid_sclk(struct amdgpu_device *adev, u32 max_sclk, u32 requested_sclk) { … } static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table, u32 *max_clock) { … } static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table, u32 clock, u16 max_voltage, u16 *voltage) { … } static void btc_adjust_clock_combinations(struct amdgpu_device *adev, const struct amdgpu_clock_and_voltage_limits *max_limits, struct rv7xx_pl *pl) { … } static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, u16 max_vddc, u16 max_vddci, u16 *vddc, u16 *vddci) { … } static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, u32 *p, u32 *u) { … } static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th) { … } static bool r600_is_uvd_state(u32 class, u32 class2) { … } static u8 rv770_get_memory_module_index(struct amdgpu_device *adev) { … } static void rv770_get_max_vddc(struct amdgpu_device *adev) { … } static void rv770_get_engine_memory_ss(struct amdgpu_device *adev) { … } static void si_apply_state_adjust_rules(struct amdgpu_device *adev, struct amdgpu_ps *rps) { … } #if 0 static int si_read_smc_soft_register(struct amdgpu_device *adev, u16 reg_offset, u32 *value) { struct si_power_info *si_pi = si_get_pi(adev); return amdgpu_si_read_smc_sram_dword(adev, si_pi->soft_regs_start + reg_offset, value, si_pi->sram_end); } #endif static int si_write_smc_soft_register(struct amdgpu_device *adev, u16 reg_offset, u32 value) { … } static bool si_is_special_1gb_platform(struct amdgpu_device *adev) { … } static void si_get_leakage_vddc(struct amdgpu_device *adev) { … } static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev, u32 index, u16 *leakage_voltage) { … } static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) { … } static void si_enable_auto_throttle_source(struct amdgpu_device *adev, enum si_dpm_auto_throttle_src source, bool enable) { … } static void si_start_dpm(struct amdgpu_device *adev) { … } static void si_stop_dpm(struct amdgpu_device *adev) { … } static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable) { … } #if 0 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev, u32 thermal_level) { PPSMC_Result ret; if (thermal_level == 0) { ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); if (ret == PPSMC_Result_OK) return 0; else return -EINVAL; } return 0; } static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev) { si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); } #endif #if 0 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power) { if (ac_power) return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 0 : -EINVAL; return 0; } #endif static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, PPSMC_Msg msg, u32 parameter) { … } static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) { … } static int si_dpm_force_performance_level(void *handle, enum amd_dpm_forced_level level) { … } #if 0 static int si_set_boot_state(struct amdgpu_device *adev) { return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 0 : -EINVAL; } #endif static int si_set_sw_state(struct amdgpu_device *adev) { … } static int si_halt_smc(struct amdgpu_device *adev) { … } static int si_resume_smc(struct amdgpu_device *adev) { … } static void si_dpm_start_smc(struct amdgpu_device *adev) { … } static void si_dpm_stop_smc(struct amdgpu_device *adev) { … } static int si_process_firmware_header(struct amdgpu_device *adev) { … } static void si_read_clock_registers(struct amdgpu_device *adev) { … } static void si_enable_thermal_protection(struct amdgpu_device *adev, bool enable) { … } static void si_enable_acpi_power_management(struct amdgpu_device *adev) { … } #if 0 static int si_enter_ulp_state(struct amdgpu_device *adev) { WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); udelay(25000); return 0; } static int si_exit_ulp_state(struct amdgpu_device *adev) { int i; WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); udelay(7000); for (i = 0; i < adev->usec_timeout; i++) { if (RREG32(SMC_RESP_0) == 1) break; udelay(1000); } return 0; } #endif static int si_notify_smc_display_change(struct amdgpu_device *adev, bool has_display) { … } static void si_program_response_times(struct amdgpu_device *adev) { … } static void si_program_ds_registers(struct amdgpu_device *adev) { … } static void si_program_display_gap(struct amdgpu_device *adev) { … } static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) { … } static void si_setup_bsp(struct amdgpu_device *adev) { … } static void si_program_git(struct amdgpu_device *adev) { … } static void si_program_tp(struct amdgpu_device *adev) { … } static void si_program_tpp(struct amdgpu_device *adev) { … } static void si_program_sstp(struct amdgpu_device *adev) { … } static void si_enable_display_gap(struct amdgpu_device *adev) { … } static void si_program_vc(struct amdgpu_device *adev) { … } static void si_clear_vc(struct amdgpu_device *adev) { … } static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) { … } static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) { … } static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) { … } static int si_upload_firmware(struct amdgpu_device *adev) { … } static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev, const struct atom_voltage_table *table, const struct amdgpu_phase_shedding_limits_table *limits) { … } static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, u32 max_voltage_steps, struct atom_voltage_table *voltage_table) { … } static int si_get_svi2_voltage_table(struct amdgpu_device *adev, struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table, struct atom_voltage_table *voltage_table) { … } static int si_construct_voltage_tables(struct amdgpu_device *adev) { … } static void si_populate_smc_voltage_table(struct amdgpu_device *adev, const struct atom_voltage_table *voltage_table, SISLANDS_SMC_STATETABLE *table) { … } static int si_populate_smc_voltage_tables(struct amdgpu_device *adev, SISLANDS_SMC_STATETABLE *table) { … } static int si_populate_voltage_value(struct amdgpu_device *adev, const struct atom_voltage_table *table, u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) { … } static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, SISLANDS_SMC_VOLTAGE_VALUE *voltage) { … } static int si_get_std_voltage_value(struct amdgpu_device *adev, SISLANDS_SMC_VOLTAGE_VALUE *voltage, u16 *std_voltage) { … } static int si_populate_std_voltage_value(struct amdgpu_device *adev, u16 value, u8 index, SISLANDS_SMC_VOLTAGE_VALUE *voltage) { … } static int si_populate_phase_shedding_value(struct amdgpu_device *adev, const struct amdgpu_phase_shedding_limits_table *limits, u16 voltage, u32 sclk, u32 mclk, SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) { … } static int si_init_arb_table_index(struct amdgpu_device *adev) { … } static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) { … } static int si_reset_to_default(struct amdgpu_device *adev) { … } static int si_force_switch_to_arb_f0(struct amdgpu_device *adev) { … } static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev, u32 engine_clock) { … } static int si_populate_memory_timing_parameters(struct amdgpu_device *adev, struct rv7xx_pl *pl, SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) { … } static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, unsigned int first_arb_set) { … } static int si_program_memory_timing_parameters(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) { … } static int si_populate_initial_mvdd_value(struct amdgpu_device *adev, struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) { … } static int si_populate_smc_initial_state(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_initial_state, SISLANDS_SMC_STATETABLE *table) { … } static enum si_pcie_gen si_gen_pcie_gen_support(struct amdgpu_device *adev, u32 sys_mask, enum si_pcie_gen asic_gen, enum si_pcie_gen default_gen) { … } static int si_populate_smc_acpi_state(struct amdgpu_device *adev, SISLANDS_SMC_STATETABLE *table) { … } static int si_populate_ulv_state(struct amdgpu_device *adev, struct SISLANDS_SMC_SWSTATE_SINGLE *state) { … } static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev) { … } static void si_get_mvdd_configuration(struct amdgpu_device *adev) { … } static int si_init_smc_table(struct amdgpu_device *adev) { … } static int si_calculate_sclk_params(struct amdgpu_device *adev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) { … } static int si_populate_sclk_value(struct amdgpu_device *adev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) { … } static int si_populate_mclk_value(struct amdgpu_device *adev, u32 engine_clock, u32 memory_clock, SISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) { … } static void si_populate_smc_sp(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) { … } static int si_convert_power_level_to_smc(struct amdgpu_device *adev, struct rv7xx_pl *pl, SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) { … } static int si_populate_smc_t(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) { … } static int si_disable_ulv(struct amdgpu_device *adev) { … } static bool si_is_state_ulv_compatible(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) { … } static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) { … } static int si_convert_power_state_to_smc(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) { … } static int si_upload_sw_state(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) { … } static int si_upload_ulv_state(struct amdgpu_device *adev) { … } static int si_upload_smc_data(struct amdgpu_device *adev) { … } static int si_set_mc_special_registers(struct amdgpu_device *adev, struct si_mc_reg_table *table) { … } static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) { … } static void si_set_valid_flag(struct si_mc_reg_table *table) { … } static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) { … } static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, struct si_mc_reg_table *si_table) { … } static int si_initialize_mc_reg_table(struct amdgpu_device *adev) { … } static void si_populate_mc_reg_addresses(struct amdgpu_device *adev, SMC_SIslands_MCRegisters *mc_reg_table) { … } static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, SMC_SIslands_MCRegisterSet *data, u32 num_entries, u32 valid_flag) { … } static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, struct rv7xx_pl *pl, SMC_SIslands_MCRegisterSet *mc_reg_table_data) { … } static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SMC_SIslands_MCRegisters *mc_reg_table) { … } static int si_populate_mc_reg_table(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_boot_state) { … } static int si_upload_mc_reg_table(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) { … } static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable) { … } static enum si_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) { … } static u16 si_get_current_pcie_speed(struct amdgpu_device *adev) { … } static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, struct amdgpu_ps *amdgpu_current_state) { … } static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, struct amdgpu_ps *amdgpu_current_state) { … } #if 0 static int si_ds_request(struct amdgpu_device *adev, bool ds_status_on, u32 count_write) { struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); if (eg_pi->sclk_deep_sleep) { if (ds_status_on) return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == PPSMC_Result_OK) ? 0 : -EINVAL; else return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) == PPSMC_Result_OK) ? 0 : -EINVAL; } return 0; } #endif static void si_set_max_cu_value(struct amdgpu_device *adev) { … } static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev, struct amdgpu_clock_voltage_dependency_table *table) { … } static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev) { … } static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, struct amdgpu_ps *amdgpu_current_state) { … } static void si_dpm_setup_asic(struct amdgpu_device *adev) { … } static int si_thermal_enable_alert(struct amdgpu_device *adev, bool enable) { … } static int si_thermal_set_temperature_range(struct amdgpu_device *adev, int min_temp, int max_temp) { … } static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) { … } static int si_thermal_setup_fan_table(struct amdgpu_device *adev) { … } static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) { … } static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) { … } static int si_dpm_get_fan_speed_pwm(void *handle, u32 *speed) { … } static int si_dpm_set_fan_speed_pwm(void *handle, u32 speed) { … } static int si_dpm_set_fan_control_mode(void *handle, u32 mode) { … } static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode) { … } #if 0 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev, u32 *speed) { u32 tach_period; u32 xclk = amdgpu_asic_get_xclk(adev); if (adev->pm.no_fan) return -ENOENT; if (adev->pm.fan_pulses_per_revolution == 0) return -ENOENT; tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; if (tach_period == 0) return -ENOENT; *speed = 60 * xclk * 10000 / tach_period; return 0; } static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev, u32 speed) { u32 tach_period, tmp; u32 xclk = amdgpu_asic_get_xclk(adev); if (adev->pm.no_fan) return -ENOENT; if (adev->pm.fan_pulses_per_revolution == 0) return -ENOENT; if ((speed < adev->pm.fan_min_rpm) || (speed > adev->pm.fan_max_rpm)) return -EINVAL; if (adev->pm.dpm.fan.ucode_fan_control) si_fan_ctrl_stop_smc_fan_control(adev); tach_period = 60 * xclk * 10000 / (8 * speed); tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; tmp |= TARGET_PERIOD(tach_period); WREG32(CG_TACH_CTRL, tmp); si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM); return 0; } #endif static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev) { … } static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev) { … } static void si_thermal_initialize(struct amdgpu_device *adev) { … } static int si_thermal_start_thermal_controller(struct amdgpu_device *adev) { … } static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev) { … } static int si_dpm_enable(struct amdgpu_device *adev) { … } static int si_set_temperature_range(struct amdgpu_device *adev) { … } static void si_dpm_disable(struct amdgpu_device *adev) { … } static int si_dpm_pre_set_power_state(void *handle) { … } static int si_power_control_set_level(struct amdgpu_device *adev) { … } static void si_set_vce_clock(struct amdgpu_device *adev, struct amdgpu_ps *new_rps, struct amdgpu_ps *old_rps) { … } static int si_dpm_set_power_state(void *handle) { … } static void si_dpm_post_set_power_state(void *handle) { … } #if 0 void si_dpm_reset_asic(struct amdgpu_device *adev) { si_restrict_performance_levels_before_switch(adev); si_disable_ulv(adev); si_set_boot_state(adev); } #endif static void si_dpm_display_configuration_changed(void *handle) { … } static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev, struct amdgpu_ps *rps, struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, u8 table_rev) { … } static void si_parse_pplib_clock_info(struct amdgpu_device *adev, struct amdgpu_ps *rps, int index, union pplib_clock_info *clock_info) { … } pplib_power_state; static int si_parse_power_table(struct amdgpu_device *adev) { … } static int si_dpm_init(struct amdgpu_device *adev) { … } static void si_dpm_fini(struct amdgpu_device *adev) { … } static void si_dpm_debugfs_print_current_performance_level(void *handle, struct seq_file *m) { … } static int si_dpm_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) { … } static int si_dpm_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { … } static int si_dpm_late_init(void *handle) { … } /** * si_dpm_init_microcode - load ucode images from disk * * @adev: amdgpu_device pointer * * Use the firmware interface to load the ucode images into * the driver (not loaded into hw). * Returns 0 on success, error on failure. */ static int si_dpm_init_microcode(struct amdgpu_device *adev) { … } static int si_dpm_sw_init(void *handle) { … } static int si_dpm_sw_fini(void *handle) { … } static int si_dpm_hw_init(void *handle) { … } static int si_dpm_hw_fini(void *handle) { … } static int si_dpm_suspend(void *handle) { … } static int si_dpm_resume(void *handle) { … } static bool si_dpm_is_idle(void *handle) { … } static int si_dpm_wait_for_idle(void *handle) { … } static int si_dpm_soft_reset(void *handle) { … } static int si_dpm_set_clockgating_state(void *handle, enum amd_clockgating_state state) { … } static int si_dpm_set_powergating_state(void *handle, enum amd_powergating_state state) { … } /* get temperature in millidegrees */ static int si_dpm_get_temp(void *handle) { … } static u32 si_dpm_get_sclk(void *handle, bool low) { … } static u32 si_dpm_get_mclk(void *handle, bool low) { … } static void si_dpm_print_power_state(void *handle, void *current_ps) { … } static int si_dpm_early_init(void *handle) { … } static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1, const struct rv7xx_pl *si_cpl2) { … } static int si_check_state_equal(void *handle, void *current_ps, void *request_ps, bool *equal) { … } static int si_dpm_read_sensor(void *handle, int idx, void *value, int *size) { … } static const struct amd_ip_funcs si_dpm_ip_funcs = …; const struct amdgpu_ip_block_version si_smu_ip_block = …; static const struct amd_pm_funcs si_dpm_funcs = …; static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = …; static void si_dpm_set_irq_funcs(struct amdgpu_device *adev) { … }
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