/* * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef __DAL_ASIC_ID_H__ #define __DAL_ASIC_ID_H__ /* * ASIC internal revision ID */ /* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */ #define SI_TAHITI_P_A0 … #define SI_TAHITI_P_B0 … #define SI_TAHITI_P_B1 … #define SI_PITCAIRN_PM_A0 … #define SI_PITCAIRN_PM_A1 … #define SI_CAPEVERDE_M_A0 … #define SI_CAPEVERDE_M_A1 … #define SI_OLAND_M_A0 … #define SI_HAINAN_V_A0 … #define SI_UNKNOWN … #define ASIC_REV_IS_TAHITI_P(rev) … #define ASIC_REV_IS_PITCAIRN_PM(rev) … #define ASIC_REV_IS_CAPEVERDE_M(rev) … #define ASIC_REV_IS_OLAND_M(rev) … #define ASIC_REV_IS_HAINAN_V(rev) … /* DCE80 (based on ci_id.h in Perforce) */ #define CI_BONAIRE_M_A0 … #define CI_BONAIRE_M_A1 … #define CI_HAWAII_P_A0 … #define CI_UNKNOWN … #define ASIC_REV_IS_BONAIRE_M(rev) … #define ASIC_REV_IS_HAWAII_P(rev) … /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */ #define KV_SPECTRE_A0 … /* KV2 with Spooky GFX core, including downgraded from Spectre core, * 3-4-1-1 (CU-Pix-Primitive-RB) */ #define KV_SPOOKY_A0 … /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ #define KB_KALINDI_A0 … /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ #define KB_KALINDI_A1 … /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ #define BV_KALINDI_A2 … /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ #define ML_GODAVARI_A0 … /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */ #define ML_GODAVARI_A1 … #define KV_UNKNOWN … #define ASIC_REV_IS_KALINDI(rev) … #define ASIC_REV_IS_BHAVANI(rev) … #define ASIC_REV_IS_GODAVARI(rev) … /* VI Family */ /* DCE10 */ #define VI_TONGA_P_A0 … #define VI_TONGA_P_A1 … #define VI_FIJI_P_A0 … /* DCE112 */ #define VI_POLARIS10_P_A0 … #define VI_POLARIS11_M_A0 … #define VI_POLARIS12_V_A0 … #define VI_VEGAM_A0 … #define VI_UNKNOWN … #define ASIC_REV_IS_TONGA_P(eChipRev) … #define ASIC_REV_IS_FIJI_P(eChipRev) … #define ASIC_REV_IS_POLARIS10_P(eChipRev) … #define ASIC_REV_IS_POLARIS11_M(eChipRev) … #define ASIC_REV_IS_POLARIS12_V(eChipRev) … #define ASIC_REV_IS_VEGAM(eChipRev) … /* DCE11 */ #define CZ_CARRIZO_A0 … #define STONEY_A0 … #define CZ_UNKNOWN … #define ASIC_REV_IS_STONEY(rev) … /* DCE12 */ #define AI_UNKNOWN … #define AI_GREENLAND_P_A0 … #define AI_GREENLAND_P_A1 … #define AI_UNKNOWN … #define AI_VEGA12_P_A0 … #define AI_VEGA20_P_A0 … #define ASICREV_IS_GREENLAND_M(eChipRev) … #define ASICREV_IS_GREENLAND_P(eChipRev) … #define ASICREV_IS_VEGA12_P(eChipRev) … #define ASICREV_IS_VEGA20_P(eChipRev) … /* DCN1_0 */ #define INTERNAL_REV_RAVEN_A0 … #define RAVEN_A0 … #define RAVEN_B0 … #define PICASSO_A0 … /* DCN1_01 */ #define RAVEN2_A0 … #define RAVEN1_F0 … #define RAVEN_UNKNOWN … #define RENOIR_A0 … #ifndef ASICREV_IS_RAVEN #define ASICREV_IS_RAVEN(eChipRev) … #endif #define PRID_DALI_DE … #define PRID_DALI_DF … #define PRID_DALI_E3 … #define PRID_DALI_E4 … #define PRID_POLLOCK_94 … #define PRID_POLLOCK_95 … #define PRID_POLLOCK_E9 … #define PRID_POLLOCK_EA … #define PRID_POLLOCK_EB … #define ASICREV_IS_PICASSO(eChipRev) … #ifndef ASICREV_IS_RAVEN2 #define ASICREV_IS_RAVEN2(eChipRev) … #endif #define ASICREV_IS_RV1_F0(eChipRev) … #define FAMILY_RV … #define FAMILY_NV … enum { … }; #define ASICREV_IS_NAVI10_P(eChipRev) … #define ASICREV_IS_NAVI12_P(eChipRev) … #define ASICREV_IS_NAVI14_M(eChipRev) … #define ASICREV_IS_RENOIR(eChipRev) … #define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) … #define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) … #define ASICREV_IS_BEIGE_GOBY_P(eChipRev) … #define GREEN_SARDINE_A0 … #ifndef ASICREV_IS_GREEN_SARDINE #define ASICREV_IS_GREEN_SARDINE(eChipRev) … #endif #define DEVICE_ID_NV_13FE … #define DEVICE_ID_NV_143F … #define FAMILY_VGH … #define DEVICE_ID_VGH_163F … #define DEVICE_ID_VGH_1435 … #define VANGOGH_A0 … #define VANGOGH_UNKNOWN … #ifndef ASICREV_IS_VANGOGH #define ASICREV_IS_VANGOGH(eChipRev) … #endif #define FAMILY_YELLOW_CARP … #define YELLOW_CARP_A0 … #define YELLOW_CARP_B0 … #define YELLOW_CARP_UNKNOWN … #ifndef ASICREV_IS_YELLOW_CARP #define ASICREV_IS_YELLOW_CARP(eChipRev) … #endif #define AMDGPU_FAMILY_GC_10_3_6 … #define GC_10_3_6_A0 … #define GC_10_3_6_UNKNOWN … #define ASICREV_IS_GC_10_3_6(eChipRev) … #define AMDGPU_FAMILY_GC_10_3_7 … #define GC_10_3_7_A0 … #define GC_10_3_7_UNKNOWN … #define ASICREV_IS_GC_10_3_7(eChipRev) … #define AMDGPU_FAMILY_GC_11_0_0 … #define AMDGPU_FAMILY_GC_11_0_1 … #define AMDGPU_FAMILY_GC_11_5_0 … #define GC_11_0_0_A0 … #define GC_11_0_2_A0 … #define GC_11_0_3_A0 … #define GC_11_0_4_A0 … #define GC_11_UNKNOWN … #define ASICREV_IS_GC_11_0_0(eChipRev) … #define ASICREV_IS_GC_11_0_2(eChipRev) … #define ASICREV_IS_GC_11_0_3(eChipRev) … #define ASICREV_IS_GC_11_0_4(eChipRev) … #define AMDGPU_FAMILY_GC_12_0_0 … enum { … }; #define ASICREV_IS_GC_12_0_1_A0(eChipRev) … #define ASICREV_IS_GC_12_0_0_A0(eChipRev) … #define ASICREV_IS_DCN4(eChipRev) … #define ASICREV_IS_DCN401(eChipRev) … /* * ASIC chip ID */ /* DCE60 */ #define DEVICE_ID_SI_TAHITI_P_6780 … #define DEVICE_ID_SI_PITCAIRN_PM_6800 … #define DEVICE_ID_SI_PITCAIRN_PM_6808 … #define DEVICE_ID_SI_CAPEVERDE_M_6820 … #define DEVICE_ID_SI_CAPEVERDE_M_6828 … #define DEVICE_ID_SI_OLAND_M_6600 … #define DEVICE_ID_SI_OLAND_M_6608 … #define DEVICE_ID_SI_HAINAN_V_6660 … /* DCE80 */ #define DEVICE_ID_KALINDI_9834 … #define DEVICE_ID_TEMASH_9839 … #define DEVICE_ID_TEMASH_983D … /* RENOIR */ #define DEVICE_ID_RENOIR_1636 … /* Asic Family IDs for different asic family. */ #define FAMILY_SI … #define FAMILY_CI … #define FAMILY_KV … #define FAMILY_VI … #define FAMILY_CZ … #define FAMILY_AI … #define FAMILY_UNKNOWN … #endif /* __DAL_ASIC_ID_H__ */
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