linux/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h

/*
 * Copyright 2017 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

/**
 * Bandwidth and Watermark calculations interface.
 * (Refer to "DCEx_mode_support.xlsm" from Perforce.)
 */
#ifndef __DCN_CALCS_H__
#define __DCN_CALCS_H__

#include "bw_fixed.h"
#include "dml/display_mode_lib.h"


struct dc;
struct dc_state;

/*******************************************************************************
 * DCN data structures.
 ******************************************************************************/

#define number_of_planes …
#define number_of_planes_minus_one …
#define number_of_states …
#define number_of_states_plus_one …

#define ddr4_dram_width …
#define ddr4_dram_factor_single_Channel …
enum dcn_bw_defs { … };

/*bounding box parameters*/
/*mode parameters*/
/*system configuration*/
/* display configuration*/
struct dcn_bw_internal_vars { … };

struct dcn_soc_bounding_box { … };
extern const struct dcn_soc_bounding_box dcn10_soc_defaults;

struct dcn_ip_params { … };
extern const struct dcn_ip_params dcn10_ip_defaults;

bool dcn_validate_bandwidth(
		struct dc *dc,
		struct dc_state *context,
		bool fast_validate);

unsigned int dcn_find_dcfclk_suits_all(
	const struct dc *dc,
	struct dc_clocks *clocks);

void dcn_get_soc_clks(
		struct dc *dc,
		int *min_fclk_khz,
		int *min_dcfclk_khz,
		int *socclk_khz);

void dcn_bw_update_from_pplib_fclks(
		struct dc *dc,
		struct dm_pp_clock_levels_with_voltage *fclks);
void dcn_bw_update_from_pplib_dcfclks(
		struct dc *dc,
		struct dm_pp_clock_levels_with_voltage *dcfclks);
void dcn_bw_notify_pplib_of_wm_ranges(
		struct dc *dc,
		int min_fclk_khz,
		int min_dcfclk_khz,
		int socclk_khz);
void dcn_bw_sync_calcs_and_dml(struct dc *dc);

enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode);

#endif /* __DCN_CALCS_H__ */