#include <drm/drm_vblank.h>
#include <drm/drm_atomic_helper.h>
#include "dc.h"
#include "amdgpu.h"
#include "amdgpu_dm_psr.h"
#include "amdgpu_dm_replay.h"
#include "amdgpu_dm_crtc.h"
#include "amdgpu_dm_plane.h"
#include "amdgpu_dm_trace.h"
#include "amdgpu_dm_debugfs.h"
#define HPD_DETECTION_PERIOD_uS …
#define HPD_DETECTION_TIME_uS …
void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
{ … }
bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
struct dc_stream_state *new_stream,
struct dc_stream_state *old_stream)
{ … }
bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
{ … }
int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
{ … }
bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)
{ … }
static void amdgpu_dm_crtc_set_panel_sr_feature(
struct vblank_control_work *vblank_work,
bool vblank_enabled, bool allow_sr_entry)
{ … }
bool amdgpu_dm_is_headless(struct amdgpu_device *adev)
{ … }
static void amdgpu_dm_idle_worker(struct work_struct *work)
{ … }
struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev)
{ … }
static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
{ … }
static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
{ … }
int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
{ … }
void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
{ … }
static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state)
{ … }
static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc)
{ … }
static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
{ … }
static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
{ … }
#ifdef CONFIG_DEBUG_FS
static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
{ … }
#endif
#ifdef AMD_PRIVATE_COLOR
static void
dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
{
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
if (adev->dm.dc->caps.color.mpc.ogam_ram)
drm_object_attach_property(&crtc->base,
adev->mode_info.regamma_tf_property,
AMDGPU_TRANSFER_FUNCTION_DEFAULT);
}
static int
amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc,
struct drm_crtc_state *state,
struct drm_property *property,
uint64_t val)
{
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
if (property == adev->mode_info.regamma_tf_property) {
if (acrtc_state->regamma_tf != val) {
acrtc_state->regamma_tf = val;
acrtc_state->base.color_mgmt_changed |= 1;
}
} else {
drm_dbg_atomic(crtc->dev,
"[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n",
crtc->base.id, crtc->name,
property->base.id, property->name);
return -EINVAL;
}
return 0;
}
static int
amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc,
const struct drm_crtc_state *state,
struct drm_property *property,
uint64_t *val)
{
struct amdgpu_device *adev = drm_to_adev(crtc->dev);
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
if (property == adev->mode_info.regamma_tf_property)
*val = acrtc_state->regamma_tf;
else
return -EINVAL;
return 0;
}
#endif
static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = …;
static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
{ … }
static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
{ … }
static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc,
struct drm_crtc_state *new_crtc_state)
{ … }
static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{ … }
static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
struct drm_atomic_state *state)
{ … }
static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = …;
int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
struct drm_plane *plane,
uint32_t crtc_index)
{ … }