linux/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

/*
 * Copyright 2018 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 */
#include <linux/string.h>
#include <linux/acpi.h>

#include <drm/drm_probe_helper.h>
#include <drm/amdgpu_drm.h>
#include "dm_services.h"
#include "amdgpu.h"
#include "amdgpu_dm.h"
#include "amdgpu_dm_irq.h"
#include "amdgpu_pm.h"
#include "dm_pp_smu.h"

bool dm_pp_apply_display_requirements(
		const struct dc_context *ctx,
		const struct dm_pp_display_configuration *pp_display_cfg)
{ … }

static void get_default_clock_levels(
		enum dm_pp_clock_type clk_type,
		struct dm_pp_clock_levels *clks)
{ … }

static enum amd_pp_clock_type dc_to_pp_clock_type(
		enum dm_pp_clock_type dm_pp_clk_type)
{ … }

static enum dm_pp_clocks_state pp_to_dc_powerlevel_state(
			enum PP_DAL_POWERLEVEL max_clocks_state)
{ … }

static void pp_to_dc_clock_levels(
		const struct amd_pp_clocks *pp_clks,
		struct dm_pp_clock_levels *dc_clks,
		enum dm_pp_clock_type dc_clk_type)
{ … }

static void pp_to_dc_clock_levels_with_latency(
		const struct pp_clock_levels_with_latency *pp_clks,
		struct dm_pp_clock_levels_with_latency *clk_level_info,
		enum dm_pp_clock_type dc_clk_type)
{ … }

static void pp_to_dc_clock_levels_with_voltage(
		const struct pp_clock_levels_with_voltage *pp_clks,
		struct dm_pp_clock_levels_with_voltage *clk_level_info,
		enum dm_pp_clock_type dc_clk_type)
{ … }

bool dm_pp_get_clock_levels_by_type(
		const struct dc_context *ctx,
		enum dm_pp_clock_type clk_type,
		struct dm_pp_clock_levels *dc_clks)
{ … }

bool dm_pp_get_clock_levels_by_type_with_latency(
	const struct dc_context *ctx,
	enum dm_pp_clock_type clk_type,
	struct dm_pp_clock_levels_with_latency *clk_level_info)
{ … }

bool dm_pp_get_clock_levels_by_type_with_voltage(
	const struct dc_context *ctx,
	enum dm_pp_clock_type clk_type,
	struct dm_pp_clock_levels_with_voltage *clk_level_info)
{ … }

bool dm_pp_notify_wm_clock_changes(
	const struct dc_context *ctx,
	struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
{ … }

bool dm_pp_apply_power_level_change_request(
	const struct dc_context *ctx,
	struct dm_pp_power_level_change_request *level_change_req)
{ … }

bool dm_pp_apply_clock_for_voltage_request(
	const struct dc_context *ctx,
	struct dm_pp_clock_for_voltage_req *clock_for_voltage_req)
{ … }

bool dm_pp_get_static_clocks(
	const struct dc_context *ctx,
	struct dm_pp_static_clock_info *static_clk_info)
{ … }

static void pp_rv_set_wm_ranges(struct pp_smu *pp,
		struct pp_smu_wm_range_sets *ranges)
{ … }

static void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
{ … }

static void pp_rv_set_active_display_count(struct pp_smu *pp, int count)
{ … }

static void pp_rv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int clock)
{ … }

static void pp_rv_set_hard_min_dcefclk_by_freq(struct pp_smu *pp, int clock)
{ … }

static void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz)
{ … }

static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
		struct pp_smu_wm_range_sets *ranges)
{ … }

static enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
{ … }

static enum pp_smu_status
pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz)
{ … }

static enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(
		struct pp_smu *pp, int mhz)
{ … }

static enum pp_smu_status
pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz)
{ … }

static enum pp_smu_status pp_nv_set_pstate_handshake_support(
	struct pp_smu *pp, bool pstate_handshake_supported)
{ … }

static enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,
		enum pp_smu_nv_clock_id clock_id, int mhz)
{ … }

static enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(
		struct pp_smu *pp, struct pp_smu_nv_clock_table *max_clocks)
{ … }

static enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,
		unsigned int *clock_values_in_khz, unsigned int *num_states)
{ … }

static enum pp_smu_status pp_rn_get_dpm_clock_table(
		struct pp_smu *pp, struct dpm_clocks *clock_table)
{ … }

static enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,
		struct pp_smu_wm_range_sets *ranges)
{ … }

void dm_pp_get_funcs(
		struct dc_context *ctx,
		struct pp_smu_funcs *funcs)
{ … }