/* * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef __IRQSRCS_DCN_1_0_H__ #define __IRQSRCS_DCN_1_0_H__ #define DCN_1_0__SRCID__DC_I2C_SW_DONE … #define DCN_1_0__CTXID__DC_I2C_SW_DONE … #define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE … #define DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE … #define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE … #define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE … #define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE … #define DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE … #define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE … #define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE … #define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE … #define DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE … #define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE … #define DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE … #define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE … #define DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE … #define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST … #define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST … #define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST … #define DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST … #define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST … #define DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST … #define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST … #define DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST … #define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST … #define DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST … #define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST … #define DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST … #define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST … #define DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST … #define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST … #define DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST … #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT … #define DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT … #define DCN_1_0__SRCID__DMCU_INTERNAL_INT … #define DCN_1_0__CTXID__DMCU_INTERNAL_INT … #define DCN_1_0__SRCID__DMCU_SCP_INT … #define DCN_1_0__CTXID__DMCU_SCP_INT … #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT … #define DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT … #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT … #define DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT … #define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT … #define DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT … #define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT … #define DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT … #define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT … #define DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT … #define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT … #define DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT … #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT … #define DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT … #define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT … #define DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT … #define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT … #define DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT … #define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT … #define DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT … #define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT … #define DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT … #define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT … #define DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT … #define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT … #define DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT … #define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT … #define DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT … #define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT … #define DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT … #define DCN_1_0__SRCID__DC_HPD1_INT … #define DCN_1_0__CTXID__DC_HPD1_INT … #define DCN_1_0__SRCID__DC_HPD2_INT … #define DCN_1_0__CTXID__DC_HPD2_INT … #define DCN_1_0__SRCID__DC_HPD3_INT … #define DCN_1_0__CTXID__DC_HPD3_INT … #define DCN_1_0__SRCID__DC_HPD4_INT … #define DCN_1_0__CTXID__DC_HPD4_INT … #define DCN_1_0__SRCID__DC_HPD5_INT … #define DCN_1_0__CTXID__DC_HPD5_INT … #define DCN_1_0__SRCID__DC_HPD6_INT … #define DCN_1_0__CTXID__DC_HPD6_INT … #define DCN_1_0__SRCID__DC_HPD1_RX_INT … #define DCN_1_0__CTXID__DC_HPD1_RX_INT … #define DCN_1_0__SRCID__DC_HPD2_RX_INT … #define DCN_1_0__CTXID__DC_HPD2_RX_INT … #define DCN_1_0__SRCID__DC_HPD3_RX_INT … #define DCN_1_0__CTXID__DC_HPD3_RX_INT … #define DCN_1_0__SRCID__DC_HPD4_RX_INT … #define DCN_1_0__CTXID__DC_HPD4_RX_INT … #define DCN_1_0__SRCID__DC_HPD5_RX_INT … #define DCN_1_0__CTXID__DC_HPD5_RX_INT … #define DCN_1_0__SRCID__DC_HPD6_RX_INT … #define DCN_1_0__CTXID__DC_HPD6_RX_INT … #define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET … #define DCN_1_0__CTXID__DC_DAC_A_AUTO_DET … #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT … #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT … #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT … #define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE … #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE … #define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR … #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR … #define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE … #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE … #define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR … #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR … #define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE … #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE … #define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR … #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR … #define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE … #define DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE … #define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE … #define DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE … #define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE … #define DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE … #define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE … #define DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE … #define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE … #define DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE … #define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE … #define DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE … #define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE … #define DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE … #define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE … #define DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE … #define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT … #define DCN_1_0__SRCID__DC_AUX1_SW_DONE … #define DCN_1_0__CTXID__DC_AUX1_SW_DONE … #define DCN_1_0__SRCID__DC_AUX1_LS_DONE … #define DCN_1_0__CTXID__DC_AUX1_LS_DONE … #define DCN_1_0__SRCID__DC_AUX2_SW_DONE … #define DCN_1_0__CTXID__DC_AUX2_SW_DONE … #define DCN_1_0__SRCID__DC_AUX2_LS_DONE … #define DCN_1_0__CTXID__DC_AUX2_LS_DONE … #define DCN_1_0__SRCID__DC_AUX3_SW_DONE … #define DCN_1_0__CTXID__DC_AUX3_SW_DONE … #define DCN_1_0__SRCID__DC_AUX3_LS_DONE … #define DCN_1_0__CTXID__DC_AUX3_LS_DONE … #define DCN_1_0__SRCID__DC_AUX4_SW_DONE … #define DCN_1_0__CTXID__DC_AUX4_SW_DONE … #define DCN_1_0__SRCID__DC_AUX4_LS_DONE … #define DCN_1_0__CTXID__DC_AUX4_LS_DONE … #define DCN_1_0__SRCID__DC_AUX5_SW_DONE … #define DCN_1_0__CTXID__DC_AUX5_SW_DONE … #define DCN_1_0__SRCID__DC_AUX5_LS_DONE … #define DCN_1_0__CTXID__DC_AUX5_LS_DONE … #define DCN_1_0__SRCID__DC_AUX6_SW_DONE … #define DCN_1_0__CTXID__DC_AUX6_SW_DONE … #define DCN_1_0__SRCID__DC_AUX6_LS_DONE … #define DCN_1_0__CTXID__DC_AUX6_LS_DONE … #define DCN_1_0__SRCID__VGA_CRT_INT … #define DCN_1_0__CTXID__VGA_CRT_INT … #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS … #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS … #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS … #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS … #define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt … #define DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt … #define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt … #define DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt … #define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT … #define DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT … #define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT … #define DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT … #define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS … #define DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS … #define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS … #define DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS … #define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS … #define DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS … #define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS … #define DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS … #define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE … #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE … #define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR … #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR … #define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE … #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE … #define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR … #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR … #define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE … #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE … #define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR … #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR … #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int … #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int … #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int … #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int … #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int … #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int … #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int … #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int … #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int … #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int … #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int … #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int … #define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT … #define DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT … #define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT … #define DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT … #define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT … #define DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT … #define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT … #define DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT … #define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT … #define DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT … #define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT … #define DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT … #define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT … #define DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT … #define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT … #define DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT … #define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT … #define DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT … #define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT … #define DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT … #define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT … #define DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT … #define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT … #define DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT … #define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT … #define DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT … #define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT … #define DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT … #define DCN_1_0__SRCID__OTG1_CPU_SS_INT … #define DCN_1_0__CTXID__OTG1_CPU_SS_INT … #define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE … #define DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE … #define DCN_1_0__SRCID__OTG2_CPU_SS_INT … #define DCN_1_0__CTXID__OTG2_CPU_SS_INT … #define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE … #define DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE … #define DCN_1_0__SRCID__OTG3_CPU_SS_INT … #define DCN_1_0__CTXID__OTG3_CPU_SS_INT … #define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE … #define DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE … #define DCN_1_0__SRCID__OTG4_CPU_SS_INT … #define DCN_1_0__CTXID__OTG4_CPU_SS_INT … #define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE … #define DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE … #define DCN_1_0__SRCID__OTG5_CPU_SS_INT … #define DCN_1_0__CTXID__OTG5_CPU_SS_INT … #define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE … #define DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE … #define DCN_1_0__SRCID__OTG6_CPU_SS_INT … #define DCN_1_0__CTXID__OTG6_CPU_SS_INT … #define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE … #define DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE … #define DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE … #define DCN_1_0__SRCID__DC_D2_OTG_V_UPDATE … #define DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE … #define DCN_1_0__SRCID__DC_D4_OTG_V_UPDATE … #define DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE … #define DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE … #define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT … #define DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT … #define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W … #define DCN_1_0__CTXID__DC_D1_FORCE_CNT_W … #define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A … #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A … #define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B … #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B … #define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP … #define DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP … #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT … #define DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT … #define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W … #define DCN_1_0__CTXID__DC_D2_FORCE_CNT_W … #define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A … #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A … #define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B … #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B … #define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP … #define DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP … #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT … #define DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT … #define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W … #define DCN_1_0__CTXID__DC_D3_FORCE_CNT_W … #define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A … #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A … #define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B … #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B … #define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP … #define DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP … #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT … #define DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT … #define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W … #define DCN_1_0__CTXID__DC_D4_FORCE_CNT_W … #define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A … #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A … #define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B … #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B … #define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP … #define DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP … #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT … #define DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT … #define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W … #define DCN_1_0__CTXID__DC_D5_FORCE_CNT_W … #define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A … #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A … #define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B … #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B … #define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP … #define DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP … #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__SRCID__DC_D1_VBLANK … #define DCN_1_0__CTXID__DC_D1_VBLANK … #define DCN_1_0__SRCID__DC_D1_VLINE1 … #define DCN_1_0__CTXID__DC_D1_VLINE1 … #define DCN_1_0__SRCID__DC_D1_VLINE2 … #define DCN_1_0__CTXID__DC_D1_VLINE2 … #define DCN_1_0__SRCID__DC_D2_VBLANK … #define DCN_1_0__CTXID__DC_D2_VBLANK … #define DCN_1_0__SRCID__DC_D2_VLINE1 … #define DCN_1_0__CTXID__DC_D2_VLINE1 … #define DCN_1_0__SRCID__DC_D2_VLINE2 … #define DCN_1_0__CTXID__DC_D2_VLINE2 … #define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR … #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DC_D3_VBLANK … #define DCN_1_0__CTXID__DC_D3_VBLANK … #define DCN_1_0__SRCID__DC_D3_VLINE1 … #define DCN_1_0__CTXID__DC_D3_VLINE1 … #define DCN_1_0__SRCID__DC_D3_VLINE2 … #define DCN_1_0__CTXID__DC_D3_VLINE2 … #define DCN_1_0__SRCID__DC_D4_VBLANK … #define DCN_1_0__CTXID__DC_D4_VBLANK … #define DCN_1_0__SRCID__DC_D4_VLINE1 … #define DCN_1_0__CTXID__DC_D4_VLINE1 … #define DCN_1_0__SRCID__DC_D4_VLINE2 … #define DCN_1_0__CTXID__DC_D4_VLINE2 … #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DC_D5_VBLANK … #define DCN_1_0__CTXID__DC_D5_VBLANK … #define DCN_1_0__SRCID__DC_D5_VLINE1 … #define DCN_1_0__CTXID__DC_D5_VLINE1 … #define DCN_1_0__SRCID__DC_D5_VLINE2 … #define DCN_1_0__CTXID__DC_D5_VLINE2 … #define DCN_1_0__SRCID__DC_D6_VBLANK … #define DCN_1_0__CTXID__DC_D6_VBLANK … #define DCN_1_0__SRCID__DC_D6_VLINE1 … #define DCN_1_0__CTXID__DC_D6_VLINE1 … #define DCN_1_0__SRCID__DC_D6_VLINE2 … #define DCN_1_0__CTXID__DC_D6_VLINE2 … #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DC_D7_VBLANK … #define DCN_1_0__CTXID__DC_D7_VBLANK … #define DCN_1_0__SRCID__DC_D7_VLINE1 … #define DCN_1_0__CTXID__DC_D7_VLINE1 … #define DCN_1_0__SRCID__DC_D7_VLINE2 … #define DCN_1_0__CTXID__DC_D7_VLINE2 … #define DCN_1_0__SRCID__DC_D8_VBLANK … #define DCN_1_0__CTXID__DC_D8_VBLANK … #define DCN_1_0__SRCID__DC_D8_VLINE1 … #define DCN_1_0__CTXID__DC_D8_VLINE1 … #define DCN_1_0__SRCID__DC_D8_VLINE2 … #define DCN_1_0__CTXID__DC_D8_VLINE2 … #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT … #define DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT … #define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W … #define DCN_1_0__CTXID__DC_D6_FORCE_CNT_W … #define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE … #define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A … #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A … #define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B … #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B … #define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP … #define DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP … #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL … #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL … #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL … #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL … #define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT … #define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS … #define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS … #define DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP … #define DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP … #define DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP … #define DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP … #define DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP … #define DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP … #define DCN_1_0__SRCID__DC_D1_OTG_VREADY … #define DCN_1_0__SRCID__DC_D2_OTG_VREADY … #define DCN_1_0__SRCID__DC_D3_OTG_VREADY … #define DCN_1_0__SRCID__DC_D4_OTG_VREADY … #define DCN_1_0__SRCID__DC_D5_OTG_VREADY … #define DCN_1_0__SRCID__DC_D6_OTG_VREADY … #define DCN_1_0__SRCID__OTG0_VSYNC_NOM … #define DCN_1_0__SRCID__OTG1_VSYNC_NOM … #define DCN_1_0__SRCID__OTG2_VSYNC_NOM … #define DCN_1_0__SRCID__OTG3_VSYNC_NOM … #define DCN_1_0__SRCID__OTG4_VSYNC_NOM … #define DCN_1_0__SRCID__OTG5_VSYNC_NOM … #define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT … #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT … #define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT … #define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT … #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT … #define DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT … #define DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT … #define DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT … #define DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT … #define DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT … #define DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT … #define DCN_1_0__SRCID__HUBP6_FLIP_INTERRUPT … #define DCN_1_0__SRCID__HUBP7_FLIP_INTERRUPT … #define DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT … #define DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT … #define DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT … #define DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT … #define DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT … #define DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT … #define DCN_1_0__SRCID__HUBP0_FLIP_AWAY_INTERRUPT … #define DCN_1_0__SRCID__HUBP1_FLIP_AWAY_INTERRUPT … #define DCN_1_0__SRCID__HUBP2_FLIP_AWAY_INTERRUPT … #define DCN_1_0__SRCID__HUBP3_FLIP_AWAY_INTERRUPT … #define DCN_1_0__SRCID__HUBP4_FLIP_AWAY_INTERRUPT … #define DCN_1_0__SRCID__HUBP5_FLIP_AWAY_INTERRUPT … #define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT … #define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT … #define DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT … #define DCN_1_0__CTXID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT … #define DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT … #define DCN_1_0__CTXID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT … #endif // __IRQSRCS_DCN_1_0_H__
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