/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _dcn_1_0_OFFSET_HEADER #define _dcn_1_0_OFFSET_HEADER // addressBlock: dce_dc_hda_azcontroller_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azendpoint_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azinputendpoint_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azroot_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azstream0_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azstream1_azdec // base address: 0x1300020 // addressBlock: dce_dc_hda_azstream2_azdec // base address: 0x1300040 // addressBlock: dce_dc_hda_azstream3_azdec // base address: 0x1300060 // addressBlock: dce_dc_hda_azstream4_azdec // base address: 0x1300080 // addressBlock: dce_dc_hda_azstream5_azdec // base address: 0x13000a0 // addressBlock: dce_dc_hda_azstream6_azdec // base address: 0x13000c0 // addressBlock: dce_dc_hda_azstream7_azdec // base address: 0x13000e0 // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] // base address: 0x48 #define mmVGA_MEM_WRITE_PAGE_ADDR … #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX … #define mmVGA_MEM_READ_PAGE_ADDR … #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX … // addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] // base address: 0x3b4 #define mmCRTC8_IDX … #define mmCRTC8_IDX_BASE_IDX … #define mmCRTC8_DATA … #define mmCRTC8_DATA_BASE_IDX … #define mmGENFC_WT … #define mmGENFC_WT_BASE_IDX … #define mmGENS1 … #define mmGENS1_BASE_IDX … #define mmATTRDW … #define mmATTRDW_BASE_IDX … #define mmATTRX … #define mmATTRX_BASE_IDX … #define mmATTRDR … #define mmATTRDR_BASE_IDX … #define mmGENMO_WT … #define mmGENMO_WT_BASE_IDX … #define mmGENS0 … #define mmGENS0_BASE_IDX … #define mmGENENB … #define mmGENENB_BASE_IDX … #define mmSEQ8_IDX … #define mmSEQ8_IDX_BASE_IDX … #define mmSEQ8_DATA … #define mmSEQ8_DATA_BASE_IDX … #define mmDAC_MASK … #define mmDAC_MASK_BASE_IDX … #define mmDAC_R_INDEX … #define mmDAC_R_INDEX_BASE_IDX … #define mmDAC_W_INDEX … #define mmDAC_W_INDEX_BASE_IDX … #define mmDAC_DATA … #define mmDAC_DATA_BASE_IDX … #define mmGENFC_RD … #define mmGENFC_RD_BASE_IDX … #define mmGENMO_RD … #define mmGENMO_RD_BASE_IDX … #define mmGRPH8_IDX … #define mmGRPH8_IDX_BASE_IDX … #define mmGRPH8_DATA … #define mmGRPH8_DATA_BASE_IDX … #define mmCRTC8_IDX_1 … #define mmCRTC8_IDX_1_BASE_IDX … #define mmCRTC8_DATA_1 … #define mmCRTC8_DATA_1_BASE_IDX … #define mmGENFC_WT_1 … #define mmGENFC_WT_1_BASE_IDX … #define mmGENS1_1 … #define mmGENS1_1_BASE_IDX … // addressBlock: dce_dc_hda_azcontroller_azdec // base address: 0x0 #define mmCORB_WRITE_POINTER … #define mmCORB_WRITE_POINTER_BASE_IDX … #define mmCORB_READ_POINTER … #define mmCORB_READ_POINTER_BASE_IDX … #define mmCORB_CONTROL … #define mmCORB_CONTROL_BASE_IDX … #define mmCORB_STATUS … #define mmCORB_STATUS_BASE_IDX … #define mmCORB_SIZE … #define mmCORB_SIZE_BASE_IDX … #define mmRIRB_LOWER_BASE_ADDRESS … #define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX … #define mmRIRB_UPPER_BASE_ADDRESS … #define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX … #define mmRIRB_WRITE_POINTER … #define mmRIRB_WRITE_POINTER_BASE_IDX … #define mmRESPONSE_INTERRUPT_COUNT … #define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX … #define mmRIRB_CONTROL … #define mmRIRB_CONTROL_BASE_IDX … #define mmRIRB_STATUS … #define mmRIRB_STATUS_BASE_IDX … #define mmRIRB_SIZE … #define mmRIRB_SIZE_BASE_IDX … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE … #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX … #define mmIMMEDIATE_COMMAND_STATUS … #define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX … #define mmDMA_POSITION_LOWER_BASE_ADDRESS … #define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX … #define mmDMA_POSITION_UPPER_BASE_ADDRESS … #define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX … #define mmWALL_CLOCK_COUNTER_ALIAS … #define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX … // addressBlock: dce_dc_hda_azendpoint_azdec // base address: 0x0 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … // addressBlock: dce_dc_hda_azinputendpoint_azdec // base address: 0x0 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA … #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX … #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX … // addressBlock: dce_dc_hda_azroot_azdec // base address: 0x0 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA … #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX … #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX … #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX … // addressBlock: dce_dc_hda_azstream0_azdec // base address: 0x0 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_hda_azstream1_azdec // base address: 0x20 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_hda_azstream2_azdec // base address: 0x40 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_hda_azstream3_azdec // base address: 0x60 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_hda_azstream4_azdec // base address: 0x80 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_hda_azstream5_azdec // base address: 0xa0 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_hda_azstream6_azdec // base address: 0xc0 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_hda_azstream7_azdec // base address: 0xe0 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS … #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX … // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] // base address: 0x48 //#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000 //#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001 // addressBlock: dce_dc_mmhubbub_vga_dispdec // base address: 0x0 //#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000 //#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001 #define mmVGA_RENDER_CONTROL … #define mmVGA_RENDER_CONTROL_BASE_IDX … #define mmVGA_SEQUENCER_RESET_CONTROL … #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX … #define mmVGA_MODE_CONTROL … #define mmVGA_MODE_CONTROL_BASE_IDX … #define mmVGA_SURFACE_PITCH_SELECT … #define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX … #define mmVGA_MEMORY_BASE_ADDRESS … #define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX … #define mmVGA_DISPBUF1_SURFACE_ADDR … #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX … #define mmVGA_DISPBUF2_SURFACE_ADDR … #define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX … #define mmVGA_MEMORY_BASE_ADDRESS_HIGH … #define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX … #define mmVGA_HDP_CONTROL … #define mmVGA_HDP_CONTROL_BASE_IDX … #define mmVGA_CACHE_CONTROL … #define mmVGA_CACHE_CONTROL_BASE_IDX … #define mmD1VGA_CONTROL … #define mmD1VGA_CONTROL_BASE_IDX … #define mmD2VGA_CONTROL … #define mmD2VGA_CONTROL_BASE_IDX … #define mmVGA_STATUS … #define mmVGA_STATUS_BASE_IDX … #define mmVGA_INTERRUPT_CONTROL … #define mmVGA_INTERRUPT_CONTROL_BASE_IDX … #define mmVGA_STATUS_CLEAR … #define mmVGA_STATUS_CLEAR_BASE_IDX … #define mmVGA_INTERRUPT_STATUS … #define mmVGA_INTERRUPT_STATUS_BASE_IDX … #define mmVGA_MAIN_CONTROL … #define mmVGA_MAIN_CONTROL_BASE_IDX … #define mmVGA_TEST_CONTROL … #define mmVGA_TEST_CONTROL_BASE_IDX … #define mmVGA_QOS_CTRL … #define mmVGA_QOS_CTRL_BASE_IDX … //#define mmVGA_CRTC8_IDX 0x002d //#define mmVGA_CRTC8_DATA 0x002d //#define mmVGA_GENFC_WT 0x002e //#define mmVGA_GENS1 0x002e //#define mmVGA_ATTRDW 0x0030 //#define mmVGA_ATTRX 0x0030 //#define mmVGA_ATTRDR 0x0030 //#define mmVGA_GENMO_WT 0x0030 //#define mmVGA_GENS0 0x0030 //#define mmVGA_GENENB 0x0030 //#define mmVGA_SEQ8_IDX 0x0031 //#define mmVGA_SEQ8_DATA 0x0031 //#define mmVGA_DAC_MASK 0x0031 //#define mmVGA_DAC_R_INDEX 0x0031 //#define mmVGA_DAC_W_INDEX 0x0032 //#define mmVGA_DAC_DATA 0x0032 //#define mmVGA_GENFC_RD 0x0032 //#define mmVGA_GENMO_RD 0x0033 //#define mmVGA_GRPH8_IDX 0x0033 //#define mmVGA_GRPH8_DATA 0x0033 //#define mmVGA_CRTC8_IDX_1 0x0035 //#define mmVGA_CRTC8_DATA_1 0x0035 //#define mmVGA_GENFC_WT_1 0x0036 //#define mmVGA_GENS1_1 0x0036 #define mmD3VGA_CONTROL … #define mmD3VGA_CONTROL_BASE_IDX … #define mmD4VGA_CONTROL … #define mmD4VGA_CONTROL_BASE_IDX … #define mmD5VGA_CONTROL … #define mmD5VGA_CONTROL_BASE_IDX … #define mmD6VGA_CONTROL … #define mmD6VGA_CONTROL_BASE_IDX … #define mmVGA_SOURCE_SELECT … #define mmVGA_SOURCE_SELECT_BASE_IDX … // addressBlock: dce_dc_dccg_dccg_dispdec // base address: 0x0 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmPHYPLLB_PIXCLK_RESYNC_CNTL … #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmPHYPLLC_PIXCLK_RESYNC_CNTL … #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmPHYPLLD_PIXCLK_RESYNC_CNTL … #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmDP_DTO_DBUF_EN … #define mmDP_DTO_DBUF_EN_BASE_IDX … #define mmDPREFCLK_CGTT_BLK_CTRL_REG … #define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmREFCLK_CNTL … #define mmREFCLK_CNTL_BASE_IDX … #define mmMIPI_CLK_CNTL … #define mmMIPI_CLK_CNTL_BASE_IDX … #define mmREFCLK_CGTT_BLK_CTRL_REG … #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmPHYPLLE_PIXCLK_RESYNC_CNTL … #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmDCCG_PERFMON_CNTL2 … #define mmDCCG_PERFMON_CNTL2_BASE_IDX … #define mmDSICLK_CGTT_BLK_CTRL_REG … #define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmDCCG_CBUS_WRCMD_DELAY … #define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX … #define mmDCCG_DS_DTO_INCR … #define mmDCCG_DS_DTO_INCR_BASE_IDX … #define mmDCCG_DS_DTO_MODULO … #define mmDCCG_DS_DTO_MODULO_BASE_IDX … #define mmDCCG_DS_CNTL … #define mmDCCG_DS_CNTL_BASE_IDX … #define mmDCCG_DS_HW_CAL_INTERVAL … #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … #define mmSYMCLKG_CLOCK_ENABLE … #define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX … #define mmDPREFCLK_CNTL … #define mmDPREFCLK_CNTL_BASE_IDX … #define mmAOMCLK0_CNTL … #define mmAOMCLK0_CNTL_BASE_IDX … #define mmAOMCLK1_CNTL … #define mmAOMCLK1_CNTL_BASE_IDX … #define mmAOMCLK2_CNTL … #define mmAOMCLK2_CNTL_BASE_IDX … #define mmDCCG_AUDIO_DTO2_PHASE … #define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX … #define mmDCCG_AUDIO_DTO2_MODULO … #define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX … #define mmDCE_VERSION … #define mmDCE_VERSION_BASE_IDX … #define mmPHYPLLG_PIXCLK_RESYNC_CNTL … #define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmDCCG_GTC_CNTL … #define mmDCCG_GTC_CNTL_BASE_IDX … #define mmDCCG_GTC_DTO_INCR … #define mmDCCG_GTC_DTO_INCR_BASE_IDX … #define mmDCCG_GTC_DTO_MODULO … #define mmDCCG_GTC_DTO_MODULO_BASE_IDX … #define mmDCCG_GTC_CURRENT … #define mmDCCG_GTC_CURRENT_BASE_IDX … #define mmMIPI_DTO_CNTL … #define mmMIPI_DTO_CNTL_BASE_IDX … #define mmMIPI_DTO_PHASE … #define mmMIPI_DTO_PHASE_BASE_IDX … #define mmMIPI_DTO_MODULO … #define mmMIPI_DTO_MODULO_BASE_IDX … #define mmDAC_CLK_ENABLE … #define mmDAC_CLK_ENABLE_BASE_IDX … #define mmDVO_CLK_ENABLE … #define mmDVO_CLK_ENABLE_BASE_IDX … #define mmAVSYNC_COUNTER_WRITE … #define mmAVSYNC_COUNTER_WRITE_BASE_IDX … #define mmAVSYNC_COUNTER_CONTROL … #define mmAVSYNC_COUNTER_CONTROL_BASE_IDX … #define mmAVSYNC_COUNTER_READ … #define mmAVSYNC_COUNTER_READ_BASE_IDX … #define mmMILLISECOND_TIME_BASE_DIV … #define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX … #define mmDISPCLK_FREQ_CHANGE_CNTL … #define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX … #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL … #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX … #define mmDCCG_PERFMON_CNTL … #define mmDCCG_PERFMON_CNTL_BASE_IDX … #define mmDCCG_GATE_DISABLE_CNTL … #define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX … #define mmDISPCLK_CGTT_BLK_CTRL_REG … #define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmSOCCLK_CGTT_BLK_CTRL_REG … #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmDCCG_CAC_STATUS … #define mmDCCG_CAC_STATUS_BASE_IDX … #define mmPIXCLK1_RESYNC_CNTL … #define mmPIXCLK1_RESYNC_CNTL_BASE_IDX … #define mmPIXCLK2_RESYNC_CNTL … #define mmPIXCLK2_RESYNC_CNTL_BASE_IDX … #define mmPIXCLK0_RESYNC_CNTL … #define mmPIXCLK0_RESYNC_CNTL_BASE_IDX … #define mmMICROSECOND_TIME_BASE_DIV … #define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX … #define mmDCCG_GATE_DISABLE_CNTL2 … #define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX … #define mmSYMCLK_CGTT_BLK_CTRL_REG … #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmPHYPLLF_PIXCLK_RESYNC_CNTL … #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmDCCG_DISP_CNTL_REG … #define mmDCCG_DISP_CNTL_REG_BASE_IDX … #define mmOTG0_PIXEL_RATE_CNTL … #define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO0_PHASE … #define mmDP_DTO0_PHASE_BASE_IDX … #define mmDP_DTO0_MODULO … #define mmDP_DTO0_MODULO_BASE_IDX … #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL … #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmOTG1_PIXEL_RATE_CNTL … #define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO1_PHASE … #define mmDP_DTO1_PHASE_BASE_IDX … #define mmDP_DTO1_MODULO … #define mmDP_DTO1_MODULO_BASE_IDX … #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL … #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmOTG2_PIXEL_RATE_CNTL … #define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO2_PHASE … #define mmDP_DTO2_PHASE_BASE_IDX … #define mmDP_DTO2_MODULO … #define mmDP_DTO2_MODULO_BASE_IDX … #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL … #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmOTG3_PIXEL_RATE_CNTL … #define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO3_PHASE … #define mmDP_DTO3_PHASE_BASE_IDX … #define mmDP_DTO3_MODULO … #define mmDP_DTO3_MODULO_BASE_IDX … #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL … #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmOTG4_PIXEL_RATE_CNTL … #define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO4_PHASE … #define mmDP_DTO4_PHASE_BASE_IDX … #define mmDP_DTO4_MODULO … #define mmDP_DTO4_MODULO_BASE_IDX … #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL … #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmOTG5_PIXEL_RATE_CNTL … #define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO5_PHASE … #define mmDP_DTO5_PHASE_BASE_IDX … #define mmDP_DTO5_MODULO … #define mmDP_DTO5_MODULO_BASE_IDX … #define mmOTG5_PHYPLL_PIXEL_RATE_CNTL … #define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmDPPCLK_CGTT_BLK_CTRL_REG … #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmSYMCLKA_CLOCK_ENABLE … #define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKB_CLOCK_ENABLE … #define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKC_CLOCK_ENABLE … #define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKD_CLOCK_ENABLE … #define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKE_CLOCK_ENABLE … #define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKF_CLOCK_ENABLE … #define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX … #define mmDCCG_SOFT_RESET … #define mmDCCG_SOFT_RESET_BASE_IDX … #define mmDVOACLKD_CNTL … #define mmDVOACLKD_CNTL_BASE_IDX … #define mmDVOACLKC_MVP_CNTL … #define mmDVOACLKC_MVP_CNTL_BASE_IDX … #define mmDVOACLKC_CNTL … #define mmDVOACLKC_CNTL_BASE_IDX … #define mmDCCG_AUDIO_DTO_SOURCE … #define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX … #define mmDCCG_AUDIO_DTO0_PHASE … #define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX … #define mmDCCG_AUDIO_DTO0_MODULE … #define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX … #define mmDCCG_AUDIO_DTO1_PHASE … #define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX … #define mmDCCG_AUDIO_DTO1_MODULE … #define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX … #define mmDCCG_VSYNC_OTG0_LATCH_VALUE … #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … #define mmDCCG_VSYNC_OTG1_LATCH_VALUE … #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … #define mmDCCG_VSYNC_OTG2_LATCH_VALUE … #define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX … #define mmDCCG_VSYNC_OTG3_LATCH_VALUE … #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX … #define mmDCCG_VSYNC_OTG4_LATCH_VALUE … #define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX … #define mmDCCG_VSYNC_OTG5_LATCH_VALUE … #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX … #define mmDCCG_VSYNC_CNT_CTRL … #define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX … #define mmDCCG_VSYNC_CNT_INT_CTRL … #define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX … #define mmDCCG_TEST_CLK_SEL … #define mmDCCG_TEST_CLK_SEL_BASE_IDX … // addressBlock: dce_dc_dccg_dccg_dfs_dispdec // base address: 0x0 #define mmDENTIST_DISPCLK_CNTL … #define mmDENTIST_DISPCLK_CNTL_BASE_IDX … // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec // base address: 0x0 #define mmDC_PERFMON0_PERFCOUNTER_CNTL … #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON0_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON0_PERFCOUNTER_STATE … #define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON0_PERFMON_CNTL … #define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON0_PERFMON_CNTL2 … #define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON0_PERFMON_CVALUE_LOW … #define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON0_PERFMON_HI … #define mmDC_PERFMON0_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON0_PERFMON_LOW … #define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec // base address: 0x30 #define mmDC_PERFMON1_PERFCOUNTER_CNTL … #define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON1_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON1_PERFCOUNTER_STATE … #define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON1_PERFMON_CNTL … #define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON1_PERFMON_CNTL2 … #define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON1_PERFMON_CVALUE_LOW … #define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON1_PERFMON_HI … #define mmDC_PERFMON1_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON1_PERFMON_LOW … #define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dccg_dccg_pll_dispdec // base address: 0x0 #define mmPLL_MACRO_CNTL_RESERVED0 … #define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED1 … #define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED2 … #define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED3 … #define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED4 … #define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED5 … #define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED6 … #define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED7 … #define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED8 … #define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED9 … #define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED10 … #define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED11 … #define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED12 … #define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED13 … #define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED14 … #define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED15 … #define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED16 … #define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED17 … #define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED18 … #define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED19 … #define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED20 … #define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED21 … #define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED22 … #define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED23 … #define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED24 … #define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED25 … #define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED26 … #define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED27 … #define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED28 … #define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED29 … #define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED30 … #define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED31 … #define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED32 … #define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED33 … #define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED34 … #define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED35 … #define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED36 … #define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED37 … #define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED38 … #define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED39 … #define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED40 … #define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmPLL_MACRO_CNTL_RESERVED41 … #define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX … // addressBlock: dce_dc_dmu_rbbmif_dispdec // base address: 0x0 #define mmRBBMIF_TIMEOUT … #define mmRBBMIF_TIMEOUT_BASE_IDX … #define mmRBBMIF_STATUS … #define mmRBBMIF_STATUS_BASE_IDX … #define mmRBBMIF_INT_STATUS … #define mmRBBMIF_INT_STATUS_BASE_IDX … #define mmRBBMIF_TIMEOUT_DIS … #define mmRBBMIF_TIMEOUT_DIS_BASE_IDX … #define mmRBBMIF_STATUS_FLAG … #define mmRBBMIF_STATUS_FLAG_BASE_IDX … // addressBlock: dce_dc_dmu_dc_pg_dispdec // base address: 0x0 #define mmDOMAIN0_PG_CONFIG … #define mmDOMAIN0_PG_CONFIG_BASE_IDX … #define mmDOMAIN0_PG_STATUS … #define mmDOMAIN0_PG_STATUS_BASE_IDX … #define mmDOMAIN1_PG_CONFIG … #define mmDOMAIN1_PG_CONFIG_BASE_IDX … #define mmDOMAIN1_PG_STATUS … #define mmDOMAIN1_PG_STATUS_BASE_IDX … #define mmDOMAIN2_PG_CONFIG … #define mmDOMAIN2_PG_CONFIG_BASE_IDX … #define mmDOMAIN2_PG_STATUS … #define mmDOMAIN2_PG_STATUS_BASE_IDX … #define mmDOMAIN3_PG_CONFIG … #define mmDOMAIN3_PG_CONFIG_BASE_IDX … #define mmDOMAIN3_PG_STATUS … #define mmDOMAIN3_PG_STATUS_BASE_IDX … #define mmDOMAIN4_PG_CONFIG … #define mmDOMAIN4_PG_CONFIG_BASE_IDX … #define mmDOMAIN4_PG_STATUS … #define mmDOMAIN4_PG_STATUS_BASE_IDX … #define mmDOMAIN5_PG_CONFIG … #define mmDOMAIN5_PG_CONFIG_BASE_IDX … #define mmDOMAIN5_PG_STATUS … #define mmDOMAIN5_PG_STATUS_BASE_IDX … #define mmDOMAIN6_PG_CONFIG … #define mmDOMAIN6_PG_CONFIG_BASE_IDX … #define mmDOMAIN6_PG_STATUS … #define mmDOMAIN6_PG_STATUS_BASE_IDX … #define mmDOMAIN7_PG_CONFIG … #define mmDOMAIN7_PG_CONFIG_BASE_IDX … #define mmDOMAIN7_PG_STATUS … #define mmDOMAIN7_PG_STATUS_BASE_IDX … #define mmDOMAIN8_PG_CONFIG … #define mmDOMAIN8_PG_CONFIG_BASE_IDX … #define mmDOMAIN8_PG_STATUS … #define mmDOMAIN8_PG_STATUS_BASE_IDX … #define mmDOMAIN9_PG_CONFIG … #define mmDOMAIN9_PG_CONFIG_BASE_IDX … #define mmDOMAIN9_PG_STATUS … #define mmDOMAIN9_PG_STATUS_BASE_IDX … #define mmDOMAIN10_PG_CONFIG … #define mmDOMAIN10_PG_CONFIG_BASE_IDX … #define mmDOMAIN10_PG_STATUS … #define mmDOMAIN10_PG_STATUS_BASE_IDX … #define mmDOMAIN11_PG_CONFIG … #define mmDOMAIN11_PG_CONFIG_BASE_IDX … #define mmDOMAIN11_PG_STATUS … #define mmDOMAIN11_PG_STATUS_BASE_IDX … #define mmDOMAIN12_PG_CONFIG … #define mmDOMAIN12_PG_CONFIG_BASE_IDX … #define mmDOMAIN12_PG_STATUS … #define mmDOMAIN12_PG_STATUS_BASE_IDX … #define mmDOMAIN13_PG_CONFIG … #define mmDOMAIN13_PG_CONFIG_BASE_IDX … #define mmDOMAIN13_PG_STATUS … #define mmDOMAIN13_PG_STATUS_BASE_IDX … #define mmDOMAIN14_PG_CONFIG … #define mmDOMAIN14_PG_CONFIG_BASE_IDX … #define mmDOMAIN14_PG_STATUS … #define mmDOMAIN14_PG_STATUS_BASE_IDX … #define mmDOMAIN15_PG_CONFIG … #define mmDOMAIN15_PG_CONFIG_BASE_IDX … #define mmDOMAIN15_PG_STATUS … #define mmDOMAIN15_PG_STATUS_BASE_IDX … #define mmDCPG_INTERRUPT_STATUS … #define mmDCPG_INTERRUPT_STATUS_BASE_IDX … #define mmDCPG_INTERRUPT_CONTROL_1 … #define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX … #define mmDCPG_INTERRUPT_CONTROL_2 … #define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX … #define mmDC_IP_REQUEST_CNTL … #define mmDC_IP_REQUEST_CNTL_BASE_IDX … #define mmDC_PGCNTL_STATUS_REG … #define mmDC_PGCNTL_STATUS_REG_BASE_IDX … // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec // base address: 0x2f8 #define mmDC_PERFMON2_PERFCOUNTER_CNTL … #define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON2_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON2_PERFCOUNTER_STATE … #define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON2_PERFMON_CNTL … #define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON2_PERFMON_CNTL2 … #define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON2_PERFMON_CVALUE_LOW … #define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON2_PERFMON_HI … #define mmDC_PERFMON2_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON2_PERFMON_LOW … #define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dmu_dmu_misc_dispdec // base address: 0x0 #define mmCC_DC_PIPE_DIS … #define mmCC_DC_PIPE_DIS_BASE_IDX … #define mmDMU_CLK_CNTL … #define mmDMU_CLK_CNTL_BASE_IDX … #define mmDMU_MEM_PWR_CNTL … #define mmDMU_MEM_PWR_CNTL_BASE_IDX … #define mmDMCU_SMU_INTERRUPT_CNTL … #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX … #define mmSMU_INTERRUPT_CONTROL … #define mmSMU_INTERRUPT_CONTROL_BASE_IDX … // addressBlock: dce_dc_dmu_dmcu_dispdec // base address: 0x0 #define mmDMCU_CTRL … #define mmDMCU_CTRL_BASE_IDX … #define mmDMCU_STATUS … #define mmDMCU_STATUS_BASE_IDX … #define mmDMCU_PC_START_ADDR … #define mmDMCU_PC_START_ADDR_BASE_IDX … #define mmDMCU_FW_START_ADDR … #define mmDMCU_FW_START_ADDR_BASE_IDX … #define mmDMCU_FW_END_ADDR … #define mmDMCU_FW_END_ADDR_BASE_IDX … #define mmDMCU_FW_ISR_START_ADDR … #define mmDMCU_FW_ISR_START_ADDR_BASE_IDX … #define mmDMCU_FW_CS_HI … #define mmDMCU_FW_CS_HI_BASE_IDX … #define mmDMCU_FW_CS_LO … #define mmDMCU_FW_CS_LO_BASE_IDX … #define mmDMCU_RAM_ACCESS_CTRL … #define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX … #define mmDMCU_ERAM_WR_CTRL … #define mmDMCU_ERAM_WR_CTRL_BASE_IDX … #define mmDMCU_ERAM_WR_DATA … #define mmDMCU_ERAM_WR_DATA_BASE_IDX … #define mmDMCU_ERAM_RD_CTRL … #define mmDMCU_ERAM_RD_CTRL_BASE_IDX … #define mmDMCU_ERAM_RD_DATA … #define mmDMCU_ERAM_RD_DATA_BASE_IDX … #define mmDMCU_IRAM_WR_CTRL … #define mmDMCU_IRAM_WR_CTRL_BASE_IDX … #define mmDMCU_IRAM_WR_DATA … #define mmDMCU_IRAM_WR_DATA_BASE_IDX … #define mmDMCU_IRAM_RD_CTRL … #define mmDMCU_IRAM_RD_CTRL_BASE_IDX … #define mmDMCU_IRAM_RD_DATA … #define mmDMCU_IRAM_RD_DATA_BASE_IDX … #define mmDMCU_EVENT_TRIGGER … #define mmDMCU_EVENT_TRIGGER_BASE_IDX … #define mmDMCU_UC_INTERNAL_INT_STATUS … #define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX … #define mmDMCU_SS_INTERRUPT_CNTL_STATUS … #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX … #define mmDMCU_INTERRUPT_STATUS … #define mmDMCU_INTERRUPT_STATUS_BASE_IDX … #define mmDMCU_INTERRUPT_STATUS_1 … #define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX … #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK … #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX … #define mmDC_DMCU_SCRATCH … #define mmDC_DMCU_SCRATCH_BASE_IDX … #define mmDMCU_INT_CNT … #define mmDMCU_INT_CNT_BASE_IDX … #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS … #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX … #define mmDMCU_UC_CLK_GATING_CNTL … #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX … #define mmMASTER_COMM_DATA_REG1 … #define mmMASTER_COMM_DATA_REG1_BASE_IDX … #define mmMASTER_COMM_DATA_REG2 … #define mmMASTER_COMM_DATA_REG2_BASE_IDX … #define mmMASTER_COMM_DATA_REG3 … #define mmMASTER_COMM_DATA_REG3_BASE_IDX … #define mmMASTER_COMM_CMD_REG … #define mmMASTER_COMM_CMD_REG_BASE_IDX … #define mmMASTER_COMM_CNTL_REG … #define mmMASTER_COMM_CNTL_REG_BASE_IDX … #define mmSLAVE_COMM_DATA_REG1 … #define mmSLAVE_COMM_DATA_REG1_BASE_IDX … #define mmSLAVE_COMM_DATA_REG2 … #define mmSLAVE_COMM_DATA_REG2_BASE_IDX … #define mmSLAVE_COMM_DATA_REG3 … #define mmSLAVE_COMM_DATA_REG3_BASE_IDX … #define mmSLAVE_COMM_CMD_REG … #define mmSLAVE_COMM_CMD_REG_BASE_IDX … #define mmSLAVE_COMM_CNTL_REG … #define mmSLAVE_COMM_CNTL_REG_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_STATUS1 … #define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_STATUS2 … #define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_STATUS3 … #define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_STATUS4 … #define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_STATUS5 … #define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 … #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX … #define mmDMCU_DPRX_INTERRUPT_STATUS1 … #define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX … #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 … #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX … #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 … #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX … #define mmDMCU_INTERRUPT_STATUS_CONTINUE … #define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE … #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE … #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX … #define mmDMCU_INT_CNT_CONTINUE … #define mmDMCU_INT_CNT_CONTINUE_BASE_IDX … // addressBlock: dce_dc_dmu_ihc_dispdec // base address: 0x0 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE … #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX … #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP … #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX … #define mmDC_GPU_TIMER_READ … #define mmDC_GPU_TIMER_READ_BASE_IDX … #define mmDC_GPU_TIMER_READ_CNTL … #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX … #define mmDISP_INTERRUPT_STATUS … #define mmDISP_INTERRUPT_STATUS_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE … #define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE2 … #define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE3 … #define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE4 … #define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE5 … #define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE6 … #define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE7 … #define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE8 … #define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE9 … #define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE10 … #define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE11 … #define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE12 … #define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE13 … #define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE14 … #define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE15 … #define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE16 … #define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE17 … #define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE18 … #define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE19 … #define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE20 … #define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE21 … #define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX … #define mmDISP_INTERRUPT_STATUS_CONTINUE22 … #define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX … #define mmDC_GPU_TIMER_START_POSITION_VREADY … #define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX … #define mmDC_GPU_TIMER_START_POSITION_FLIP … #define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX … #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK … #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX … #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY … #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX … // addressBlock: dce_dc_wb0_dispdec_cnv_dispdec // base address: 0x0 #define mmCNV0_WB_ENABLE … #define mmCNV0_WB_ENABLE_BASE_IDX … #define mmCNV0_WB_EC_CONFIG … #define mmCNV0_WB_EC_CONFIG_BASE_IDX … #define mmCNV0_CNV_MODE … #define mmCNV0_CNV_MODE_BASE_IDX … #define mmCNV0_CNV_WINDOW_START … #define mmCNV0_CNV_WINDOW_START_BASE_IDX … #define mmCNV0_CNV_WINDOW_SIZE … #define mmCNV0_CNV_WINDOW_SIZE_BASE_IDX … #define mmCNV0_CNV_UPDATE … #define mmCNV0_CNV_UPDATE_BASE_IDX … #define mmCNV0_CNV_SOURCE_SIZE … #define mmCNV0_CNV_SOURCE_SIZE_BASE_IDX … #define mmCNV0_CNV_CSC_CONTROL … #define mmCNV0_CNV_CSC_CONTROL_BASE_IDX … #define mmCNV0_CNV_CSC_C11_C12 … #define mmCNV0_CNV_CSC_C11_C12_BASE_IDX … #define mmCNV0_CNV_CSC_C13_C14 … #define mmCNV0_CNV_CSC_C13_C14_BASE_IDX … #define mmCNV0_CNV_CSC_C21_C22 … #define mmCNV0_CNV_CSC_C21_C22_BASE_IDX … #define mmCNV0_CNV_CSC_C23_C24 … #define mmCNV0_CNV_CSC_C23_C24_BASE_IDX … #define mmCNV0_CNV_CSC_C31_C32 … #define mmCNV0_CNV_CSC_C31_C32_BASE_IDX … #define mmCNV0_CNV_CSC_C33_C34 … #define mmCNV0_CNV_CSC_C33_C34_BASE_IDX … #define mmCNV0_CNV_CSC_ROUND_OFFSET_R … #define mmCNV0_CNV_CSC_ROUND_OFFSET_R_BASE_IDX … #define mmCNV0_CNV_CSC_ROUND_OFFSET_G … #define mmCNV0_CNV_CSC_ROUND_OFFSET_G_BASE_IDX … #define mmCNV0_CNV_CSC_ROUND_OFFSET_B … #define mmCNV0_CNV_CSC_ROUND_OFFSET_B_BASE_IDX … #define mmCNV0_CNV_CSC_CLAMP_R … #define mmCNV0_CNV_CSC_CLAMP_R_BASE_IDX … #define mmCNV0_CNV_CSC_CLAMP_G … #define mmCNV0_CNV_CSC_CLAMP_G_BASE_IDX … #define mmCNV0_CNV_CSC_CLAMP_B … #define mmCNV0_CNV_CSC_CLAMP_B_BASE_IDX … #define mmCNV0_CNV_TEST_CNTL … #define mmCNV0_CNV_TEST_CNTL_BASE_IDX … #define mmCNV0_CNV_TEST_CRC_RED … #define mmCNV0_CNV_TEST_CRC_RED_BASE_IDX … #define mmCNV0_CNV_TEST_CRC_GREEN … #define mmCNV0_CNV_TEST_CRC_GREEN_BASE_IDX … #define mmCNV0_CNV_TEST_CRC_BLUE … #define mmCNV0_CNV_TEST_CRC_BLUE_BASE_IDX … #define mmCNV0_CNV_INPUT_SELECT … #define mmCNV0_CNV_INPUT_SELECT_BASE_IDX … #define mmCNV0_WB_SOFT_RESET … #define mmCNV0_WB_SOFT_RESET_BASE_IDX … #define mmCNV0_WB_WARM_UP_MODE_CTL1 … #define mmCNV0_WB_WARM_UP_MODE_CTL1_BASE_IDX … #define mmCNV0_WB_WARM_UP_MODE_CTL2 … #define mmCNV0_WB_WARM_UP_MODE_CTL2_BASE_IDX … // addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec // base address: 0x0 #define mmWBSCL0_WBSCL_COEF_RAM_SELECT … #define mmWBSCL0_WBSCL_COEF_RAM_SELECT_BASE_IDX … #define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA … #define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmWBSCL0_WBSCL_MODE … #define mmWBSCL0_WBSCL_MODE_BASE_IDX … #define mmWBSCL0_WBSCL_TAP_CONTROL … #define mmWBSCL0_WBSCL_TAP_CONTROL_BASE_IDX … #define mmWBSCL0_WBSCL_DEST_SIZE … #define mmWBSCL0_WBSCL_DEST_SIZE_BASE_IDX … #define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO … #define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB … #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX … #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR … #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX … #define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO … #define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB … #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX … #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR … #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX … #define mmWBSCL0_WBSCL_ROUND_OFFSET … #define mmWBSCL0_WBSCL_ROUND_OFFSET_BASE_IDX … #define mmWBSCL0_WBSCL_CLAMP … #define mmWBSCL0_WBSCL_CLAMP_BASE_IDX … #define mmWBSCL0_WBSCL_OVERFLOW_STATUS … #define mmWBSCL0_WBSCL_OVERFLOW_STATUS_BASE_IDX … #define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS … #define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX … #define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY … #define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX … #define mmWBSCL0_WBSCL_TEST_CNTL … #define mmWBSCL0_WBSCL_TEST_CNTL_BASE_IDX … #define mmWBSCL0_WBSCL_TEST_CRC_RED … #define mmWBSCL0_WBSCL_TEST_CRC_RED_BASE_IDX … #define mmWBSCL0_WBSCL_TEST_CRC_GREEN … #define mmWBSCL0_WBSCL_TEST_CRC_GREEN_BASE_IDX … #define mmWBSCL0_WBSCL_TEST_CRC_BLUE … #define mmWBSCL0_WBSCL_TEST_CRC_BLUE_BASE_IDX … #define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN … #define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX … #define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT … #define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX … #define mmWBSCL0_WBSCL_RAM_SHUTDOWN … #define mmWBSCL0_WBSCL_RAM_SHUTDOWN_BASE_IDX … // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec // base address: 0x8e8 #define mmDC_PERFMON3_PERFCOUNTER_CNTL … #define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON3_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON3_PERFCOUNTER_STATE … #define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON3_PERFMON_CNTL … #define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON3_PERFMON_CNTL2 … #define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON3_PERFMON_CVALUE_LOW … #define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON3_PERFMON_HI … #define mmDC_PERFMON3_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON3_PERFMON_LOW … #define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_wb1_dispdec_cnv_dispdec // base address: 0x1b0 #define mmCNV1_WB_ENABLE … #define mmCNV1_WB_ENABLE_BASE_IDX … #define mmCNV1_WB_EC_CONFIG … #define mmCNV1_WB_EC_CONFIG_BASE_IDX … #define mmCNV1_CNV_MODE … #define mmCNV1_CNV_MODE_BASE_IDX … #define mmCNV1_CNV_WINDOW_START … #define mmCNV1_CNV_WINDOW_START_BASE_IDX … #define mmCNV1_CNV_WINDOW_SIZE … #define mmCNV1_CNV_WINDOW_SIZE_BASE_IDX … #define mmCNV1_CNV_UPDATE … #define mmCNV1_CNV_UPDATE_BASE_IDX … #define mmCNV1_CNV_SOURCE_SIZE … #define mmCNV1_CNV_SOURCE_SIZE_BASE_IDX … #define mmCNV1_CNV_CSC_CONTROL … #define mmCNV1_CNV_CSC_CONTROL_BASE_IDX … #define mmCNV1_CNV_CSC_C11_C12 … #define mmCNV1_CNV_CSC_C11_C12_BASE_IDX … #define mmCNV1_CNV_CSC_C13_C14 … #define mmCNV1_CNV_CSC_C13_C14_BASE_IDX … #define mmCNV1_CNV_CSC_C21_C22 … #define mmCNV1_CNV_CSC_C21_C22_BASE_IDX … #define mmCNV1_CNV_CSC_C23_C24 … #define mmCNV1_CNV_CSC_C23_C24_BASE_IDX … #define mmCNV1_CNV_CSC_C31_C32 … #define mmCNV1_CNV_CSC_C31_C32_BASE_IDX … #define mmCNV1_CNV_CSC_C33_C34 … #define mmCNV1_CNV_CSC_C33_C34_BASE_IDX … #define mmCNV1_CNV_CSC_ROUND_OFFSET_R … #define mmCNV1_CNV_CSC_ROUND_OFFSET_R_BASE_IDX … #define mmCNV1_CNV_CSC_ROUND_OFFSET_G … #define mmCNV1_CNV_CSC_ROUND_OFFSET_G_BASE_IDX … #define mmCNV1_CNV_CSC_ROUND_OFFSET_B … #define mmCNV1_CNV_CSC_ROUND_OFFSET_B_BASE_IDX … #define mmCNV1_CNV_CSC_CLAMP_R … #define mmCNV1_CNV_CSC_CLAMP_R_BASE_IDX … #define mmCNV1_CNV_CSC_CLAMP_G … #define mmCNV1_CNV_CSC_CLAMP_G_BASE_IDX … #define mmCNV1_CNV_CSC_CLAMP_B … #define mmCNV1_CNV_CSC_CLAMP_B_BASE_IDX … #define mmCNV1_CNV_TEST_CNTL … #define mmCNV1_CNV_TEST_CNTL_BASE_IDX … #define mmCNV1_CNV_TEST_CRC_RED … #define mmCNV1_CNV_TEST_CRC_RED_BASE_IDX … #define mmCNV1_CNV_TEST_CRC_GREEN … #define mmCNV1_CNV_TEST_CRC_GREEN_BASE_IDX … #define mmCNV1_CNV_TEST_CRC_BLUE … #define mmCNV1_CNV_TEST_CRC_BLUE_BASE_IDX … #define mmCNV1_CNV_INPUT_SELECT … #define mmCNV1_CNV_INPUT_SELECT_BASE_IDX … #define mmCNV1_WB_SOFT_RESET … #define mmCNV1_WB_SOFT_RESET_BASE_IDX … #define mmCNV1_WB_WARM_UP_MODE_CTL1 … #define mmCNV1_WB_WARM_UP_MODE_CTL1_BASE_IDX … #define mmCNV1_WB_WARM_UP_MODE_CTL2 … #define mmCNV1_WB_WARM_UP_MODE_CTL2_BASE_IDX … // addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec // base address: 0x1b0 #define mmWBSCL1_WBSCL_COEF_RAM_SELECT … #define mmWBSCL1_WBSCL_COEF_RAM_SELECT_BASE_IDX … #define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA … #define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmWBSCL1_WBSCL_MODE … #define mmWBSCL1_WBSCL_MODE_BASE_IDX … #define mmWBSCL1_WBSCL_TAP_CONTROL … #define mmWBSCL1_WBSCL_TAP_CONTROL_BASE_IDX … #define mmWBSCL1_WBSCL_DEST_SIZE … #define mmWBSCL1_WBSCL_DEST_SIZE_BASE_IDX … #define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO … #define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB … #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX … #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR … #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX … #define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO … #define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB … #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX … #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR … #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX … #define mmWBSCL1_WBSCL_ROUND_OFFSET … #define mmWBSCL1_WBSCL_ROUND_OFFSET_BASE_IDX … #define mmWBSCL1_WBSCL_CLAMP … #define mmWBSCL1_WBSCL_CLAMP_BASE_IDX … #define mmWBSCL1_WBSCL_OVERFLOW_STATUS … #define mmWBSCL1_WBSCL_OVERFLOW_STATUS_BASE_IDX … #define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS … #define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX … #define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY … #define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX … #define mmWBSCL1_WBSCL_TEST_CNTL … #define mmWBSCL1_WBSCL_TEST_CNTL_BASE_IDX … #define mmWBSCL1_WBSCL_TEST_CRC_RED … #define mmWBSCL1_WBSCL_TEST_CRC_RED_BASE_IDX … #define mmWBSCL1_WBSCL_TEST_CRC_GREEN … #define mmWBSCL1_WBSCL_TEST_CRC_GREEN_BASE_IDX … #define mmWBSCL1_WBSCL_TEST_CRC_BLUE … #define mmWBSCL1_WBSCL_TEST_CRC_BLUE_BASE_IDX … #define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN … #define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX … #define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT … #define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX … #define mmWBSCL1_WBSCL_RAM_SHUTDOWN … #define mmWBSCL1_WBSCL_RAM_SHUTDOWN_BASE_IDX … // addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec // base address: 0xa98 #define mmDC_PERFMON4_PERFCOUNTER_CNTL … #define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON4_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON4_PERFCOUNTER_STATE … #define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON4_PERFMON_CNTL … #define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON4_PERFMON_CNTL2 … #define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON4_PERFMON_CVALUE_LOW … #define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON4_PERFMON_HI … #define mmDC_PERFMON4_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON4_PERFMON_LOW … #define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec // base address: 0x0 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL … #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R … #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS … #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_PITCH … #define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS … #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 … #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL … #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE … #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET … #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL … #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK … #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL … #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_WATERMARK … #define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL … #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL … #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL … #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX … #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL … #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE … #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX … #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE … #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX … // addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec // base address: 0x100 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL … #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R … #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS … #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_PITCH … #define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS … #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 … #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL … #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE … #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET … #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL … #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK … #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL … #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_WATERMARK … #define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL … #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL … #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL … #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX … #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL … #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE … #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX … #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE … #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX … // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec // base address: 0x0 #define mmWBIF0_MISC_CTRL … #define mmWBIF0_MISC_CTRL_BASE_IDX … #define mmWBIF0_SMU_WM_CONTROL … #define mmWBIF0_SMU_WM_CONTROL_BASE_IDX … #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER … #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX … #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER … #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX … #define mmWBIF1_MISC_CTRL … #define mmWBIF1_MISC_CTRL_BASE_IDX … #define mmWBIF1_SMU_WM_CONTROL … #define mmWBIF1_SMU_WM_CONTROL_BASE_IDX … #define mmWBIF1_PHASE0_OUTSTANDING_COUNTER … #define mmWBIF1_PHASE0_OUTSTANDING_COUNTER_BASE_IDX … #define mmWBIF1_PHASE1_OUTSTANDING_COUNTER … #define mmWBIF1_PHASE1_OUTSTANDING_COUNTER_BASE_IDX … #define mmVGA_SRC_SPLIT_CNTL … #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX … #define mmMMHUBBUB_MEM_PWR_STATUS … #define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX … #define mmMMHUBBUB_MEM_PWR_CNTL … #define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX … #define mmMMHUBBUB_CLOCK_CNTL … #define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX … #define mmMMHUBBUB_SOFT_RESET … #define mmMMHUBBUB_SOFT_RESET_BASE_IDX … // addressBlock: dce_dc_mmhubbub_vgaif_dispdec // base address: 0x0 #define mmMCIF_CONTROL … #define mmMCIF_CONTROL_BASE_IDX … #define mmMCIF_WRITE_COMBINE_CONTROL … #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX … #define mmMCIF_PHASE0_OUTSTANDING_COUNTER … #define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX … #define mmMCIF_PHASE1_OUTSTANDING_COUNTER … #define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX … #define mmMCIF_PHASE2_OUTSTANDING_COUNTER … #define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX … // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec // base address: 0xd48 #define mmDC_PERFMON5_PERFCOUNTER_CNTL … #define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON5_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON5_PERFCOUNTER_STATE … #define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON5_PERFMON_CNTL … #define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON5_PERFMON_CNTL2 … #define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON5_PERFMON_CVALUE_LOW … #define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON5_PERFMON_HI … #define mmDC_PERFMON5_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON5_PERFMON_LOW … #define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream0_dispdec // base address: 0x0 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX … #define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM0_AZALIA_STREAM_DATA … #define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream1_dispdec // base address: 0x8 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX … #define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM1_AZALIA_STREAM_DATA … #define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream2_dispdec // base address: 0x10 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX … #define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM2_AZALIA_STREAM_DATA … #define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream3_dispdec // base address: 0x18 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX … #define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM3_AZALIA_STREAM_DATA … #define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream4_dispdec // base address: 0x20 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX … #define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM4_AZALIA_STREAM_DATA … #define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream5_dispdec // base address: 0x28 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX … #define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM5_AZALIA_STREAM_DATA … #define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream6_dispdec // base address: 0x30 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX … #define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM6_AZALIA_STREAM_DATA … #define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream7_dispdec // base address: 0x38 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX … #define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM7_AZALIA_STREAM_DATA … #define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_az_misc_dispdec // base address: 0x0 #define mmAZ_CLOCK_CNTL … #define mmAZ_CLOCK_CNTL_BASE_IDX … // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec // base address: 0xde8 #define mmDC_PERFMON6_PERFCOUNTER_CNTL … #define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON6_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON6_PERFCOUNTER_STATE … #define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON6_PERFMON_CNTL … #define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON6_PERFMON_CNTL2 … #define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON6_PERFMON_CVALUE_LOW … #define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON6_PERFMON_HI … #define mmDC_PERFMON6_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON6_PERFMON_LOW … #define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_hda_azf0endpoint0_dispdec // base address: 0x0 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0endpoint1_dispdec // base address: 0x18 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0endpoint2_dispdec // base address: 0x30 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0endpoint3_dispdec // base address: 0x48 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0endpoint4_dispdec // base address: 0x60 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0endpoint5_dispdec // base address: 0x78 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0endpoint6_dispdec // base address: 0x90 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0endpoint7_dispdec // base address: 0xa8 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0controller_dispdec // base address: 0x0 #define mmAZALIA_CONTROLLER_CLOCK_GATING … #define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX … #define mmAZALIA_AUDIO_DTO … #define mmAZALIA_AUDIO_DTO_BASE_IDX … #define mmAZALIA_AUDIO_DTO_CONTROL … #define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX … #define mmAZALIA_SOCCLK_CONTROL … #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX … #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE … #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX … #define mmAZALIA_DATA_DMA_CONTROL … #define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX … #define mmAZALIA_BDL_DMA_CONTROL … #define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX … #define mmAZALIA_RIRB_AND_DP_CONTROL … #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX … #define mmAZALIA_CORB_DMA_CONTROL … #define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX … #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER … #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX … #define mmAZALIA_CYCLIC_BUFFER_SYNC … #define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX … #define mmAZALIA_GLOBAL_CAPABILITIES … #define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX … #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY … #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX … #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL … #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX … #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY … #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL0 … #define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL1 … #define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL2 … #define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL3 … #define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX … #define mmAZALIA_INPUT_CRC0_RESULT … #define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL0 … #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL1 … #define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL2 … #define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL3 … #define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX … #define mmAZALIA_INPUT_CRC1_RESULT … #define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX … #define mmAZALIA_CRC0_CONTROL0 … #define mmAZALIA_CRC0_CONTROL0_BASE_IDX … #define mmAZALIA_CRC0_CONTROL1 … #define mmAZALIA_CRC0_CONTROL1_BASE_IDX … #define mmAZALIA_CRC0_CONTROL2 … #define mmAZALIA_CRC0_CONTROL2_BASE_IDX … #define mmAZALIA_CRC0_CONTROL3 … #define mmAZALIA_CRC0_CONTROL3_BASE_IDX … #define mmAZALIA_CRC0_RESULT … #define mmAZALIA_CRC0_RESULT_BASE_IDX … #define mmAZALIA_CRC1_CONTROL0 … #define mmAZALIA_CRC1_CONTROL0_BASE_IDX … #define mmAZALIA_CRC1_CONTROL1 … #define mmAZALIA_CRC1_CONTROL1_BASE_IDX … #define mmAZALIA_CRC1_CONTROL2 … #define mmAZALIA_CRC1_CONTROL2_BASE_IDX … #define mmAZALIA_CRC1_CONTROL3 … #define mmAZALIA_CRC1_CONTROL3_BASE_IDX … #define mmAZALIA_CRC1_RESULT … #define mmAZALIA_CRC1_RESULT_BASE_IDX … #define mmAZALIA_MEM_PWR_CTRL … #define mmAZALIA_MEM_PWR_CTRL_BASE_IDX … #define mmAZALIA_MEM_PWR_STATUS … #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_hda_azf0root_dispdec // base address: 0x0 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX … #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL … #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL … #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX … #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY … #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX … #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY … #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET0 … #define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET1 … #define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET2 … #define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET3 … #define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET4 … #define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET5 … #define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX … #define mmAZALIA_F0_GTC_GROUP_OFFSET6 … #define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX … #define mmREG_DC_AUDIO_PORT_CONNECTIVITY … #define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX … #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY … #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream8_dispdec // base address: 0x320 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX … #define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM8_AZALIA_STREAM_DATA … #define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream9_dispdec // base address: 0x328 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX … #define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM9_AZALIA_STREAM_DATA … #define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream10_dispdec // base address: 0x330 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX … #define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM10_AZALIA_STREAM_DATA … #define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream11_dispdec // base address: 0x338 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX … #define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM11_AZALIA_STREAM_DATA … #define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream12_dispdec // base address: 0x340 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX … #define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM12_AZALIA_STREAM_DATA … #define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream13_dispdec // base address: 0x348 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX … #define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM13_AZALIA_STREAM_DATA … #define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream14_dispdec // base address: 0x350 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX … #define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM14_AZALIA_STREAM_DATA … #define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0stream15_dispdec // base address: 0x358 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX … #define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX … #define mmAZF0STREAM15_AZALIA_STREAM_DATA … #define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec // base address: 0x0 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec // base address: 0x10 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec // base address: 0x20 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec // base address: 0x30 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec // base address: 0x40 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec // base address: 0x50 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec // base address: 0x60 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec // base address: 0x70 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec // base address: 0x0 #define mmDCHUBBUB_SDPIF_CFG0 … #define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX … #define mmDCHUBBUB_SDPIF_CFG1 … #define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX … #define mmDCHUBBUB_FORCE_IO_STATUS_0 … #define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX … #define mmDCHUBBUB_FORCE_IO_STATUS_1 … #define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX … #define mmDCHUBBUB_SDPIF_FB_BASE … #define mmDCHUBBUB_SDPIF_FB_BASE_BASE_IDX … #define mmDCHUBBUB_SDPIF_FB_TOP … #define mmDCHUBBUB_SDPIF_FB_TOP_BASE_IDX … #define mmDCHUBBUB_SDPIF_FB_OFFSET … #define mmDCHUBBUB_SDPIF_FB_OFFSET_BASE_IDX … #define mmDCHUBBUB_SDPIF_AGP_BOT … #define mmDCHUBBUB_SDPIF_AGP_BOT_BASE_IDX … #define mmDCHUBBUB_SDPIF_AGP_TOP … #define mmDCHUBBUB_SDPIF_AGP_TOP_BASE_IDX … #define mmDCHUBBUB_SDPIF_AGP_BASE … #define mmDCHUBBUB_SDPIF_AGP_BASE_BASE_IDX … #define mmDCHUBBUB_SDPIF_APER_BASE … #define mmDCHUBBUB_SDPIF_APER_BASE_BASE_IDX … #define mmDCHUBBUB_SDPIF_APER_TOP … #define mmDCHUBBUB_SDPIF_APER_TOP_BASE_IDX … #define mmDCHUBBUB_SDPIF_APER_DEF_0 … #define mmDCHUBBUB_SDPIF_APER_DEF_0_BASE_IDX … #define mmDCHUBBUB_SDPIF_APER_DEF_1 … #define mmDCHUBBUB_SDPIF_APER_DEF_1_BASE_IDX … #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 … #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX … #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1 … #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1_BASE_IDX … #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W … #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0 … #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0 … #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0 … #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0 … #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0 … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0 … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1 … #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1 … #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1 … #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1 … #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1 … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1 … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2 … #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2 … #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2 … #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2 … #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2 … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2 … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3 … #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3 … #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3 … #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3 … #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3 … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3_BASE_IDX … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3 … #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3_BASE_IDX … #define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL … #define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX … #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL … #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX … #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS … #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec // base address: 0x0 #define mmDCHUBBUB_RET_PATH_DCC_CFG … #define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL … #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX … #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS … #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX … #define mmDCHUBBUB_CRC_CTRL … #define mmDCHUBBUB_CRC_CTRL_BASE_IDX … #define mmDCHUBBUB_CRC0_VAL_R_G … #define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX … #define mmDCHUBBUB_CRC0_VAL_B_A … #define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX … #define mmDCHUBBUB_CRC1_VAL_R_G … #define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX … #define mmDCHUBBUB_CRC1_VAL_B_A … #define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX … // addressBlock: dce_dc_dchubbub_hubbub_dispdec // base address: 0x0 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND … #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX … #define mmDCHUBBUB_ARB_SAT_LEVEL … #define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX … #define mmDCHUBBUB_ARB_QOS_FORCE … #define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX … #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL … #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A … #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A … #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B … #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B … #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C … #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C … #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D … #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D … #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX … #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL … #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX … #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE … #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX … #define mmDCHUBBUB_GLOBAL_TIMER_CNTL … #define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX … #define mmSURFACE_CHECK0_ADDRESS_LSB … #define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX … #define mmSURFACE_CHECK0_ADDRESS_MSB … #define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX … #define mmSURFACE_CHECK1_ADDRESS_LSB … #define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX … #define mmSURFACE_CHECK1_ADDRESS_MSB … #define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX … #define mmSURFACE_CHECK2_ADDRESS_LSB … #define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX … #define mmSURFACE_CHECK2_ADDRESS_MSB … #define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX … #define mmSURFACE_CHECK3_ADDRESS_LSB … #define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX … #define mmSURFACE_CHECK3_ADDRESS_MSB … #define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX … #define mmVTG0_CONTROL … #define mmVTG0_CONTROL_BASE_IDX … #define mmVTG1_CONTROL … #define mmVTG1_CONTROL_BASE_IDX … #define mmVTG2_CONTROL … #define mmVTG2_CONTROL_BASE_IDX … #define mmVTG3_CONTROL … #define mmVTG3_CONTROL_BASE_IDX … #define mmVTG4_CONTROL … #define mmVTG4_CONTROL_BASE_IDX … #define mmVTG5_CONTROL … #define mmVTG5_CONTROL_BASE_IDX … #define mmDCHUBBUB_SOFT_RESET … #define mmDCHUBBUB_SOFT_RESET_BASE_IDX … #define mmDCHUBBUB_CLOCK_CNTL … #define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX … #define mmDCFCLK_CNTL … #define mmDCFCLK_CNTL_BASE_IDX … #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL … #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX … #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 … #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX … #define mmDCHUBBUB_VLINE_SNAPSHOT … #define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX … #define mmDCHUBBUB_SPARE … #define mmDCHUBBUB_SPARE_BASE_IDX … #define mmDCHUBBUB_TEST_DEBUG_INDEX … #define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX … #define mmDCHUBBUB_TEST_DEBUG_DATA … #define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec // base address: 0x1534 #define mmDC_PERFMON7_PERFCOUNTER_CNTL … #define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON7_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON7_PERFCOUNTER_STATE … #define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON7_PERFMON_CNTL … #define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON7_PERFMON_CNTL2 … #define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON7_PERFMON_CVALUE_LOW … #define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON7_PERFMON_HI … #define mmDC_PERFMON7_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON7_PERFMON_LOW … #define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec // base address: 0x0 #define mmHUBP0_DCSURF_SURFACE_CONFIG … #define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX … #define mmHUBP0_DCSURF_ADDR_CONFIG … #define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX … #define mmHUBP0_DCSURF_TILING_CONFIG … #define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX … #define mmHUBP0_DCSURF_PRI_VIEWPORT_START … #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION … #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C … #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP0_DCSURF_SEC_VIEWPORT_START … #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION … #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C … #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG … #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C … #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define mmHUBP0_DCHUBP_CNTL … #define mmHUBP0_DCHUBP_CNTL_BASE_IDX … #define mmHUBP0_HUBP_CLK_CNTL … #define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX … #define mmHUBP0_DCHUBP_VMPG_CONFIG … #define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX … #define mmHUBP0_HUBPREQ_DEBUG_DB … #define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX … #define mmHUBP0_HUBPREQ_DEBUG … #define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX … #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec // base address: 0x0 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH … #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C … #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL … #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX … #define mmHUBPREQ0_DCSURF_FLIP_CONTROL … #define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX … #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 … #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX … #define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL … #define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL_BASE_IDX … #define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME … #define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT … #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCN_EXPANSION_MODE … #define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX … #define mmHUBPREQ0_DCN_TTU_QOS_WM … #define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX … #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL … #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 … #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 … #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 … #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 … #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 … #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 … #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS … #define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS_BASE_IDX … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB … #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL … #define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL_BASE_IDX … #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL … #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX … #define mmHUBPREQ0_BLANK_OFFSET_0 … #define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX … #define mmHUBPREQ0_BLANK_OFFSET_1 … #define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX … #define mmHUBPREQ0_DST_DIMENSIONS … #define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX … #define mmHUBPREQ0_DST_AFTER_SCALER … #define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX … #define mmHUBPREQ0_PREFETCH_SETTINS … #define mmHUBPREQ0_PREFETCH_SETTINS_BASE_IDX … #define mmHUBPREQ0_PREFETCH_SETTINS_C … #define mmHUBPREQ0_PREFETCH_SETTINS_C_BASE_IDX … #define mmHUBPREQ0_VBLANK_PARAMETERS_0 … #define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ0_VBLANK_PARAMETERS_1 … #define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ0_VBLANK_PARAMETERS_2 … #define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ0_VBLANK_PARAMETERS_3 … #define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ0_VBLANK_PARAMETERS_4 … #define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_0 … #define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_1 … #define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_2 … #define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_3 … #define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_4 … #define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_5 … #define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_6 … #define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_7 … #define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX … #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE … #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX … #define mmHUBPREQ0_PER_LINE_DELIVERY … #define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX … #define mmHUBPREQ0_CURSOR_SETTINS … #define mmHUBPREQ0_CURSOR_SETTINS_BASE_IDX … #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ … #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL … #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS … #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec // base address: 0x0 #define mmHUBPRET0_HUBPRET_CONTROL … #define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX … #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL … #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS … #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 … #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 … #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE0 … #define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE1 … #define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX … #define mmHUBPRET0_HUBPRET_INTERRUPT … #define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE … #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS … #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec // base address: 0x0 #define mmCURSOR0_CURSOR_CONTROL … #define mmCURSOR0_CURSOR_CONTROL_BASE_IDX … #define mmCURSOR0_CURSOR_SURFACE_ADDRESS … #define mmCURSOR0_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH … #define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR0_CURSOR_SIZE … #define mmCURSOR0_CURSOR_SIZE_BASE_IDX … #define mmCURSOR0_CURSOR_POSITION … #define mmCURSOR0_CURSOR_POSITION_BASE_IDX … #define mmCURSOR0_CURSOR_HOT_SPOT … #define mmCURSOR0_CURSOR_HOT_SPOT_BASE_IDX … #define mmCURSOR0_CURSOR_STEREO_CONTROL … #define mmCURSOR0_CURSOR_STEREO_CONTROL_BASE_IDX … #define mmCURSOR0_CURSOR_DST_OFFSET … #define mmCURSOR0_CURSOR_DST_OFFSET_BASE_IDX … #define mmCURSOR0_CURSOR_MEM_PWR_CTRL … #define mmCURSOR0_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define mmCURSOR0_CURSOR_MEM_PWR_STATUS … #define mmCURSOR0_CURSOR_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec // base address: 0x1844 #define mmDC_PERFMON8_PERFCOUNTER_CNTL … #define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON8_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON8_PERFCOUNTER_STATE … #define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON8_PERFMON_CNTL … #define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON8_PERFMON_CNTL2 … #define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON8_PERFMON_CVALUE_LOW … #define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON8_PERFMON_HI … #define mmDC_PERFMON8_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON8_PERFMON_LOW … #define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec // base address: 0x310 #define mmHUBP1_DCSURF_SURFACE_CONFIG … #define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX … #define mmHUBP1_DCSURF_ADDR_CONFIG … #define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX … #define mmHUBP1_DCSURF_TILING_CONFIG … #define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX … #define mmHUBP1_DCSURF_PRI_VIEWPORT_START … #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION … #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C … #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP1_DCSURF_SEC_VIEWPORT_START … #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION … #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C … #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG … #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C … #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define mmHUBP1_DCHUBP_CNTL … #define mmHUBP1_DCHUBP_CNTL_BASE_IDX … #define mmHUBP1_HUBP_CLK_CNTL … #define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX … #define mmHUBP1_DCHUBP_VMPG_CONFIG … #define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX … #define mmHUBP1_HUBPREQ_DEBUG_DB … #define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX … #define mmHUBP1_HUBPREQ_DEBUG … #define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX … #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec // base address: 0x310 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH … #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C … #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL … #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX … #define mmHUBPREQ1_DCSURF_FLIP_CONTROL … #define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX … #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 … #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX … #define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL … #define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL_BASE_IDX … #define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME … #define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT … #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCN_EXPANSION_MODE … #define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX … #define mmHUBPREQ1_DCN_TTU_QOS_WM … #define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX … #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL … #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 … #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 … #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 … #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 … #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 … #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 … #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS … #define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS_BASE_IDX … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB … #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL … #define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL_BASE_IDX … #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL … #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX … #define mmHUBPREQ1_BLANK_OFFSET_0 … #define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX … #define mmHUBPREQ1_BLANK_OFFSET_1 … #define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX … #define mmHUBPREQ1_DST_DIMENSIONS … #define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX … #define mmHUBPREQ1_DST_AFTER_SCALER … #define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX … #define mmHUBPREQ1_PREFETCH_SETTINS … #define mmHUBPREQ1_PREFETCH_SETTINS_BASE_IDX … #define mmHUBPREQ1_PREFETCH_SETTINS_C … #define mmHUBPREQ1_PREFETCH_SETTINS_C_BASE_IDX … #define mmHUBPREQ1_VBLANK_PARAMETERS_0 … #define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ1_VBLANK_PARAMETERS_1 … #define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ1_VBLANK_PARAMETERS_2 … #define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ1_VBLANK_PARAMETERS_3 … #define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ1_VBLANK_PARAMETERS_4 … #define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_0 … #define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_1 … #define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_2 … #define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_3 … #define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_4 … #define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_5 … #define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_6 … #define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_7 … #define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX … #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE … #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX … #define mmHUBPREQ1_PER_LINE_DELIVERY … #define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX … #define mmHUBPREQ1_CURSOR_SETTINS … #define mmHUBPREQ1_CURSOR_SETTINS_BASE_IDX … #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ … #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL … #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS … #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec // base address: 0x310 #define mmHUBPRET1_HUBPRET_CONTROL … #define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX … #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL … #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS … #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 … #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 … #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE0 … #define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE1 … #define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX … #define mmHUBPRET1_HUBPRET_INTERRUPT … #define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE … #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS … #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec // base address: 0x310 #define mmCURSOR1_CURSOR_CONTROL … #define mmCURSOR1_CURSOR_CONTROL_BASE_IDX … #define mmCURSOR1_CURSOR_SURFACE_ADDRESS … #define mmCURSOR1_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH … #define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR1_CURSOR_SIZE … #define mmCURSOR1_CURSOR_SIZE_BASE_IDX … #define mmCURSOR1_CURSOR_POSITION … #define mmCURSOR1_CURSOR_POSITION_BASE_IDX … #define mmCURSOR1_CURSOR_HOT_SPOT … #define mmCURSOR1_CURSOR_HOT_SPOT_BASE_IDX … #define mmCURSOR1_CURSOR_STEREO_CONTROL … #define mmCURSOR1_CURSOR_STEREO_CONTROL_BASE_IDX … #define mmCURSOR1_CURSOR_DST_OFFSET … #define mmCURSOR1_CURSOR_DST_OFFSET_BASE_IDX … #define mmCURSOR1_CURSOR_MEM_PWR_CTRL … #define mmCURSOR1_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define mmCURSOR1_CURSOR_MEM_PWR_STATUS … #define mmCURSOR1_CURSOR_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec // base address: 0x1b54 #define mmDC_PERFMON9_PERFCOUNTER_CNTL … #define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON9_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON9_PERFCOUNTER_STATE … #define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON9_PERFMON_CNTL … #define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON9_PERFMON_CNTL2 … #define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON9_PERFMON_CVALUE_LOW … #define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON9_PERFMON_HI … #define mmDC_PERFMON9_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON9_PERFMON_LOW … #define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec // base address: 0x620 #define mmHUBP2_DCSURF_SURFACE_CONFIG … #define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX … #define mmHUBP2_DCSURF_ADDR_CONFIG … #define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX … #define mmHUBP2_DCSURF_TILING_CONFIG … #define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX … #define mmHUBP2_DCSURF_PRI_VIEWPORT_START … #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION … #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C … #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP2_DCSURF_SEC_VIEWPORT_START … #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION … #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C … #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG … #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C … #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define mmHUBP2_DCHUBP_CNTL … #define mmHUBP2_DCHUBP_CNTL_BASE_IDX … #define mmHUBP2_HUBP_CLK_CNTL … #define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX … #define mmHUBP2_DCHUBP_VMPG_CONFIG … #define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX … #define mmHUBP2_HUBPREQ_DEBUG_DB … #define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX … #define mmHUBP2_HUBPREQ_DEBUG … #define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX … #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec // base address: 0x620 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH … #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C … #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL … #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX … #define mmHUBPREQ2_DCSURF_FLIP_CONTROL … #define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX … #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 … #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX … #define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL … #define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL_BASE_IDX … #define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME … #define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT … #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCN_EXPANSION_MODE … #define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX … #define mmHUBPREQ2_DCN_TTU_QOS_WM … #define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX … #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL … #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 … #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 … #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 … #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 … #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 … #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 … #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS … #define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS_BASE_IDX … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB … #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL … #define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL_BASE_IDX … #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL … #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX … #define mmHUBPREQ2_BLANK_OFFSET_0 … #define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX … #define mmHUBPREQ2_BLANK_OFFSET_1 … #define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX … #define mmHUBPREQ2_DST_DIMENSIONS … #define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX … #define mmHUBPREQ2_DST_AFTER_SCALER … #define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX … #define mmHUBPREQ2_PREFETCH_SETTINS … #define mmHUBPREQ2_PREFETCH_SETTINS_BASE_IDX … #define mmHUBPREQ2_PREFETCH_SETTINS_C … #define mmHUBPREQ2_PREFETCH_SETTINS_C_BASE_IDX … #define mmHUBPREQ2_VBLANK_PARAMETERS_0 … #define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ2_VBLANK_PARAMETERS_1 … #define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ2_VBLANK_PARAMETERS_2 … #define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ2_VBLANK_PARAMETERS_3 … #define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ2_VBLANK_PARAMETERS_4 … #define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_0 … #define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_1 … #define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_2 … #define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_3 … #define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_4 … #define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_5 … #define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_6 … #define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_7 … #define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX … #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE … #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX … #define mmHUBPREQ2_PER_LINE_DELIVERY … #define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX … #define mmHUBPREQ2_CURSOR_SETTINS … #define mmHUBPREQ2_CURSOR_SETTINS_BASE_IDX … #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ … #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL … #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS … #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec // base address: 0x620 #define mmHUBPRET2_HUBPRET_CONTROL … #define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX … #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL … #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS … #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 … #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 … #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE0 … #define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE1 … #define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX … #define mmHUBPRET2_HUBPRET_INTERRUPT … #define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE … #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS … #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec // base address: 0x620 #define mmCURSOR2_CURSOR_CONTROL … #define mmCURSOR2_CURSOR_CONTROL_BASE_IDX … #define mmCURSOR2_CURSOR_SURFACE_ADDRESS … #define mmCURSOR2_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH … #define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR2_CURSOR_SIZE … #define mmCURSOR2_CURSOR_SIZE_BASE_IDX … #define mmCURSOR2_CURSOR_POSITION … #define mmCURSOR2_CURSOR_POSITION_BASE_IDX … #define mmCURSOR2_CURSOR_HOT_SPOT … #define mmCURSOR2_CURSOR_HOT_SPOT_BASE_IDX … #define mmCURSOR2_CURSOR_STEREO_CONTROL … #define mmCURSOR2_CURSOR_STEREO_CONTROL_BASE_IDX … #define mmCURSOR2_CURSOR_DST_OFFSET … #define mmCURSOR2_CURSOR_DST_OFFSET_BASE_IDX … #define mmCURSOR2_CURSOR_MEM_PWR_CTRL … #define mmCURSOR2_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define mmCURSOR2_CURSOR_MEM_PWR_STATUS … #define mmCURSOR2_CURSOR_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec // base address: 0x1e64 #define mmDC_PERFMON10_PERFCOUNTER_CNTL … #define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON10_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON10_PERFCOUNTER_STATE … #define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON10_PERFMON_CNTL … #define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON10_PERFMON_CNTL2 … #define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON10_PERFMON_CVALUE_LOW … #define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON10_PERFMON_HI … #define mmDC_PERFMON10_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON10_PERFMON_LOW … #define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec // base address: 0x930 #define mmHUBP3_DCSURF_SURFACE_CONFIG … #define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX … #define mmHUBP3_DCSURF_ADDR_CONFIG … #define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX … #define mmHUBP3_DCSURF_TILING_CONFIG … #define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX … #define mmHUBP3_DCSURF_PRI_VIEWPORT_START … #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION … #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C … #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP3_DCSURF_SEC_VIEWPORT_START … #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION … #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C … #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG … #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C … #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define mmHUBP3_DCHUBP_CNTL … #define mmHUBP3_DCHUBP_CNTL_BASE_IDX … #define mmHUBP3_HUBP_CLK_CNTL … #define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX … #define mmHUBP3_DCHUBP_VMPG_CONFIG … #define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX … #define mmHUBP3_HUBPREQ_DEBUG_DB … #define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX … #define mmHUBP3_HUBPREQ_DEBUG … #define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX … #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec // base address: 0x930 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH … #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C … #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL … #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX … #define mmHUBPREQ3_DCSURF_FLIP_CONTROL … #define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX … #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 … #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX … #define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL … #define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL_BASE_IDX … #define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME … #define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT … #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCN_EXPANSION_MODE … #define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX … #define mmHUBPREQ3_DCN_TTU_QOS_WM … #define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX … #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL … #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 … #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 … #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 … #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 … #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 … #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 … #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB … #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS … #define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS_BASE_IDX … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB … #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX … #define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL … #define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL_BASE_IDX … #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL … #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX … #define mmHUBPREQ3_BLANK_OFFSET_0 … #define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX … #define mmHUBPREQ3_BLANK_OFFSET_1 … #define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX … #define mmHUBPREQ3_DST_DIMENSIONS … #define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX … #define mmHUBPREQ3_DST_AFTER_SCALER … #define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX … #define mmHUBPREQ3_PREFETCH_SETTINS … #define mmHUBPREQ3_PREFETCH_SETTINS_BASE_IDX … #define mmHUBPREQ3_PREFETCH_SETTINS_C … #define mmHUBPREQ3_PREFETCH_SETTINS_C_BASE_IDX … #define mmHUBPREQ3_VBLANK_PARAMETERS_0 … #define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ3_VBLANK_PARAMETERS_1 … #define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ3_VBLANK_PARAMETERS_2 … #define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ3_VBLANK_PARAMETERS_3 … #define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ3_VBLANK_PARAMETERS_4 … #define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_0 … #define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_1 … #define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_2 … #define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_3 … #define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_4 … #define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_5 … #define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_6 … #define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_7 … #define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX … #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE … #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX … #define mmHUBPREQ3_PER_LINE_DELIVERY … #define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX … #define mmHUBPREQ3_CURSOR_SETTINS … #define mmHUBPREQ3_CURSOR_SETTINS_BASE_IDX … #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ … #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL … #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS … #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec // base address: 0x930 #define mmHUBPRET3_HUBPRET_CONTROL … #define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX … #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL … #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS … #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 … #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 … #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE0 … #define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE1 … #define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX … #define mmHUBPRET3_HUBPRET_INTERRUPT … #define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE … #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS … #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec // base address: 0x930 #define mmCURSOR3_CURSOR_CONTROL … #define mmCURSOR3_CURSOR_CONTROL_BASE_IDX … #define mmCURSOR3_CURSOR_SURFACE_ADDRESS … #define mmCURSOR3_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH … #define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR3_CURSOR_SIZE … #define mmCURSOR3_CURSOR_SIZE_BASE_IDX … #define mmCURSOR3_CURSOR_POSITION … #define mmCURSOR3_CURSOR_POSITION_BASE_IDX … #define mmCURSOR3_CURSOR_HOT_SPOT … #define mmCURSOR3_CURSOR_HOT_SPOT_BASE_IDX … #define mmCURSOR3_CURSOR_STEREO_CONTROL … #define mmCURSOR3_CURSOR_STEREO_CONTROL_BASE_IDX … #define mmCURSOR3_CURSOR_DST_OFFSET … #define mmCURSOR3_CURSOR_DST_OFFSET_BASE_IDX … #define mmCURSOR3_CURSOR_MEM_PWR_CTRL … #define mmCURSOR3_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define mmCURSOR3_CURSOR_MEM_PWR_STATUS … #define mmCURSOR3_CURSOR_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec // base address: 0x2174 #define mmDC_PERFMON11_PERFCOUNTER_CNTL … #define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON11_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON11_PERFCOUNTER_STATE … #define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON11_PERFMON_CNTL … #define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON11_PERFMON_CNTL2 … #define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON11_PERFMON_CVALUE_LOW … #define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON11_PERFMON_HI … #define mmDC_PERFMON11_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON11_PERFMON_LOW … #define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec // base address: 0x0 #define mmDPP_TOP0_DPP_CONTROL … #define mmDPP_TOP0_DPP_CONTROL_BASE_IDX … #define mmDPP_TOP0_DPP_SOFT_RESET … #define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX … #define mmDPP_TOP0_DPP_CRC_VAL_R_G … #define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX … #define mmDPP_TOP0_DPP_CRC_VAL_B_A … #define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX … #define mmDPP_TOP0_DPP_CRC_CTRL … #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX … #define mmDPP_TOP0_HOST_READ_CONTROL … #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX … // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec // base address: 0x0 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT … #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define mmCNVC_CFG0_FORMAT_CONTROL … #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX … #define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS … #define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS_BASE_IDX … #define mmCNVC_CFG0_DENORM_CONTROL … #define mmCNVC_CFG0_DENORM_CONTROL_BASE_IDX … #define mmCNVC_CFG0_COLOR_KEYER_CONTROL … #define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX … #define mmCNVC_CFG0_COLOR_KEYER_ALPHA … #define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX … #define mmCNVC_CFG0_COLOR_KEYER_RED … #define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX … #define mmCNVC_CFG0_COLOR_KEYER_GREEN … #define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX … #define mmCNVC_CFG0_COLOR_KEYER_BLUE … #define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX … // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec // base address: 0x0 #define mmCNVC_CUR0_CURSOR0_CONTROL … #define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX … #define mmCNVC_CUR0_CURSOR0_COLOR0 … #define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX … #define mmCNVC_CUR0_CURSOR0_COLOR1 … #define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX … #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS … #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX … // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec // base address: 0x0 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT … #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define mmDSCL0_SCL_COEF_RAM_TAP_DATA … #define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmDSCL0_SCL_MODE … #define mmDSCL0_SCL_MODE_BASE_IDX … #define mmDSCL0_SCL_TAP_CONTROL … #define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX … #define mmDSCL0_DSCL_CONTROL … #define mmDSCL0_DSCL_CONTROL_BASE_IDX … #define mmDSCL0_DSCL_2TAP_CONTROL … #define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX … #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL … #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO … #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL0_SCL_HORZ_FILTER_INIT … #define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C … #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL0_SCL_HORZ_FILTER_INIT_C … #define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO … #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_INIT … #define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT … #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C … #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_INIT_C … #define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C … #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define mmDSCL0_SCL_BLACK_OFFSET … #define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX … #define mmDSCL0_DSCL_UPDATE … #define mmDSCL0_DSCL_UPDATE_BASE_IDX … #define mmDSCL0_DSCL_AUTOCAL … #define mmDSCL0_DSCL_AUTOCAL_BASE_IDX … #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmDSCL0_OTG_H_BLANK … #define mmDSCL0_OTG_H_BLANK_BASE_IDX … #define mmDSCL0_OTG_V_BLANK … #define mmDSCL0_OTG_V_BLANK_BASE_IDX … #define mmDSCL0_RECOUT_START … #define mmDSCL0_RECOUT_START_BASE_IDX … #define mmDSCL0_RECOUT_SIZE … #define mmDSCL0_RECOUT_SIZE_BASE_IDX … #define mmDSCL0_MPC_SIZE … #define mmDSCL0_MPC_SIZE_BASE_IDX … #define mmDSCL0_LB_DATA_FORMAT … #define mmDSCL0_LB_DATA_FORMAT_BASE_IDX … #define mmDSCL0_LB_MEMORY_CTRL … #define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX … #define mmDSCL0_LB_V_COUNTER … #define mmDSCL0_LB_V_COUNTER_BASE_IDX … #define mmDSCL0_DSCL_MEM_PWR_CTRL … #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … #define mmDSCL0_DSCL_MEM_PWR_STATUS … #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX … #define mmDSCL0_OBUF_CONTROL … #define mmDSCL0_OBUF_CONTROL_BASE_IDX … #define mmDSCL0_OBUF_MEM_PWR_CTRL … #define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec // base address: 0x0 #define mmCM0_CM_CONTROL … #define mmCM0_CM_CONTROL_BASE_IDX … #define mmCM0_CM_COMA_C11_C12 … #define mmCM0_CM_COMA_C11_C12_BASE_IDX … #define mmCM0_CM_COMA_C13_C14 … #define mmCM0_CM_COMA_C13_C14_BASE_IDX … #define mmCM0_CM_COMA_C21_C22 … #define mmCM0_CM_COMA_C21_C22_BASE_IDX … #define mmCM0_CM_COMA_C23_C24 … #define mmCM0_CM_COMA_C23_C24_BASE_IDX … #define mmCM0_CM_COMA_C31_C32 … #define mmCM0_CM_COMA_C31_C32_BASE_IDX … #define mmCM0_CM_COMA_C33_C34 … #define mmCM0_CM_COMA_C33_C34_BASE_IDX … #define mmCM0_CM_COMB_C11_C12 … #define mmCM0_CM_COMB_C11_C12_BASE_IDX … #define mmCM0_CM_COMB_C13_C14 … #define mmCM0_CM_COMB_C13_C14_BASE_IDX … #define mmCM0_CM_COMB_C21_C22 … #define mmCM0_CM_COMB_C21_C22_BASE_IDX … #define mmCM0_CM_COMB_C23_C24 … #define mmCM0_CM_COMB_C23_C24_BASE_IDX … #define mmCM0_CM_COMB_C31_C32 … #define mmCM0_CM_COMB_C31_C32_BASE_IDX … #define mmCM0_CM_COMB_C33_C34 … #define mmCM0_CM_COMB_C33_C34_BASE_IDX … #define mmCM0_CM_IGAM_CONTROL … #define mmCM0_CM_IGAM_CONTROL_BASE_IDX … #define mmCM0_CM_IGAM_LUT_RW_CONTROL … #define mmCM0_CM_IGAM_LUT_RW_CONTROL_BASE_IDX … #define mmCM0_CM_IGAM_LUT_RW_INDEX … #define mmCM0_CM_IGAM_LUT_RW_INDEX_BASE_IDX … #define mmCM0_CM_IGAM_LUT_SEQ_COLOR … #define mmCM0_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX … #define mmCM0_CM_IGAM_LUT_30_COLOR … #define mmCM0_CM_IGAM_LUT_30_COLOR_BASE_IDX … #define mmCM0_CM_IGAM_LUT_PWL_DATA … #define mmCM0_CM_IGAM_LUT_PWL_DATA_BASE_IDX … #define mmCM0_CM_IGAM_LUT_AUTOFILL … #define mmCM0_CM_IGAM_LUT_AUTOFILL_BASE_IDX … #define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE … #define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX … #define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN … #define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX … #define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED … #define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX … #define mmCM0_CM_ICSC_CONTROL … #define mmCM0_CM_ICSC_CONTROL_BASE_IDX … #define mmCM0_CM_ICSC_C11_C12 … #define mmCM0_CM_ICSC_C11_C12_BASE_IDX … #define mmCM0_CM_ICSC_C13_C14 … #define mmCM0_CM_ICSC_C13_C14_BASE_IDX … #define mmCM0_CM_ICSC_C21_C22 … #define mmCM0_CM_ICSC_C21_C22_BASE_IDX … #define mmCM0_CM_ICSC_C23_C24 … #define mmCM0_CM_ICSC_C23_C24_BASE_IDX … #define mmCM0_CM_ICSC_C31_C32 … #define mmCM0_CM_ICSC_C31_C32_BASE_IDX … #define mmCM0_CM_ICSC_C33_C34 … #define mmCM0_CM_ICSC_C33_C34_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_CONTROL … #define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C11_C12 … #define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C13_C14 … #define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C21_C22 … #define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C23_C24 … #define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C31_C32 … #define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C33_C34 … #define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmCM0_CM_OCSC_CONTROL … #define mmCM0_CM_OCSC_CONTROL_BASE_IDX … #define mmCM0_CM_OCSC_C11_C12 … #define mmCM0_CM_OCSC_C11_C12_BASE_IDX … #define mmCM0_CM_OCSC_C13_C14 … #define mmCM0_CM_OCSC_C13_C14_BASE_IDX … #define mmCM0_CM_OCSC_C21_C22 … #define mmCM0_CM_OCSC_C21_C22_BASE_IDX … #define mmCM0_CM_OCSC_C23_C24 … #define mmCM0_CM_OCSC_C23_C24_BASE_IDX … #define mmCM0_CM_OCSC_C31_C32 … #define mmCM0_CM_OCSC_C31_C32_BASE_IDX … #define mmCM0_CM_OCSC_C33_C34 … #define mmCM0_CM_OCSC_C33_C34_BASE_IDX … #define mmCM0_CM_BNS_VALUES_R … #define mmCM0_CM_BNS_VALUES_R_BASE_IDX … #define mmCM0_CM_BNS_VALUES_G … #define mmCM0_CM_BNS_VALUES_G_BASE_IDX … #define mmCM0_CM_BNS_VALUES_B … #define mmCM0_CM_BNS_VALUES_B_BASE_IDX … #define mmCM0_CM_DGAM_CONTROL … #define mmCM0_CM_DGAM_CONTROL_BASE_IDX … #define mmCM0_CM_DGAM_LUT_INDEX … #define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX … #define mmCM0_CM_DGAM_LUT_DATA … #define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX … #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK … #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_START_CNTL_B … #define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_START_CNTL_G … #define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_START_CNTL_R … #define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_0_1 … #define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_2_3 … #define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_4_5 … #define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_6_7 … #define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_8_9 … #define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_10_11 … #define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_12_13 … #define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_14_15 … #define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_START_CNTL_B … #define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_START_CNTL_G … #define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_START_CNTL_R … #define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_0_1 … #define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_2_3 … #define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_4_5 … #define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_6_7 … #define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_8_9 … #define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_10_11 … #define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_12_13 … #define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_14_15 … #define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM0_CM_RGAM_CONTROL … #define mmCM0_CM_RGAM_CONTROL_BASE_IDX … #define mmCM0_CM_RGAM_LUT_INDEX … #define mmCM0_CM_RGAM_LUT_INDEX_BASE_IDX … #define mmCM0_CM_RGAM_LUT_DATA … #define mmCM0_CM_RGAM_LUT_DATA_BASE_IDX … #define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK … #define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_START_CNTL_B … #define mmCM0_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_START_CNTL_G … #define mmCM0_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_START_CNTL_R … #define mmCM0_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B … #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G … #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R … #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_END_CNTL1_B … #define mmCM0_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_END_CNTL2_B … #define mmCM0_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_END_CNTL1_G … #define mmCM0_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_END_CNTL2_G … #define mmCM0_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_END_CNTL1_R … #define mmCM0_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_END_CNTL2_R … #define mmCM0_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_0_1 … #define mmCM0_CM_RGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_2_3 … #define mmCM0_CM_RGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_4_5 … #define mmCM0_CM_RGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_6_7 … #define mmCM0_CM_RGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_8_9 … #define mmCM0_CM_RGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_10_11 … #define mmCM0_CM_RGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_12_13 … #define mmCM0_CM_RGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_14_15 … #define mmCM0_CM_RGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_16_17 … #define mmCM0_CM_RGAM_RAMA_REGION_16_17_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_18_19 … #define mmCM0_CM_RGAM_RAMA_REGION_18_19_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_20_21 … #define mmCM0_CM_RGAM_RAMA_REGION_20_21_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_22_23 … #define mmCM0_CM_RGAM_RAMA_REGION_22_23_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_24_25 … #define mmCM0_CM_RGAM_RAMA_REGION_24_25_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_26_27 … #define mmCM0_CM_RGAM_RAMA_REGION_26_27_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_28_29 … #define mmCM0_CM_RGAM_RAMA_REGION_28_29_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_30_31 … #define mmCM0_CM_RGAM_RAMA_REGION_30_31_BASE_IDX … #define mmCM0_CM_RGAM_RAMA_REGION_32_33 … #define mmCM0_CM_RGAM_RAMA_REGION_32_33_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_START_CNTL_B … #define mmCM0_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_START_CNTL_G … #define mmCM0_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_START_CNTL_R … #define mmCM0_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B … #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G … #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R … #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_END_CNTL1_B … #define mmCM0_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_END_CNTL2_B … #define mmCM0_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_END_CNTL1_G … #define mmCM0_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_END_CNTL2_G … #define mmCM0_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_END_CNTL1_R … #define mmCM0_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_END_CNTL2_R … #define mmCM0_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_0_1 … #define mmCM0_CM_RGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_2_3 … #define mmCM0_CM_RGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_4_5 … #define mmCM0_CM_RGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_6_7 … #define mmCM0_CM_RGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_8_9 … #define mmCM0_CM_RGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_10_11 … #define mmCM0_CM_RGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_12_13 … #define mmCM0_CM_RGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_14_15 … #define mmCM0_CM_RGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_16_17 … #define mmCM0_CM_RGAM_RAMB_REGION_16_17_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_18_19 … #define mmCM0_CM_RGAM_RAMB_REGION_18_19_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_20_21 … #define mmCM0_CM_RGAM_RAMB_REGION_20_21_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_22_23 … #define mmCM0_CM_RGAM_RAMB_REGION_22_23_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_24_25 … #define mmCM0_CM_RGAM_RAMB_REGION_24_25_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_26_27 … #define mmCM0_CM_RGAM_RAMB_REGION_26_27_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_28_29 … #define mmCM0_CM_RGAM_RAMB_REGION_28_29_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_30_31 … #define mmCM0_CM_RGAM_RAMB_REGION_30_31_BASE_IDX … #define mmCM0_CM_RGAM_RAMB_REGION_32_33 … #define mmCM0_CM_RGAM_RAMB_REGION_32_33_BASE_IDX … #define mmCM0_CM_HDR_MULT_COEF … #define mmCM0_CM_HDR_MULT_COEF_BASE_IDX … #define mmCM0_CM_RANGE_CLAMP_CONTROL_R … #define mmCM0_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX … #define mmCM0_CM_RANGE_CLAMP_CONTROL_G … #define mmCM0_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX … #define mmCM0_CM_RANGE_CLAMP_CONTROL_B … #define mmCM0_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX … #define mmCM0_CM_DENORM_CONTROL … #define mmCM0_CM_DENORM_CONTROL_BASE_IDX … #define mmCM0_CM_CMOUT_CONTROL … #define mmCM0_CM_CMOUT_CONTROL_BASE_IDX … #define mmCM0_CM_CMOUT_RANDOM_SEEDS … #define mmCM0_CM_CMOUT_RANDOM_SEEDS_BASE_IDX … #define mmCM0_CM_MEM_PWR_CTRL … #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX … #define mmCM0_CM_MEM_PWR_STATUS … #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX … #define mmCM0_CM_TEST_DEBUG_INDEX … #define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX … #define mmCM0_CM_TEST_DEBUG_DATA … #define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec // base address: 0x3530 #define mmDC_PERFMON12_PERFCOUNTER_CNTL … #define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON12_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON12_PERFCOUNTER_STATE … #define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON12_PERFMON_CNTL … #define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON12_PERFMON_CNTL2 … #define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON12_PERFMON_CVALUE_LOW … #define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON12_PERFMON_HI … #define mmDC_PERFMON12_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON12_PERFMON_LOW … #define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec // base address: 0x46c #define mmDPP_TOP1_DPP_CONTROL … #define mmDPP_TOP1_DPP_CONTROL_BASE_IDX … #define mmDPP_TOP1_DPP_SOFT_RESET … #define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX … #define mmDPP_TOP1_DPP_CRC_VAL_R_G … #define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX … #define mmDPP_TOP1_DPP_CRC_VAL_B_A … #define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX … #define mmDPP_TOP1_DPP_CRC_CTRL … #define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX … #define mmDPP_TOP1_HOST_READ_CONTROL … #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX … // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec // base address: 0x46c #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT … #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define mmCNVC_CFG1_FORMAT_CONTROL … #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX … #define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS … #define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS_BASE_IDX … #define mmCNVC_CFG1_DENORM_CONTROL … #define mmCNVC_CFG1_DENORM_CONTROL_BASE_IDX … #define mmCNVC_CFG1_COLOR_KEYER_CONTROL … #define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX … #define mmCNVC_CFG1_COLOR_KEYER_ALPHA … #define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX … #define mmCNVC_CFG1_COLOR_KEYER_RED … #define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX … #define mmCNVC_CFG1_COLOR_KEYER_GREEN … #define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX … #define mmCNVC_CFG1_COLOR_KEYER_BLUE … #define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX … // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec // base address: 0x46c #define mmCNVC_CUR1_CURSOR0_CONTROL … #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX … #define mmCNVC_CUR1_CURSOR0_COLOR0 … #define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX … #define mmCNVC_CUR1_CURSOR0_COLOR1 … #define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX … #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS … #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX … // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec // base address: 0x46c #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT … #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define mmDSCL1_SCL_COEF_RAM_TAP_DATA … #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmDSCL1_SCL_MODE … #define mmDSCL1_SCL_MODE_BASE_IDX … #define mmDSCL1_SCL_TAP_CONTROL … #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX … #define mmDSCL1_DSCL_CONTROL … #define mmDSCL1_DSCL_CONTROL_BASE_IDX … #define mmDSCL1_DSCL_2TAP_CONTROL … #define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX … #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL … #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO … #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL1_SCL_HORZ_FILTER_INIT … #define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C … #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL1_SCL_HORZ_FILTER_INIT_C … #define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO … #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_INIT … #define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT … #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C … #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_INIT_C … #define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C … #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define mmDSCL1_SCL_BLACK_OFFSET … #define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX … #define mmDSCL1_DSCL_UPDATE … #define mmDSCL1_DSCL_UPDATE_BASE_IDX … #define mmDSCL1_DSCL_AUTOCAL … #define mmDSCL1_DSCL_AUTOCAL_BASE_IDX … #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmDSCL1_OTG_H_BLANK … #define mmDSCL1_OTG_H_BLANK_BASE_IDX … #define mmDSCL1_OTG_V_BLANK … #define mmDSCL1_OTG_V_BLANK_BASE_IDX … #define mmDSCL1_RECOUT_START … #define mmDSCL1_RECOUT_START_BASE_IDX … #define mmDSCL1_RECOUT_SIZE … #define mmDSCL1_RECOUT_SIZE_BASE_IDX … #define mmDSCL1_MPC_SIZE … #define mmDSCL1_MPC_SIZE_BASE_IDX … #define mmDSCL1_LB_DATA_FORMAT … #define mmDSCL1_LB_DATA_FORMAT_BASE_IDX … #define mmDSCL1_LB_MEMORY_CTRL … #define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX … #define mmDSCL1_LB_V_COUNTER … #define mmDSCL1_LB_V_COUNTER_BASE_IDX … #define mmDSCL1_DSCL_MEM_PWR_CTRL … #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX … #define mmDSCL1_DSCL_MEM_PWR_STATUS … #define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … #define mmDSCL1_OBUF_CONTROL … #define mmDSCL1_OBUF_CONTROL_BASE_IDX … #define mmDSCL1_OBUF_MEM_PWR_CTRL … #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec // base address: 0x46c #define mmCM1_CM_CONTROL … #define mmCM1_CM_CONTROL_BASE_IDX … #define mmCM1_CM_COMA_C11_C12 … #define mmCM1_CM_COMA_C11_C12_BASE_IDX … #define mmCM1_CM_COMA_C13_C14 … #define mmCM1_CM_COMA_C13_C14_BASE_IDX … #define mmCM1_CM_COMA_C21_C22 … #define mmCM1_CM_COMA_C21_C22_BASE_IDX … #define mmCM1_CM_COMA_C23_C24 … #define mmCM1_CM_COMA_C23_C24_BASE_IDX … #define mmCM1_CM_COMA_C31_C32 … #define mmCM1_CM_COMA_C31_C32_BASE_IDX … #define mmCM1_CM_COMA_C33_C34 … #define mmCM1_CM_COMA_C33_C34_BASE_IDX … #define mmCM1_CM_COMB_C11_C12 … #define mmCM1_CM_COMB_C11_C12_BASE_IDX … #define mmCM1_CM_COMB_C13_C14 … #define mmCM1_CM_COMB_C13_C14_BASE_IDX … #define mmCM1_CM_COMB_C21_C22 … #define mmCM1_CM_COMB_C21_C22_BASE_IDX … #define mmCM1_CM_COMB_C23_C24 … #define mmCM1_CM_COMB_C23_C24_BASE_IDX … #define mmCM1_CM_COMB_C31_C32 … #define mmCM1_CM_COMB_C31_C32_BASE_IDX … #define mmCM1_CM_COMB_C33_C34 … #define mmCM1_CM_COMB_C33_C34_BASE_IDX … #define mmCM1_CM_IGAM_CONTROL … #define mmCM1_CM_IGAM_CONTROL_BASE_IDX … #define mmCM1_CM_IGAM_LUT_RW_CONTROL … #define mmCM1_CM_IGAM_LUT_RW_CONTROL_BASE_IDX … #define mmCM1_CM_IGAM_LUT_RW_INDEX … #define mmCM1_CM_IGAM_LUT_RW_INDEX_BASE_IDX … #define mmCM1_CM_IGAM_LUT_SEQ_COLOR … #define mmCM1_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX … #define mmCM1_CM_IGAM_LUT_30_COLOR … #define mmCM1_CM_IGAM_LUT_30_COLOR_BASE_IDX … #define mmCM1_CM_IGAM_LUT_PWL_DATA … #define mmCM1_CM_IGAM_LUT_PWL_DATA_BASE_IDX … #define mmCM1_CM_IGAM_LUT_AUTOFILL … #define mmCM1_CM_IGAM_LUT_AUTOFILL_BASE_IDX … #define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE … #define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX … #define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN … #define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX … #define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED … #define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX … #define mmCM1_CM_ICSC_CONTROL … #define mmCM1_CM_ICSC_CONTROL_BASE_IDX … #define mmCM1_CM_ICSC_C11_C12 … #define mmCM1_CM_ICSC_C11_C12_BASE_IDX … #define mmCM1_CM_ICSC_C13_C14 … #define mmCM1_CM_ICSC_C13_C14_BASE_IDX … #define mmCM1_CM_ICSC_C21_C22 … #define mmCM1_CM_ICSC_C21_C22_BASE_IDX … #define mmCM1_CM_ICSC_C23_C24 … #define mmCM1_CM_ICSC_C23_C24_BASE_IDX … #define mmCM1_CM_ICSC_C31_C32 … #define mmCM1_CM_ICSC_C31_C32_BASE_IDX … #define mmCM1_CM_ICSC_C33_C34 … #define mmCM1_CM_ICSC_C33_C34_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_CONTROL … #define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C11_C12 … #define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C13_C14 … #define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C21_C22 … #define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C23_C24 … #define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C31_C32 … #define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C33_C34 … #define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmCM1_CM_OCSC_CONTROL … #define mmCM1_CM_OCSC_CONTROL_BASE_IDX … #define mmCM1_CM_OCSC_C11_C12 … #define mmCM1_CM_OCSC_C11_C12_BASE_IDX … #define mmCM1_CM_OCSC_C13_C14 … #define mmCM1_CM_OCSC_C13_C14_BASE_IDX … #define mmCM1_CM_OCSC_C21_C22 … #define mmCM1_CM_OCSC_C21_C22_BASE_IDX … #define mmCM1_CM_OCSC_C23_C24 … #define mmCM1_CM_OCSC_C23_C24_BASE_IDX … #define mmCM1_CM_OCSC_C31_C32 … #define mmCM1_CM_OCSC_C31_C32_BASE_IDX … #define mmCM1_CM_OCSC_C33_C34 … #define mmCM1_CM_OCSC_C33_C34_BASE_IDX … #define mmCM1_CM_BNS_VALUES_R … #define mmCM1_CM_BNS_VALUES_R_BASE_IDX … #define mmCM1_CM_BNS_VALUES_G … #define mmCM1_CM_BNS_VALUES_G_BASE_IDX … #define mmCM1_CM_BNS_VALUES_B … #define mmCM1_CM_BNS_VALUES_B_BASE_IDX … #define mmCM1_CM_DGAM_CONTROL … #define mmCM1_CM_DGAM_CONTROL_BASE_IDX … #define mmCM1_CM_DGAM_LUT_INDEX … #define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX … #define mmCM1_CM_DGAM_LUT_DATA … #define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX … #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK … #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_START_CNTL_B … #define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_START_CNTL_G … #define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_START_CNTL_R … #define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_0_1 … #define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_2_3 … #define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_4_5 … #define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_6_7 … #define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_8_9 … #define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_10_11 … #define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_12_13 … #define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_14_15 … #define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_START_CNTL_B … #define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_START_CNTL_G … #define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_START_CNTL_R … #define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_0_1 … #define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_2_3 … #define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_4_5 … #define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_6_7 … #define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_8_9 … #define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_10_11 … #define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_12_13 … #define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_14_15 … #define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM1_CM_RGAM_CONTROL … #define mmCM1_CM_RGAM_CONTROL_BASE_IDX … #define mmCM1_CM_RGAM_LUT_INDEX … #define mmCM1_CM_RGAM_LUT_INDEX_BASE_IDX … #define mmCM1_CM_RGAM_LUT_DATA … #define mmCM1_CM_RGAM_LUT_DATA_BASE_IDX … #define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK … #define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_START_CNTL_B … #define mmCM1_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_START_CNTL_G … #define mmCM1_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_START_CNTL_R … #define mmCM1_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B … #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G … #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R … #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_END_CNTL1_B … #define mmCM1_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_END_CNTL2_B … #define mmCM1_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_END_CNTL1_G … #define mmCM1_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_END_CNTL2_G … #define mmCM1_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_END_CNTL1_R … #define mmCM1_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_END_CNTL2_R … #define mmCM1_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_0_1 … #define mmCM1_CM_RGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_2_3 … #define mmCM1_CM_RGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_4_5 … #define mmCM1_CM_RGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_6_7 … #define mmCM1_CM_RGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_8_9 … #define mmCM1_CM_RGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_10_11 … #define mmCM1_CM_RGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_12_13 … #define mmCM1_CM_RGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_14_15 … #define mmCM1_CM_RGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_16_17 … #define mmCM1_CM_RGAM_RAMA_REGION_16_17_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_18_19 … #define mmCM1_CM_RGAM_RAMA_REGION_18_19_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_20_21 … #define mmCM1_CM_RGAM_RAMA_REGION_20_21_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_22_23 … #define mmCM1_CM_RGAM_RAMA_REGION_22_23_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_24_25 … #define mmCM1_CM_RGAM_RAMA_REGION_24_25_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_26_27 … #define mmCM1_CM_RGAM_RAMA_REGION_26_27_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_28_29 … #define mmCM1_CM_RGAM_RAMA_REGION_28_29_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_30_31 … #define mmCM1_CM_RGAM_RAMA_REGION_30_31_BASE_IDX … #define mmCM1_CM_RGAM_RAMA_REGION_32_33 … #define mmCM1_CM_RGAM_RAMA_REGION_32_33_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_START_CNTL_B … #define mmCM1_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_START_CNTL_G … #define mmCM1_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_START_CNTL_R … #define mmCM1_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B … #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G … #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R … #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_END_CNTL1_B … #define mmCM1_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_END_CNTL2_B … #define mmCM1_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_END_CNTL1_G … #define mmCM1_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_END_CNTL2_G … #define mmCM1_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_END_CNTL1_R … #define mmCM1_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_END_CNTL2_R … #define mmCM1_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_0_1 … #define mmCM1_CM_RGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_2_3 … #define mmCM1_CM_RGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_4_5 … #define mmCM1_CM_RGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_6_7 … #define mmCM1_CM_RGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_8_9 … #define mmCM1_CM_RGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_10_11 … #define mmCM1_CM_RGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_12_13 … #define mmCM1_CM_RGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_14_15 … #define mmCM1_CM_RGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_16_17 … #define mmCM1_CM_RGAM_RAMB_REGION_16_17_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_18_19 … #define mmCM1_CM_RGAM_RAMB_REGION_18_19_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_20_21 … #define mmCM1_CM_RGAM_RAMB_REGION_20_21_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_22_23 … #define mmCM1_CM_RGAM_RAMB_REGION_22_23_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_24_25 … #define mmCM1_CM_RGAM_RAMB_REGION_24_25_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_26_27 … #define mmCM1_CM_RGAM_RAMB_REGION_26_27_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_28_29 … #define mmCM1_CM_RGAM_RAMB_REGION_28_29_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_30_31 … #define mmCM1_CM_RGAM_RAMB_REGION_30_31_BASE_IDX … #define mmCM1_CM_RGAM_RAMB_REGION_32_33 … #define mmCM1_CM_RGAM_RAMB_REGION_32_33_BASE_IDX … #define mmCM1_CM_HDR_MULT_COEF … #define mmCM1_CM_HDR_MULT_COEF_BASE_IDX … #define mmCM1_CM_RANGE_CLAMP_CONTROL_R … #define mmCM1_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX … #define mmCM1_CM_RANGE_CLAMP_CONTROL_G … #define mmCM1_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX … #define mmCM1_CM_RANGE_CLAMP_CONTROL_B … #define mmCM1_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX … #define mmCM1_CM_DENORM_CONTROL … #define mmCM1_CM_DENORM_CONTROL_BASE_IDX … #define mmCM1_CM_CMOUT_CONTROL … #define mmCM1_CM_CMOUT_CONTROL_BASE_IDX … #define mmCM1_CM_CMOUT_RANDOM_SEEDS … #define mmCM1_CM_CMOUT_RANDOM_SEEDS_BASE_IDX … #define mmCM1_CM_MEM_PWR_CTRL … #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX … #define mmCM1_CM_MEM_PWR_STATUS … #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX … #define mmCM1_CM_TEST_DEBUG_INDEX … #define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX … #define mmCM1_CM_TEST_DEBUG_DATA … #define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec // base address: 0x399c #define mmDC_PERFMON13_PERFCOUNTER_CNTL … #define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON13_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON13_PERFCOUNTER_STATE … #define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON13_PERFMON_CNTL … #define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON13_PERFMON_CNTL2 … #define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON13_PERFMON_CVALUE_LOW … #define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON13_PERFMON_HI … #define mmDC_PERFMON13_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON13_PERFMON_LOW … #define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec // base address: 0x8d8 #define mmDPP_TOP2_DPP_CONTROL … #define mmDPP_TOP2_DPP_CONTROL_BASE_IDX … #define mmDPP_TOP2_DPP_SOFT_RESET … #define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX … #define mmDPP_TOP2_DPP_CRC_VAL_R_G … #define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX … #define mmDPP_TOP2_DPP_CRC_VAL_B_A … #define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX … #define mmDPP_TOP2_DPP_CRC_CTRL … #define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX … #define mmDPP_TOP2_HOST_READ_CONTROL … #define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX … // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec // base address: 0x8d8 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT … #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define mmCNVC_CFG2_FORMAT_CONTROL … #define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX … #define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS … #define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS_BASE_IDX … #define mmCNVC_CFG2_DENORM_CONTROL … #define mmCNVC_CFG2_DENORM_CONTROL_BASE_IDX … #define mmCNVC_CFG2_COLOR_KEYER_CONTROL … #define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX … #define mmCNVC_CFG2_COLOR_KEYER_ALPHA … #define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX … #define mmCNVC_CFG2_COLOR_KEYER_RED … #define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX … #define mmCNVC_CFG2_COLOR_KEYER_GREEN … #define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX … #define mmCNVC_CFG2_COLOR_KEYER_BLUE … #define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX … // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec // base address: 0x8d8 #define mmCNVC_CUR2_CURSOR0_CONTROL … #define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX … #define mmCNVC_CUR2_CURSOR0_COLOR0 … #define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX … #define mmCNVC_CUR2_CURSOR0_COLOR1 … #define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX … #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS … #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX … // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec // base address: 0x8d8 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT … #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define mmDSCL2_SCL_COEF_RAM_TAP_DATA … #define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmDSCL2_SCL_MODE … #define mmDSCL2_SCL_MODE_BASE_IDX … #define mmDSCL2_SCL_TAP_CONTROL … #define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX … #define mmDSCL2_DSCL_CONTROL … #define mmDSCL2_DSCL_CONTROL_BASE_IDX … #define mmDSCL2_DSCL_2TAP_CONTROL … #define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX … #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL … #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO … #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL2_SCL_HORZ_FILTER_INIT … #define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C … #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL2_SCL_HORZ_FILTER_INIT_C … #define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO … #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_INIT … #define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT … #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C … #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_INIT_C … #define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C … #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define mmDSCL2_SCL_BLACK_OFFSET … #define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX … #define mmDSCL2_DSCL_UPDATE … #define mmDSCL2_DSCL_UPDATE_BASE_IDX … #define mmDSCL2_DSCL_AUTOCAL … #define mmDSCL2_DSCL_AUTOCAL_BASE_IDX … #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmDSCL2_OTG_H_BLANK … #define mmDSCL2_OTG_H_BLANK_BASE_IDX … #define mmDSCL2_OTG_V_BLANK … #define mmDSCL2_OTG_V_BLANK_BASE_IDX … #define mmDSCL2_RECOUT_START … #define mmDSCL2_RECOUT_START_BASE_IDX … #define mmDSCL2_RECOUT_SIZE … #define mmDSCL2_RECOUT_SIZE_BASE_IDX … #define mmDSCL2_MPC_SIZE … #define mmDSCL2_MPC_SIZE_BASE_IDX … #define mmDSCL2_LB_DATA_FORMAT … #define mmDSCL2_LB_DATA_FORMAT_BASE_IDX … #define mmDSCL2_LB_MEMORY_CTRL … #define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX … #define mmDSCL2_LB_V_COUNTER … #define mmDSCL2_LB_V_COUNTER_BASE_IDX … #define mmDSCL2_DSCL_MEM_PWR_CTRL … #define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … #define mmDSCL2_DSCL_MEM_PWR_STATUS … #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX … #define mmDSCL2_OBUF_CONTROL … #define mmDSCL2_OBUF_CONTROL_BASE_IDX … #define mmDSCL2_OBUF_MEM_PWR_CTRL … #define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec // base address: 0x8d8 #define mmCM2_CM_CONTROL … #define mmCM2_CM_CONTROL_BASE_IDX … #define mmCM2_CM_COMA_C11_C12 … #define mmCM2_CM_COMA_C11_C12_BASE_IDX … #define mmCM2_CM_COMA_C13_C14 … #define mmCM2_CM_COMA_C13_C14_BASE_IDX … #define mmCM2_CM_COMA_C21_C22 … #define mmCM2_CM_COMA_C21_C22_BASE_IDX … #define mmCM2_CM_COMA_C23_C24 … #define mmCM2_CM_COMA_C23_C24_BASE_IDX … #define mmCM2_CM_COMA_C31_C32 … #define mmCM2_CM_COMA_C31_C32_BASE_IDX … #define mmCM2_CM_COMA_C33_C34 … #define mmCM2_CM_COMA_C33_C34_BASE_IDX … #define mmCM2_CM_COMB_C11_C12 … #define mmCM2_CM_COMB_C11_C12_BASE_IDX … #define mmCM2_CM_COMB_C13_C14 … #define mmCM2_CM_COMB_C13_C14_BASE_IDX … #define mmCM2_CM_COMB_C21_C22 … #define mmCM2_CM_COMB_C21_C22_BASE_IDX … #define mmCM2_CM_COMB_C23_C24 … #define mmCM2_CM_COMB_C23_C24_BASE_IDX … #define mmCM2_CM_COMB_C31_C32 … #define mmCM2_CM_COMB_C31_C32_BASE_IDX … #define mmCM2_CM_COMB_C33_C34 … #define mmCM2_CM_COMB_C33_C34_BASE_IDX … #define mmCM2_CM_IGAM_CONTROL … #define mmCM2_CM_IGAM_CONTROL_BASE_IDX … #define mmCM2_CM_IGAM_LUT_RW_CONTROL … #define mmCM2_CM_IGAM_LUT_RW_CONTROL_BASE_IDX … #define mmCM2_CM_IGAM_LUT_RW_INDEX … #define mmCM2_CM_IGAM_LUT_RW_INDEX_BASE_IDX … #define mmCM2_CM_IGAM_LUT_SEQ_COLOR … #define mmCM2_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX … #define mmCM2_CM_IGAM_LUT_30_COLOR … #define mmCM2_CM_IGAM_LUT_30_COLOR_BASE_IDX … #define mmCM2_CM_IGAM_LUT_PWL_DATA … #define mmCM2_CM_IGAM_LUT_PWL_DATA_BASE_IDX … #define mmCM2_CM_IGAM_LUT_AUTOFILL … #define mmCM2_CM_IGAM_LUT_AUTOFILL_BASE_IDX … #define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE … #define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX … #define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN … #define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX … #define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED … #define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX … #define mmCM2_CM_ICSC_CONTROL … #define mmCM2_CM_ICSC_CONTROL_BASE_IDX … #define mmCM2_CM_ICSC_C11_C12 … #define mmCM2_CM_ICSC_C11_C12_BASE_IDX … #define mmCM2_CM_ICSC_C13_C14 … #define mmCM2_CM_ICSC_C13_C14_BASE_IDX … #define mmCM2_CM_ICSC_C21_C22 … #define mmCM2_CM_ICSC_C21_C22_BASE_IDX … #define mmCM2_CM_ICSC_C23_C24 … #define mmCM2_CM_ICSC_C23_C24_BASE_IDX … #define mmCM2_CM_ICSC_C31_C32 … #define mmCM2_CM_ICSC_C31_C32_BASE_IDX … #define mmCM2_CM_ICSC_C33_C34 … #define mmCM2_CM_ICSC_C33_C34_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_CONTROL … #define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C11_C12 … #define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C13_C14 … #define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C21_C22 … #define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C23_C24 … #define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C31_C32 … #define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C33_C34 … #define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmCM2_CM_OCSC_CONTROL … #define mmCM2_CM_OCSC_CONTROL_BASE_IDX … #define mmCM2_CM_OCSC_C11_C12 … #define mmCM2_CM_OCSC_C11_C12_BASE_IDX … #define mmCM2_CM_OCSC_C13_C14 … #define mmCM2_CM_OCSC_C13_C14_BASE_IDX … #define mmCM2_CM_OCSC_C21_C22 … #define mmCM2_CM_OCSC_C21_C22_BASE_IDX … #define mmCM2_CM_OCSC_C23_C24 … #define mmCM2_CM_OCSC_C23_C24_BASE_IDX … #define mmCM2_CM_OCSC_C31_C32 … #define mmCM2_CM_OCSC_C31_C32_BASE_IDX … #define mmCM2_CM_OCSC_C33_C34 … #define mmCM2_CM_OCSC_C33_C34_BASE_IDX … #define mmCM2_CM_BNS_VALUES_R … #define mmCM2_CM_BNS_VALUES_R_BASE_IDX … #define mmCM2_CM_BNS_VALUES_G … #define mmCM2_CM_BNS_VALUES_G_BASE_IDX … #define mmCM2_CM_BNS_VALUES_B … #define mmCM2_CM_BNS_VALUES_B_BASE_IDX … #define mmCM2_CM_DGAM_CONTROL … #define mmCM2_CM_DGAM_CONTROL_BASE_IDX … #define mmCM2_CM_DGAM_LUT_INDEX … #define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX … #define mmCM2_CM_DGAM_LUT_DATA … #define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX … #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK … #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_START_CNTL_B … #define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_START_CNTL_G … #define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_START_CNTL_R … #define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_0_1 … #define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_2_3 … #define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_4_5 … #define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_6_7 … #define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_8_9 … #define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_10_11 … #define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_12_13 … #define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_14_15 … #define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_START_CNTL_B … #define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_START_CNTL_G … #define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_START_CNTL_R … #define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_0_1 … #define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_2_3 … #define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_4_5 … #define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_6_7 … #define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_8_9 … #define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_10_11 … #define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_12_13 … #define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_14_15 … #define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM2_CM_RGAM_CONTROL … #define mmCM2_CM_RGAM_CONTROL_BASE_IDX … #define mmCM2_CM_RGAM_LUT_INDEX … #define mmCM2_CM_RGAM_LUT_INDEX_BASE_IDX … #define mmCM2_CM_RGAM_LUT_DATA … #define mmCM2_CM_RGAM_LUT_DATA_BASE_IDX … #define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK … #define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_START_CNTL_B … #define mmCM2_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_START_CNTL_G … #define mmCM2_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_START_CNTL_R … #define mmCM2_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B … #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G … #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R … #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_END_CNTL1_B … #define mmCM2_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_END_CNTL2_B … #define mmCM2_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_END_CNTL1_G … #define mmCM2_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_END_CNTL2_G … #define mmCM2_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_END_CNTL1_R … #define mmCM2_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_END_CNTL2_R … #define mmCM2_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_0_1 … #define mmCM2_CM_RGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_2_3 … #define mmCM2_CM_RGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_4_5 … #define mmCM2_CM_RGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_6_7 … #define mmCM2_CM_RGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_8_9 … #define mmCM2_CM_RGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_10_11 … #define mmCM2_CM_RGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_12_13 … #define mmCM2_CM_RGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_14_15 … #define mmCM2_CM_RGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_16_17 … #define mmCM2_CM_RGAM_RAMA_REGION_16_17_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_18_19 … #define mmCM2_CM_RGAM_RAMA_REGION_18_19_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_20_21 … #define mmCM2_CM_RGAM_RAMA_REGION_20_21_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_22_23 … #define mmCM2_CM_RGAM_RAMA_REGION_22_23_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_24_25 … #define mmCM2_CM_RGAM_RAMA_REGION_24_25_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_26_27 … #define mmCM2_CM_RGAM_RAMA_REGION_26_27_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_28_29 … #define mmCM2_CM_RGAM_RAMA_REGION_28_29_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_30_31 … #define mmCM2_CM_RGAM_RAMA_REGION_30_31_BASE_IDX … #define mmCM2_CM_RGAM_RAMA_REGION_32_33 … #define mmCM2_CM_RGAM_RAMA_REGION_32_33_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_START_CNTL_B … #define mmCM2_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_START_CNTL_G … #define mmCM2_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_START_CNTL_R … #define mmCM2_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B … #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G … #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R … #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_END_CNTL1_B … #define mmCM2_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_END_CNTL2_B … #define mmCM2_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_END_CNTL1_G … #define mmCM2_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_END_CNTL2_G … #define mmCM2_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_END_CNTL1_R … #define mmCM2_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_END_CNTL2_R … #define mmCM2_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_0_1 … #define mmCM2_CM_RGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_2_3 … #define mmCM2_CM_RGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_4_5 … #define mmCM2_CM_RGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_6_7 … #define mmCM2_CM_RGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_8_9 … #define mmCM2_CM_RGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_10_11 … #define mmCM2_CM_RGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_12_13 … #define mmCM2_CM_RGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_14_15 … #define mmCM2_CM_RGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_16_17 … #define mmCM2_CM_RGAM_RAMB_REGION_16_17_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_18_19 … #define mmCM2_CM_RGAM_RAMB_REGION_18_19_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_20_21 … #define mmCM2_CM_RGAM_RAMB_REGION_20_21_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_22_23 … #define mmCM2_CM_RGAM_RAMB_REGION_22_23_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_24_25 … #define mmCM2_CM_RGAM_RAMB_REGION_24_25_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_26_27 … #define mmCM2_CM_RGAM_RAMB_REGION_26_27_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_28_29 … #define mmCM2_CM_RGAM_RAMB_REGION_28_29_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_30_31 … #define mmCM2_CM_RGAM_RAMB_REGION_30_31_BASE_IDX … #define mmCM2_CM_RGAM_RAMB_REGION_32_33 … #define mmCM2_CM_RGAM_RAMB_REGION_32_33_BASE_IDX … #define mmCM2_CM_HDR_MULT_COEF … #define mmCM2_CM_HDR_MULT_COEF_BASE_IDX … #define mmCM2_CM_RANGE_CLAMP_CONTROL_R … #define mmCM2_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX … #define mmCM2_CM_RANGE_CLAMP_CONTROL_G … #define mmCM2_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX … #define mmCM2_CM_RANGE_CLAMP_CONTROL_B … #define mmCM2_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX … #define mmCM2_CM_DENORM_CONTROL … #define mmCM2_CM_DENORM_CONTROL_BASE_IDX … #define mmCM2_CM_CMOUT_CONTROL … #define mmCM2_CM_CMOUT_CONTROL_BASE_IDX … #define mmCM2_CM_CMOUT_RANDOM_SEEDS … #define mmCM2_CM_CMOUT_RANDOM_SEEDS_BASE_IDX … #define mmCM2_CM_MEM_PWR_CTRL … #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX … #define mmCM2_CM_MEM_PWR_STATUS … #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX … #define mmCM2_CM_TEST_DEBUG_INDEX … #define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX … #define mmCM2_CM_TEST_DEBUG_DATA … #define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec // base address: 0x3e08 #define mmDC_PERFMON14_PERFCOUNTER_CNTL … #define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON14_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON14_PERFCOUNTER_STATE … #define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON14_PERFMON_CNTL … #define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON14_PERFMON_CNTL2 … #define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON14_PERFMON_CVALUE_LOW … #define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON14_PERFMON_HI … #define mmDC_PERFMON14_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON14_PERFMON_LOW … #define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec // base address: 0xd44 #define mmDPP_TOP3_DPP_CONTROL … #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX … #define mmDPP_TOP3_DPP_SOFT_RESET … #define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX … #define mmDPP_TOP3_DPP_CRC_VAL_R_G … #define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX … #define mmDPP_TOP3_DPP_CRC_VAL_B_A … #define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX … #define mmDPP_TOP3_DPP_CRC_CTRL … #define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX … #define mmDPP_TOP3_HOST_READ_CONTROL … #define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX … // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec // base address: 0xd44 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT … #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define mmCNVC_CFG3_FORMAT_CONTROL … #define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX … #define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS … #define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS_BASE_IDX … #define mmCNVC_CFG3_DENORM_CONTROL … #define mmCNVC_CFG3_DENORM_CONTROL_BASE_IDX … #define mmCNVC_CFG3_COLOR_KEYER_CONTROL … #define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX … #define mmCNVC_CFG3_COLOR_KEYER_ALPHA … #define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX … #define mmCNVC_CFG3_COLOR_KEYER_RED … #define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX … #define mmCNVC_CFG3_COLOR_KEYER_GREEN … #define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX … #define mmCNVC_CFG3_COLOR_KEYER_BLUE … #define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX … // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec // base address: 0xd44 #define mmCNVC_CUR3_CURSOR0_CONTROL … #define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX … #define mmCNVC_CUR3_CURSOR0_COLOR0 … #define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX … #define mmCNVC_CUR3_CURSOR0_COLOR1 … #define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX … #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS … #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX … // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec // base address: 0xd44 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT … #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define mmDSCL3_SCL_COEF_RAM_TAP_DATA … #define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmDSCL3_SCL_MODE … #define mmDSCL3_SCL_MODE_BASE_IDX … #define mmDSCL3_SCL_TAP_CONTROL … #define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX … #define mmDSCL3_DSCL_CONTROL … #define mmDSCL3_DSCL_CONTROL_BASE_IDX … #define mmDSCL3_DSCL_2TAP_CONTROL … #define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX … #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL … #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO … #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL3_SCL_HORZ_FILTER_INIT … #define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C … #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL3_SCL_HORZ_FILTER_INIT_C … #define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO … #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_INIT … #define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT … #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C … #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_INIT_C … #define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C … #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define mmDSCL3_SCL_BLACK_OFFSET … #define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX … #define mmDSCL3_DSCL_UPDATE … #define mmDSCL3_DSCL_UPDATE_BASE_IDX … #define mmDSCL3_DSCL_AUTOCAL … #define mmDSCL3_DSCL_AUTOCAL_BASE_IDX … #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmDSCL3_OTG_H_BLANK … #define mmDSCL3_OTG_H_BLANK_BASE_IDX … #define mmDSCL3_OTG_V_BLANK … #define mmDSCL3_OTG_V_BLANK_BASE_IDX … #define mmDSCL3_RECOUT_START … #define mmDSCL3_RECOUT_START_BASE_IDX … #define mmDSCL3_RECOUT_SIZE … #define mmDSCL3_RECOUT_SIZE_BASE_IDX … #define mmDSCL3_MPC_SIZE … #define mmDSCL3_MPC_SIZE_BASE_IDX … #define mmDSCL3_LB_DATA_FORMAT … #define mmDSCL3_LB_DATA_FORMAT_BASE_IDX … #define mmDSCL3_LB_MEMORY_CTRL … #define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX … #define mmDSCL3_LB_V_COUNTER … #define mmDSCL3_LB_V_COUNTER_BASE_IDX … #define mmDSCL3_DSCL_MEM_PWR_CTRL … #define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX … #define mmDSCL3_DSCL_MEM_PWR_STATUS … #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX … #define mmDSCL3_OBUF_CONTROL … #define mmDSCL3_OBUF_CONTROL_BASE_IDX … #define mmDSCL3_OBUF_MEM_PWR_CTRL … #define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec // base address: 0xd44 #define mmCM3_CM_CONTROL … #define mmCM3_CM_CONTROL_BASE_IDX … #define mmCM3_CM_COMA_C11_C12 … #define mmCM3_CM_COMA_C11_C12_BASE_IDX … #define mmCM3_CM_COMA_C13_C14 … #define mmCM3_CM_COMA_C13_C14_BASE_IDX … #define mmCM3_CM_COMA_C21_C22 … #define mmCM3_CM_COMA_C21_C22_BASE_IDX … #define mmCM3_CM_COMA_C23_C24 … #define mmCM3_CM_COMA_C23_C24_BASE_IDX … #define mmCM3_CM_COMA_C31_C32 … #define mmCM3_CM_COMA_C31_C32_BASE_IDX … #define mmCM3_CM_COMA_C33_C34 … #define mmCM3_CM_COMA_C33_C34_BASE_IDX … #define mmCM3_CM_COMB_C11_C12 … #define mmCM3_CM_COMB_C11_C12_BASE_IDX … #define mmCM3_CM_COMB_C13_C14 … #define mmCM3_CM_COMB_C13_C14_BASE_IDX … #define mmCM3_CM_COMB_C21_C22 … #define mmCM3_CM_COMB_C21_C22_BASE_IDX … #define mmCM3_CM_COMB_C23_C24 … #define mmCM3_CM_COMB_C23_C24_BASE_IDX … #define mmCM3_CM_COMB_C31_C32 … #define mmCM3_CM_COMB_C31_C32_BASE_IDX … #define mmCM3_CM_COMB_C33_C34 … #define mmCM3_CM_COMB_C33_C34_BASE_IDX … #define mmCM3_CM_IGAM_CONTROL … #define mmCM3_CM_IGAM_CONTROL_BASE_IDX … #define mmCM3_CM_IGAM_LUT_RW_CONTROL … #define mmCM3_CM_IGAM_LUT_RW_CONTROL_BASE_IDX … #define mmCM3_CM_IGAM_LUT_RW_INDEX … #define mmCM3_CM_IGAM_LUT_RW_INDEX_BASE_IDX … #define mmCM3_CM_IGAM_LUT_SEQ_COLOR … #define mmCM3_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX … #define mmCM3_CM_IGAM_LUT_30_COLOR … #define mmCM3_CM_IGAM_LUT_30_COLOR_BASE_IDX … #define mmCM3_CM_IGAM_LUT_PWL_DATA … #define mmCM3_CM_IGAM_LUT_PWL_DATA_BASE_IDX … #define mmCM3_CM_IGAM_LUT_AUTOFILL … #define mmCM3_CM_IGAM_LUT_AUTOFILL_BASE_IDX … #define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE … #define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX … #define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN … #define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX … #define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED … #define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX … #define mmCM3_CM_ICSC_CONTROL … #define mmCM3_CM_ICSC_CONTROL_BASE_IDX … #define mmCM3_CM_ICSC_C11_C12 … #define mmCM3_CM_ICSC_C11_C12_BASE_IDX … #define mmCM3_CM_ICSC_C13_C14 … #define mmCM3_CM_ICSC_C13_C14_BASE_IDX … #define mmCM3_CM_ICSC_C21_C22 … #define mmCM3_CM_ICSC_C21_C22_BASE_IDX … #define mmCM3_CM_ICSC_C23_C24 … #define mmCM3_CM_ICSC_C23_C24_BASE_IDX … #define mmCM3_CM_ICSC_C31_C32 … #define mmCM3_CM_ICSC_C31_C32_BASE_IDX … #define mmCM3_CM_ICSC_C33_C34 … #define mmCM3_CM_ICSC_C33_C34_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_CONTROL … #define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C11_C12 … #define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C13_C14 … #define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C21_C22 … #define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C23_C24 … #define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C31_C32 … #define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C33_C34 … #define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmCM3_CM_OCSC_CONTROL … #define mmCM3_CM_OCSC_CONTROL_BASE_IDX … #define mmCM3_CM_OCSC_C11_C12 … #define mmCM3_CM_OCSC_C11_C12_BASE_IDX … #define mmCM3_CM_OCSC_C13_C14 … #define mmCM3_CM_OCSC_C13_C14_BASE_IDX … #define mmCM3_CM_OCSC_C21_C22 … #define mmCM3_CM_OCSC_C21_C22_BASE_IDX … #define mmCM3_CM_OCSC_C23_C24 … #define mmCM3_CM_OCSC_C23_C24_BASE_IDX … #define mmCM3_CM_OCSC_C31_C32 … #define mmCM3_CM_OCSC_C31_C32_BASE_IDX … #define mmCM3_CM_OCSC_C33_C34 … #define mmCM3_CM_OCSC_C33_C34_BASE_IDX … #define mmCM3_CM_BNS_VALUES_R … #define mmCM3_CM_BNS_VALUES_R_BASE_IDX … #define mmCM3_CM_BNS_VALUES_G … #define mmCM3_CM_BNS_VALUES_G_BASE_IDX … #define mmCM3_CM_BNS_VALUES_B … #define mmCM3_CM_BNS_VALUES_B_BASE_IDX … #define mmCM3_CM_DGAM_CONTROL … #define mmCM3_CM_DGAM_CONTROL_BASE_IDX … #define mmCM3_CM_DGAM_LUT_INDEX … #define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX … #define mmCM3_CM_DGAM_LUT_DATA … #define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX … #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK … #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_START_CNTL_B … #define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_START_CNTL_G … #define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_START_CNTL_R … #define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_0_1 … #define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_2_3 … #define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_4_5 … #define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_6_7 … #define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_8_9 … #define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_10_11 … #define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_12_13 … #define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_14_15 … #define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_START_CNTL_B … #define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_START_CNTL_G … #define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_START_CNTL_R … #define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_0_1 … #define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_2_3 … #define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_4_5 … #define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_6_7 … #define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_8_9 … #define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_10_11 … #define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_12_13 … #define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_14_15 … #define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM3_CM_RGAM_CONTROL … #define mmCM3_CM_RGAM_CONTROL_BASE_IDX … #define mmCM3_CM_RGAM_LUT_INDEX … #define mmCM3_CM_RGAM_LUT_INDEX_BASE_IDX … #define mmCM3_CM_RGAM_LUT_DATA … #define mmCM3_CM_RGAM_LUT_DATA_BASE_IDX … #define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK … #define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_START_CNTL_B … #define mmCM3_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_START_CNTL_G … #define mmCM3_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_START_CNTL_R … #define mmCM3_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B … #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G … #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R … #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_END_CNTL1_B … #define mmCM3_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_END_CNTL2_B … #define mmCM3_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_END_CNTL1_G … #define mmCM3_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_END_CNTL2_G … #define mmCM3_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_END_CNTL1_R … #define mmCM3_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_END_CNTL2_R … #define mmCM3_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_0_1 … #define mmCM3_CM_RGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_2_3 … #define mmCM3_CM_RGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_4_5 … #define mmCM3_CM_RGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_6_7 … #define mmCM3_CM_RGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_8_9 … #define mmCM3_CM_RGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_10_11 … #define mmCM3_CM_RGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_12_13 … #define mmCM3_CM_RGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_14_15 … #define mmCM3_CM_RGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_16_17 … #define mmCM3_CM_RGAM_RAMA_REGION_16_17_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_18_19 … #define mmCM3_CM_RGAM_RAMA_REGION_18_19_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_20_21 … #define mmCM3_CM_RGAM_RAMA_REGION_20_21_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_22_23 … #define mmCM3_CM_RGAM_RAMA_REGION_22_23_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_24_25 … #define mmCM3_CM_RGAM_RAMA_REGION_24_25_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_26_27 … #define mmCM3_CM_RGAM_RAMA_REGION_26_27_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_28_29 … #define mmCM3_CM_RGAM_RAMA_REGION_28_29_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_30_31 … #define mmCM3_CM_RGAM_RAMA_REGION_30_31_BASE_IDX … #define mmCM3_CM_RGAM_RAMA_REGION_32_33 … #define mmCM3_CM_RGAM_RAMA_REGION_32_33_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_START_CNTL_B … #define mmCM3_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_START_CNTL_G … #define mmCM3_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_START_CNTL_R … #define mmCM3_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B … #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G … #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R … #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_END_CNTL1_B … #define mmCM3_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_END_CNTL2_B … #define mmCM3_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_END_CNTL1_G … #define mmCM3_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_END_CNTL2_G … #define mmCM3_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_END_CNTL1_R … #define mmCM3_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_END_CNTL2_R … #define mmCM3_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_0_1 … #define mmCM3_CM_RGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_2_3 … #define mmCM3_CM_RGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_4_5 … #define mmCM3_CM_RGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_6_7 … #define mmCM3_CM_RGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_8_9 … #define mmCM3_CM_RGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_10_11 … #define mmCM3_CM_RGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_12_13 … #define mmCM3_CM_RGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_14_15 … #define mmCM3_CM_RGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_16_17 … #define mmCM3_CM_RGAM_RAMB_REGION_16_17_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_18_19 … #define mmCM3_CM_RGAM_RAMB_REGION_18_19_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_20_21 … #define mmCM3_CM_RGAM_RAMB_REGION_20_21_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_22_23 … #define mmCM3_CM_RGAM_RAMB_REGION_22_23_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_24_25 … #define mmCM3_CM_RGAM_RAMB_REGION_24_25_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_26_27 … #define mmCM3_CM_RGAM_RAMB_REGION_26_27_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_28_29 … #define mmCM3_CM_RGAM_RAMB_REGION_28_29_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_30_31 … #define mmCM3_CM_RGAM_RAMB_REGION_30_31_BASE_IDX … #define mmCM3_CM_RGAM_RAMB_REGION_32_33 … #define mmCM3_CM_RGAM_RAMB_REGION_32_33_BASE_IDX … #define mmCM3_CM_HDR_MULT_COEF … #define mmCM3_CM_HDR_MULT_COEF_BASE_IDX … #define mmCM3_CM_RANGE_CLAMP_CONTROL_R … #define mmCM3_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX … #define mmCM3_CM_RANGE_CLAMP_CONTROL_G … #define mmCM3_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX … #define mmCM3_CM_RANGE_CLAMP_CONTROL_B … #define mmCM3_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX … #define mmCM3_CM_DENORM_CONTROL … #define mmCM3_CM_DENORM_CONTROL_BASE_IDX … #define mmCM3_CM_CMOUT_CONTROL … #define mmCM3_CM_CMOUT_CONTROL_BASE_IDX … #define mmCM3_CM_CMOUT_RANDOM_SEEDS … #define mmCM3_CM_CMOUT_RANDOM_SEEDS_BASE_IDX … #define mmCM3_CM_MEM_PWR_CTRL … #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX … #define mmCM3_CM_MEM_PWR_STATUS … #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX … #define mmCM3_CM_TEST_DEBUG_INDEX … #define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX … #define mmCM3_CM_TEST_DEBUG_DATA … #define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec // base address: 0x4274 #define mmDC_PERFMON15_PERFCOUNTER_CNTL … #define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON15_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON15_PERFCOUNTER_STATE … #define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON15_PERFMON_CNTL … #define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON15_PERFMON_CNTL2 … #define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON15_PERFMON_CVALUE_LOW … #define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON15_PERFMON_HI … #define mmDC_PERFMON15_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON15_PERFMON_LOW … #define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc0_dispdec // base address: 0x0 #define mmMPCC0_MPCC_TOP_SEL … #define mmMPCC0_MPCC_TOP_SEL_BASE_IDX … #define mmMPCC0_MPCC_BOT_SEL … #define mmMPCC0_MPCC_BOT_SEL_BASE_IDX … #define mmMPCC0_MPCC_OPP_ID … #define mmMPCC0_MPCC_OPP_ID_BASE_IDX … #define mmMPCC0_MPCC_CONTROL … #define mmMPCC0_MPCC_CONTROL_BASE_IDX … #define mmMPCC0_MPCC_SM_CONTROL … #define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX … #define mmMPCC0_MPCC_UPDATE_LOCK_SEL … #define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define mmMPCC0_MPCC_TOP_OFFSET … #define mmMPCC0_MPCC_TOP_OFFSET_BASE_IDX … #define mmMPCC0_MPCC_BOT_OFFSET … #define mmMPCC0_MPCC_BOT_OFFSET_BASE_IDX … #define mmMPCC0_MPCC_OFFSET … #define mmMPCC0_MPCC_OFFSET_BASE_IDX … #define mmMPCC0_MPCC_BG_R_CR … #define mmMPCC0_MPCC_BG_R_CR_BASE_IDX … #define mmMPCC0_MPCC_BG_G_Y … #define mmMPCC0_MPCC_BG_G_Y_BASE_IDX … #define mmMPCC0_MPCC_BG_B_CB … #define mmMPCC0_MPCC_BG_B_CB_BASE_IDX … #define mmMPCC0_MPCC_STALL_STATUS … #define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX … #define mmMPCC0_MPCC_STATUS … #define mmMPCC0_MPCC_STATUS_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc1_dispdec // base address: 0x6c #define mmMPCC1_MPCC_TOP_SEL … #define mmMPCC1_MPCC_TOP_SEL_BASE_IDX … #define mmMPCC1_MPCC_BOT_SEL … #define mmMPCC1_MPCC_BOT_SEL_BASE_IDX … #define mmMPCC1_MPCC_OPP_ID … #define mmMPCC1_MPCC_OPP_ID_BASE_IDX … #define mmMPCC1_MPCC_CONTROL … #define mmMPCC1_MPCC_CONTROL_BASE_IDX … #define mmMPCC1_MPCC_SM_CONTROL … #define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX … #define mmMPCC1_MPCC_UPDATE_LOCK_SEL … #define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define mmMPCC1_MPCC_TOP_OFFSET … #define mmMPCC1_MPCC_TOP_OFFSET_BASE_IDX … #define mmMPCC1_MPCC_BOT_OFFSET … #define mmMPCC1_MPCC_BOT_OFFSET_BASE_IDX … #define mmMPCC1_MPCC_OFFSET … #define mmMPCC1_MPCC_OFFSET_BASE_IDX … #define mmMPCC1_MPCC_BG_R_CR … #define mmMPCC1_MPCC_BG_R_CR_BASE_IDX … #define mmMPCC1_MPCC_BG_G_Y … #define mmMPCC1_MPCC_BG_G_Y_BASE_IDX … #define mmMPCC1_MPCC_BG_B_CB … #define mmMPCC1_MPCC_BG_B_CB_BASE_IDX … #define mmMPCC1_MPCC_STALL_STATUS … #define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX … #define mmMPCC1_MPCC_STATUS … #define mmMPCC1_MPCC_STATUS_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc2_dispdec // base address: 0xd8 #define mmMPCC2_MPCC_TOP_SEL … #define mmMPCC2_MPCC_TOP_SEL_BASE_IDX … #define mmMPCC2_MPCC_BOT_SEL … #define mmMPCC2_MPCC_BOT_SEL_BASE_IDX … #define mmMPCC2_MPCC_OPP_ID … #define mmMPCC2_MPCC_OPP_ID_BASE_IDX … #define mmMPCC2_MPCC_CONTROL … #define mmMPCC2_MPCC_CONTROL_BASE_IDX … #define mmMPCC2_MPCC_SM_CONTROL … #define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX … #define mmMPCC2_MPCC_UPDATE_LOCK_SEL … #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define mmMPCC2_MPCC_TOP_OFFSET … #define mmMPCC2_MPCC_TOP_OFFSET_BASE_IDX … #define mmMPCC2_MPCC_BOT_OFFSET … #define mmMPCC2_MPCC_BOT_OFFSET_BASE_IDX … #define mmMPCC2_MPCC_OFFSET … #define mmMPCC2_MPCC_OFFSET_BASE_IDX … #define mmMPCC2_MPCC_BG_R_CR … #define mmMPCC2_MPCC_BG_R_CR_BASE_IDX … #define mmMPCC2_MPCC_BG_G_Y … #define mmMPCC2_MPCC_BG_G_Y_BASE_IDX … #define mmMPCC2_MPCC_BG_B_CB … #define mmMPCC2_MPCC_BG_B_CB_BASE_IDX … #define mmMPCC2_MPCC_STALL_STATUS … #define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX … #define mmMPCC2_MPCC_STATUS … #define mmMPCC2_MPCC_STATUS_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc3_dispdec // base address: 0x144 #define mmMPCC3_MPCC_TOP_SEL … #define mmMPCC3_MPCC_TOP_SEL_BASE_IDX … #define mmMPCC3_MPCC_BOT_SEL … #define mmMPCC3_MPCC_BOT_SEL_BASE_IDX … #define mmMPCC3_MPCC_OPP_ID … #define mmMPCC3_MPCC_OPP_ID_BASE_IDX … #define mmMPCC3_MPCC_CONTROL … #define mmMPCC3_MPCC_CONTROL_BASE_IDX … #define mmMPCC3_MPCC_SM_CONTROL … #define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX … #define mmMPCC3_MPCC_UPDATE_LOCK_SEL … #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define mmMPCC3_MPCC_TOP_OFFSET … #define mmMPCC3_MPCC_TOP_OFFSET_BASE_IDX … #define mmMPCC3_MPCC_BOT_OFFSET … #define mmMPCC3_MPCC_BOT_OFFSET_BASE_IDX … #define mmMPCC3_MPCC_OFFSET … #define mmMPCC3_MPCC_OFFSET_BASE_IDX … #define mmMPCC3_MPCC_BG_R_CR … #define mmMPCC3_MPCC_BG_R_CR_BASE_IDX … #define mmMPCC3_MPCC_BG_G_Y … #define mmMPCC3_MPCC_BG_G_Y_BASE_IDX … #define mmMPCC3_MPCC_BG_B_CB … #define mmMPCC3_MPCC_BG_B_CB_BASE_IDX … #define mmMPCC3_MPCC_STALL_STATUS … #define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX … #define mmMPCC3_MPCC_STATUS … #define mmMPCC3_MPCC_STATUS_BASE_IDX … // addressBlock: dce_dc_mpc_mpc_cfg_dispdec // base address: 0x0 #define mmMPC_CLOCK_CONTROL … #define mmMPC_CLOCK_CONTROL_BASE_IDX … #define mmMPC_SOFT_RESET … #define mmMPC_SOFT_RESET_BASE_IDX … #define mmMPC_CRC_CTRL … #define mmMPC_CRC_CTRL_BASE_IDX … #define mmMPC_CRC_SEL_CONTROL … #define mmMPC_CRC_SEL_CONTROL_BASE_IDX … #define mmMPC_CRC_RESULT_AR … #define mmMPC_CRC_RESULT_AR_BASE_IDX … #define mmMPC_CRC_RESULT_GB … #define mmMPC_CRC_RESULT_GB_BASE_IDX … #define mmMPC_CRC_RESULT_C … #define mmMPC_CRC_RESULT_C_BASE_IDX … #define mmMPC_PERFMON_EVENT_CTRL … #define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX … #define mmMPC_BYPASS_BG_AR … #define mmMPC_BYPASS_BG_AR_BASE_IDX … #define mmMPC_BYPASS_BG_GB … #define mmMPC_BYPASS_BG_GB_BASE_IDX … #define mmMPC_OUT0_MUX … #define mmMPC_OUT0_MUX_BASE_IDX … #define mmMPC_OUT1_MUX … #define mmMPC_OUT1_MUX_BASE_IDX … #define mmMPC_OUT2_MUX … #define mmMPC_OUT2_MUX_BASE_IDX … #define mmMPC_OUT3_MUX … #define mmMPC_OUT3_MUX_BASE_IDX … #define mmMPC_STALL_GRACE_WINDOW … #define mmMPC_STALL_GRACE_WINDOW_BASE_IDX … #define mmADR_CFG_VUPDATE_LOCK_SET0 … #define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX … #define mmADR_VUPDATE_LOCK_SET0 … #define mmADR_VUPDATE_LOCK_SET0_BASE_IDX … #define mmCUR0_VUPDATE_LOCK_SET0 … #define mmCUR0_VUPDATE_LOCK_SET0_BASE_IDX … #define mmCUR1_VUPDATE_LOCK_SET0 … #define mmCUR1_VUPDATE_LOCK_SET0_BASE_IDX … #define mmADR_CFG_VUPDATE_LOCK_SET1 … #define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX … #define mmADR_VUPDATE_LOCK_SET1 … #define mmADR_VUPDATE_LOCK_SET1_BASE_IDX … #define mmCUR0_VUPDATE_LOCK_SET1 … #define mmCUR0_VUPDATE_LOCK_SET1_BASE_IDX … #define mmCUR1_VUPDATE_LOCK_SET1 … #define mmCUR1_VUPDATE_LOCK_SET1_BASE_IDX … #define mmADR_CFG_VUPDATE_LOCK_SET2 … #define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX … #define mmADR_VUPDATE_LOCK_SET2 … #define mmADR_VUPDATE_LOCK_SET2_BASE_IDX … #define mmCUR0_VUPDATE_LOCK_SET2 … #define mmCUR0_VUPDATE_LOCK_SET2_BASE_IDX … #define mmCUR1_VUPDATE_LOCK_SET2 … #define mmCUR1_VUPDATE_LOCK_SET2_BASE_IDX … #define mmADR_CFG_VUPDATE_LOCK_SET3 … #define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX … #define mmADR_VUPDATE_LOCK_SET3 … #define mmADR_VUPDATE_LOCK_SET3_BASE_IDX … #define mmCUR0_VUPDATE_LOCK_SET3 … #define mmCUR0_VUPDATE_LOCK_SET3_BASE_IDX … #define mmCUR1_VUPDATE_LOCK_SET3 … #define mmCUR1_VUPDATE_LOCK_SET3_BASE_IDX … // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec // base address: 0x5e90 #define mmDC_PERFMON16_PERFCOUNTER_CNTL … #define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON16_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON16_PERFCOUNTER_STATE … #define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON16_PERFMON_CNTL … #define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON16_PERFMON_CNTL2 … #define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON16_PERFMON_CVALUE_LOW … #define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON16_PERFMON_HI … #define mmDC_PERFMON16_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON16_PERFMON_LOW … #define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_opp_abm0_dispdec // base address: 0x0 #define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL … #define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX … #define mmABM0_BL1_PWM_USER_LEVEL … #define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX … #define mmABM0_BL1_PWM_TARGET_ABM_LEVEL … #define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX … #define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL … #define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX … #define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE … #define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE … #define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … #define mmABM0_BL1_PWM_ABM_CNTL … #define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX … #define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … #define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX … #define mmABM0_BL1_PWM_GRP2_REG_LOCK … #define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX … #define mmABM0_DC_ABM1_CNTL … #define mmABM0_DC_ABM1_CNTL_BASE_IDX … #define mmABM0_DC_ABM1_IPCSC_COEFF_SEL … #define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX … #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 … #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX … #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 … #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX … #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 … #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX … #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 … #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX … #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 … #define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX … #define mmABM0_DC_ABM1_ACE_THRES_12 … #define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX … #define mmABM0_DC_ABM1_ACE_THRES_34 … #define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX … #define mmABM0_DC_ABM1_ACE_CNTL_MISC … #define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX … #define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS … #define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX … #define mmABM0_DC_ABM1_HG_MISC_CTRL … #define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX … #define mmABM0_DC_ABM1_LS_SUM_OF_LUMA … #define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX … #define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA … #define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX … #define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA … #define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX … #define mmABM0_DC_ABM1_LS_PIXEL_COUNT … #define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX … #define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES … #define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX … #define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT … #define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX … #define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT … #define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX … #define mmABM0_DC_ABM1_HG_SAMPLE_RATE … #define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX … #define mmABM0_DC_ABM1_LS_SAMPLE_RATE … #define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX … #define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG … #define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX … #define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX … #define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX … #define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX … #define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX … #define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX … #define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX … #define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX … #define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_1 … #define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_2 … #define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_3 … #define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_4 … #define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_5 … #define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_6 … #define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_7 … #define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_8 … #define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_9 … #define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_10 … #define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_11 … #define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_12 … #define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_13 … #define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_14 … #define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_15 … #define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_16 … #define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_17 … #define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_18 … #define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_19 … #define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_20 … #define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_21 … #define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_22 … #define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_23 … #define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX … #define mmABM0_DC_ABM1_HG_RESULT_24 … #define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX … #define mmABM0_DC_ABM1_BL_MASTER_LOCK … #define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX … // addressBlock: dce_dc_opp_abm1_dispdec // base address: 0x118 #define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL … #define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX … #define mmABM1_BL1_PWM_USER_LEVEL … #define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX … #define mmABM1_BL1_PWM_TARGET_ABM_LEVEL … #define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX … #define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL … #define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX … #define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE … #define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … #define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE … #define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX … #define mmABM1_BL1_PWM_ABM_CNTL … #define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX … #define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE … #define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX … #define mmABM1_BL1_PWM_GRP2_REG_LOCK … #define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX … #define mmABM1_DC_ABM1_CNTL … #define mmABM1_DC_ABM1_CNTL_BASE_IDX … #define mmABM1_DC_ABM1_IPCSC_COEFF_SEL … #define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX … #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 … #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX … #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 … #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX … #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 … #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX … #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 … #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX … #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 … #define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX … #define mmABM1_DC_ABM1_ACE_THRES_12 … #define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX … #define mmABM1_DC_ABM1_ACE_THRES_34 … #define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX … #define mmABM1_DC_ABM1_ACE_CNTL_MISC … #define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX … #define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS … #define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX … #define mmABM1_DC_ABM1_HG_MISC_CTRL … #define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX … #define mmABM1_DC_ABM1_LS_SUM_OF_LUMA … #define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX … #define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA … #define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX … #define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA … #define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX … #define mmABM1_DC_ABM1_LS_PIXEL_COUNT … #define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX … #define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES … #define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX … #define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT … #define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX … #define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT … #define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX … #define mmABM1_DC_ABM1_HG_SAMPLE_RATE … #define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX … #define mmABM1_DC_ABM1_LS_SAMPLE_RATE … #define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX … #define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG … #define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX … #define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX … #define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX … #define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX … #define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX … #define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX … #define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX … #define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX … #define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_1 … #define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_2 … #define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_3 … #define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_4 … #define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_5 … #define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_6 … #define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_7 … #define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_8 … #define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_9 … #define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_10 … #define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_11 … #define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_12 … #define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_13 … #define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_14 … #define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_15 … #define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_16 … #define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_17 … #define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_18 … #define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_19 … #define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_20 … #define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_21 … #define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_22 … #define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_23 … #define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX … #define mmABM1_DC_ABM1_HG_RESULT_24 … #define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX … #define mmABM1_DC_ABM1_BL_MASTER_LOCK … #define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX … // addressBlock: dce_dc_opp_fmt0_dispdec // base address: 0x0 #define mmFMT0_FMT_CLAMP_COMPONENT_R … #define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT0_FMT_CLAMP_COMPONENT_G … #define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT0_FMT_CLAMP_COMPONENT_B … #define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT0_FMT_DYNAMIC_EXP_CNTL … #define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT0_FMT_CONTROL … #define mmFMT0_FMT_CONTROL_BASE_IDX … #define mmFMT0_FMT_BIT_DEPTH_CONTROL … #define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT0_FMT_DITHER_RAND_R_SEED … #define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT0_FMT_DITHER_RAND_G_SEED … #define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT0_FMT_DITHER_RAND_B_SEED … #define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT0_FMT_CLAMP_CNTL … #define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT0_FMT_MAP420_MEMORY_CONTROL … #define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_oppbuf0_dispdec // base address: 0x0 #define mmOPPBUF0_OPPBUF_CONTROL … #define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX … #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 … #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 … #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe0_dispdec // base address: 0x0 #define mmOPP_PIPE0_OPP_PIPE_CONTROL … #define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec // base address: 0x0 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dce_dc_opp_fmt1_dispdec // base address: 0x168 #define mmFMT1_FMT_CLAMP_COMPONENT_R … #define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT1_FMT_CLAMP_COMPONENT_G … #define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT1_FMT_CLAMP_COMPONENT_B … #define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT1_FMT_DYNAMIC_EXP_CNTL … #define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT1_FMT_CONTROL … #define mmFMT1_FMT_CONTROL_BASE_IDX … #define mmFMT1_FMT_BIT_DEPTH_CONTROL … #define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT1_FMT_DITHER_RAND_R_SEED … #define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT1_FMT_DITHER_RAND_G_SEED … #define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT1_FMT_DITHER_RAND_B_SEED … #define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT1_FMT_CLAMP_CNTL … #define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT1_FMT_MAP420_MEMORY_CONTROL … #define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_oppbuf1_dispdec // base address: 0x168 #define mmOPPBUF1_OPPBUF_CONTROL … #define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX … #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 … #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 … #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe1_dispdec // base address: 0x168 #define mmOPP_PIPE1_OPP_PIPE_CONTROL … #define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec // base address: 0x168 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dce_dc_opp_fmt2_dispdec // base address: 0x2d0 #define mmFMT2_FMT_CLAMP_COMPONENT_R … #define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT2_FMT_CLAMP_COMPONENT_G … #define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT2_FMT_CLAMP_COMPONENT_B … #define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT2_FMT_DYNAMIC_EXP_CNTL … #define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT2_FMT_CONTROL … #define mmFMT2_FMT_CONTROL_BASE_IDX … #define mmFMT2_FMT_BIT_DEPTH_CONTROL … #define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT2_FMT_DITHER_RAND_R_SEED … #define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT2_FMT_DITHER_RAND_G_SEED … #define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT2_FMT_DITHER_RAND_B_SEED … #define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT2_FMT_CLAMP_CNTL … #define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT2_FMT_MAP420_MEMORY_CONTROL … #define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_oppbuf2_dispdec // base address: 0x2d0 #define mmOPPBUF2_OPPBUF_CONTROL … #define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX … #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 … #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 … #define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe2_dispdec // base address: 0x2d0 #define mmOPP_PIPE2_OPP_PIPE_CONTROL … #define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec // base address: 0x2d0 #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL … #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK … #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX … #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 … #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 … #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 … #define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dce_dc_opp_fmt3_dispdec // base address: 0x438 #define mmFMT3_FMT_CLAMP_COMPONENT_R … #define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT3_FMT_CLAMP_COMPONENT_G … #define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT3_FMT_CLAMP_COMPONENT_B … #define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT3_FMT_DYNAMIC_EXP_CNTL … #define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT3_FMT_CONTROL … #define mmFMT3_FMT_CONTROL_BASE_IDX … #define mmFMT3_FMT_BIT_DEPTH_CONTROL … #define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT3_FMT_DITHER_RAND_R_SEED … #define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT3_FMT_DITHER_RAND_G_SEED … #define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT3_FMT_DITHER_RAND_B_SEED … #define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT3_FMT_CLAMP_CNTL … #define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT3_FMT_MAP420_MEMORY_CONTROL … #define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_oppbuf3_dispdec // base address: 0x438 #define mmOPPBUF3_OPPBUF_CONTROL … #define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX … #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 … #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 … #define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe3_dispdec // base address: 0x438 #define mmOPP_PIPE3_OPP_PIPE_CONTROL … #define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec // base address: 0x438 #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL … #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK … #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX … #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 … #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 … #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 … #define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dce_dc_opp_fmt4_dispdec // base address: 0x5a0 #define mmFMT4_FMT_CLAMP_COMPONENT_R … #define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT4_FMT_CLAMP_COMPONENT_G … #define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT4_FMT_CLAMP_COMPONENT_B … #define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT4_FMT_DYNAMIC_EXP_CNTL … #define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT4_FMT_CONTROL … #define mmFMT4_FMT_CONTROL_BASE_IDX … #define mmFMT4_FMT_BIT_DEPTH_CONTROL … #define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT4_FMT_DITHER_RAND_R_SEED … #define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT4_FMT_DITHER_RAND_G_SEED … #define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT4_FMT_DITHER_RAND_B_SEED … #define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT4_FMT_CLAMP_CNTL … #define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT4_FMT_MAP420_MEMORY_CONTROL … #define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_oppbuf4_dispdec // base address: 0x5a0 #define mmOPPBUF4_OPPBUF_CONTROL … #define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX … #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 … #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 … #define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe4_dispdec // base address: 0x5a0 #define mmOPP_PIPE4_OPP_PIPE_CONTROL … #define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec // base address: 0x5a0 #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL … #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK … #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX … #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 … #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 … #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 … #define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dce_dc_opp_fmt5_dispdec // base address: 0x708 #define mmFMT5_FMT_CLAMP_COMPONENT_R … #define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT5_FMT_CLAMP_COMPONENT_G … #define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT5_FMT_CLAMP_COMPONENT_B … #define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT5_FMT_DYNAMIC_EXP_CNTL … #define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT5_FMT_CONTROL … #define mmFMT5_FMT_CONTROL_BASE_IDX … #define mmFMT5_FMT_BIT_DEPTH_CONTROL … #define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT5_FMT_DITHER_RAND_R_SEED … #define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT5_FMT_DITHER_RAND_G_SEED … #define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT5_FMT_DITHER_RAND_B_SEED … #define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT5_FMT_CLAMP_CNTL … #define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT5_FMT_MAP420_MEMORY_CONTROL … #define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_oppbuf5_dispdec // base address: 0x708 #define mmOPPBUF5_OPPBUF_CONTROL … #define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX … #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 … #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 … #define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe5_dispdec // base address: 0x708 #define mmOPP_PIPE5_OPP_PIPE_CONTROL … #define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec // base address: 0x708 #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL … #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK … #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX … #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 … #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 … #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 … #define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dce_dc_opp_opp_top_dispdec // base address: 0x0 #define mmOPP_TOP_CLK_CONTROL … #define mmOPP_TOP_CLK_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec // base address: 0x6af8 #define mmDC_PERFMON17_PERFCOUNTER_CNTL … #define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON17_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON17_PERFCOUNTER_STATE … #define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON17_PERFMON_CNTL … #define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON17_PERFMON_CNTL2 … #define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON17_PERFMON_CVALUE_LOW … #define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON17_PERFMON_HI … #define mmDC_PERFMON17_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON17_PERFMON_LOW … #define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_optc_odm0_dispdec // base address: 0x0 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL … #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define mmODM0_OPTC_DATA_SOURCE_SELECT … #define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define mmODM0_OPTC_INPUT_CLOCK_CONTROL … #define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … #define mmODM0_OPTC_INPUT_SPARE_REGISTER … #define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_odm1_dispdec // base address: 0x40 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL … #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define mmODM1_OPTC_DATA_SOURCE_SELECT … #define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define mmODM1_OPTC_INPUT_CLOCK_CONTROL … #define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … #define mmODM1_OPTC_INPUT_SPARE_REGISTER … #define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_odm2_dispdec // base address: 0x80 #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL … #define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define mmODM2_OPTC_DATA_SOURCE_SELECT … #define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define mmODM2_OPTC_INPUT_CLOCK_CONTROL … #define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … #define mmODM2_OPTC_INPUT_SPARE_REGISTER … #define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_odm3_dispdec // base address: 0xc0 #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL … #define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define mmODM3_OPTC_DATA_SOURCE_SELECT … #define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define mmODM3_OPTC_INPUT_CLOCK_CONTROL … #define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … #define mmODM3_OPTC_INPUT_SPARE_REGISTER … #define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_odm4_dispdec // base address: 0x100 #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL … #define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define mmODM4_OPTC_DATA_SOURCE_SELECT … #define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define mmODM4_OPTC_INPUT_CLOCK_CONTROL … #define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … #define mmODM4_OPTC_INPUT_SPARE_REGISTER … #define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_odm5_dispdec // base address: 0x140 #define mmODM5_OPTC_INPUT_GLOBAL_CONTROL … #define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define mmODM5_OPTC_DATA_SOURCE_SELECT … #define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define mmODM5_OPTC_INPUT_CLOCK_CONTROL … #define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … #define mmODM5_OPTC_INPUT_SPARE_REGISTER … #define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_otg0_dispdec // base address: 0x0 #define mmOTG0_OTG_H_TOTAL … #define mmOTG0_OTG_H_TOTAL_BASE_IDX … #define mmOTG0_OTG_H_BLANK_START_END … #define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX … #define mmOTG0_OTG_H_SYNC_A … #define mmOTG0_OTG_H_SYNC_A_BASE_IDX … #define mmOTG0_OTG_H_SYNC_A_CNTL … #define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX … #define mmOTG0_OTG_H_TIMING_CNTL … #define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX … #define mmOTG0_OTG_V_TOTAL … #define mmOTG0_OTG_V_TOTAL_BASE_IDX … #define mmOTG0_OTG_V_TOTAL_MIN … #define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX … #define mmOTG0_OTG_V_TOTAL_MAX … #define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX … #define mmOTG0_OTG_V_TOTAL_MID … #define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX … #define mmOTG0_OTG_V_TOTAL_CONTROL … #define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX … #define mmOTG0_OTG_V_TOTAL_INT_STATUS … #define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS … #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmOTG0_OTG_V_BLANK_START_END … #define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX … #define mmOTG0_OTG_V_SYNC_A … #define mmOTG0_OTG_V_SYNC_A_BASE_IDX … #define mmOTG0_OTG_V_SYNC_A_CNTL … #define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX … #define mmOTG0_OTG_TRIGA_CNTL … #define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX … #define mmOTG0_OTG_TRIGA_MANUAL_TRIG … #define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmOTG0_OTG_TRIGB_CNTL … #define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX … #define mmOTG0_OTG_TRIGB_MANUAL_TRIG … #define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL … #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmOTG0_OTG_FLOW_CONTROL … #define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX … #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE … #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmOTG0_OTG_AVSYNC_COUNTER … #define mmOTG0_OTG_AVSYNC_COUNTER_BASE_IDX … #define mmOTG0_OTG_CONTROL … #define mmOTG0_OTG_CONTROL_BASE_IDX … #define mmOTG0_OTG_BLANK_CONTROL … #define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX … #define mmOTG0_OTG_PIPE_ABORT_CONTROL … #define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX … #define mmOTG0_OTG_INTERLACE_CONTROL … #define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX … #define mmOTG0_OTG_INTERLACE_STATUS … #define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX … #define mmOTG0_OTG_FIELD_INDICATION_CONTROL … #define mmOTG0_OTG_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmOTG0_OTG_PIXEL_DATA_READBACK0 … #define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define mmOTG0_OTG_PIXEL_DATA_READBACK1 … #define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define mmOTG0_OTG_STATUS … #define mmOTG0_OTG_STATUS_BASE_IDX … #define mmOTG0_OTG_STATUS_POSITION … #define mmOTG0_OTG_STATUS_POSITION_BASE_IDX … #define mmOTG0_OTG_NOM_VERT_POSITION … #define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX … #define mmOTG0_OTG_STATUS_FRAME_COUNT … #define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define mmOTG0_OTG_STATUS_VF_COUNT … #define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX … #define mmOTG0_OTG_STATUS_HV_COUNT … #define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … #define mmOTG0_OTG_COUNT_CONTROL … #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX … #define mmOTG0_OTG_COUNT_RESET … #define mmOTG0_OTG_COUNT_RESET_BASE_IDX … #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmOTG0_OTG_VERT_SYNC_CONTROL … #define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define mmOTG0_OTG_STEREO_STATUS … #define mmOTG0_OTG_STEREO_STATUS_BASE_IDX … #define mmOTG0_OTG_STEREO_CONTROL … #define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX … #define mmOTG0_OTG_SNAPSHOT_STATUS … #define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX … #define mmOTG0_OTG_SNAPSHOT_CONTROL … #define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define mmOTG0_OTG_SNAPSHOT_POSITION … #define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX … #define mmOTG0_OTG_SNAPSHOT_FRAME … #define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX … #define mmOTG0_OTG_INTERRUPT_CONTROL … #define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX … #define mmOTG0_OTG_UPDATE_LOCK … #define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX … #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL … #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmOTG0_OTG_TEST_PATTERN_CONTROL … #define mmOTG0_OTG_TEST_PATTERN_CONTROL_BASE_IDX … #define mmOTG0_OTG_TEST_PATTERN_PARAMETERS … #define mmOTG0_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmOTG0_OTG_TEST_PATTERN_COLOR … #define mmOTG0_OTG_TEST_PATTERN_COLOR_BASE_IDX … #define mmOTG0_OTG_MASTER_EN … #define mmOTG0_OTG_MASTER_EN_BASE_IDX … #define mmOTG0_OTG_BLANK_DATA_COLOR … #define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX … #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT … #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmOTG0_OTG_BLACK_COLOR … #define mmOTG0_OTG_BLACK_COLOR_BASE_IDX … #define mmOTG0_OTG_BLACK_COLOR_EXT … #define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION … #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL … #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION … #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL … #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION … #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL … #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC_CNTL … #define mmOTG0_OTG_CRC_CNTL_BASE_IDX … #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL … #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL … #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL … #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL … #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC0_DATA_RG … #define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX … #define mmOTG0_OTG_CRC0_DATA_B … #define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX … #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL … #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL … #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL … #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL … #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC1_DATA_RG … #define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX … #define mmOTG0_OTG_CRC1_DATA_B … #define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX … #define mmOTG0_OTG_CRC2_DATA_RG … #define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX … #define mmOTG0_OTG_CRC2_DATA_B … #define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX … #define mmOTG0_OTG_CRC3_DATA_RG … #define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX … #define mmOTG0_OTG_CRC3_DATA_B … #define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX … #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK … #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmOTG0_OTG_STATIC_SCREEN_CONTROL … #define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmOTG0_OTG_3D_STRUCTURE_CONTROL … #define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmOTG0_OTG_GSL_VSYNC_GAP … #define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX … #define mmOTG0_OTG_MASTER_UPDATE_MODE … #define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define mmOTG0_OTG_CLOCK_CONTROL … #define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX … #define mmOTG0_OTG_VSTARTUP_PARAM … #define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX … #define mmOTG0_OTG_VUPDATE_PARAM … #define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX … #define mmOTG0_OTG_VREADY_PARAM … #define mmOTG0_OTG_VREADY_PARAM_BASE_IDX … #define mmOTG0_OTG_GLOBAL_SYNC_STATUS … #define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define mmOTG0_OTG_MASTER_UPDATE_LOCK … #define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define mmOTG0_OTG_GSL_CONTROL … #define mmOTG0_OTG_GSL_CONTROL_BASE_IDX … #define mmOTG0_OTG_GSL_WINDOW_X … #define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX … #define mmOTG0_OTG_GSL_WINDOW_Y … #define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX … #define mmOTG0_OTG_VUPDATE_KEEPOUT … #define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define mmOTG0_OTG_GLOBAL_CONTROL0 … #define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX … #define mmOTG0_OTG_GLOBAL_CONTROL1 … #define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX … #define mmOTG0_OTG_GLOBAL_CONTROL2 … #define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX … #define mmOTG0_OTG_GLOBAL_CONTROL3 … #define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX … #define mmOTG0_OTG_TRIG_MANUAL_CONTROL … #define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define mmOTG0_OTG_MANUAL_FLOW_CONTROL … #define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX … #define mmOTG0_OTG_RANGE_TIMING_INT_STATUS … #define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmOTG0_OTG_DRR_CONTROL … #define mmOTG0_OTG_DRR_CONTROL_BASE_IDX … #define mmOTG0_OTG_REQUEST_CONTROL … #define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX … #define mmOTG0_OTG_SPARE_REGISTER … #define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_otg1_dispdec // base address: 0x200 #define mmOTG1_OTG_H_TOTAL … #define mmOTG1_OTG_H_TOTAL_BASE_IDX … #define mmOTG1_OTG_H_BLANK_START_END … #define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX … #define mmOTG1_OTG_H_SYNC_A … #define mmOTG1_OTG_H_SYNC_A_BASE_IDX … #define mmOTG1_OTG_H_SYNC_A_CNTL … #define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX … #define mmOTG1_OTG_H_TIMING_CNTL … #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX … #define mmOTG1_OTG_V_TOTAL … #define mmOTG1_OTG_V_TOTAL_BASE_IDX … #define mmOTG1_OTG_V_TOTAL_MIN … #define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX … #define mmOTG1_OTG_V_TOTAL_MAX … #define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX … #define mmOTG1_OTG_V_TOTAL_MID … #define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX … #define mmOTG1_OTG_V_TOTAL_CONTROL … #define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX … #define mmOTG1_OTG_V_TOTAL_INT_STATUS … #define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS … #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmOTG1_OTG_V_BLANK_START_END … #define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX … #define mmOTG1_OTG_V_SYNC_A … #define mmOTG1_OTG_V_SYNC_A_BASE_IDX … #define mmOTG1_OTG_V_SYNC_A_CNTL … #define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX … #define mmOTG1_OTG_TRIGA_CNTL … #define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX … #define mmOTG1_OTG_TRIGA_MANUAL_TRIG … #define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmOTG1_OTG_TRIGB_CNTL … #define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX … #define mmOTG1_OTG_TRIGB_MANUAL_TRIG … #define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL … #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmOTG1_OTG_FLOW_CONTROL … #define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX … #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE … #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmOTG1_OTG_AVSYNC_COUNTER … #define mmOTG1_OTG_AVSYNC_COUNTER_BASE_IDX … #define mmOTG1_OTG_CONTROL … #define mmOTG1_OTG_CONTROL_BASE_IDX … #define mmOTG1_OTG_BLANK_CONTROL … #define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX … #define mmOTG1_OTG_PIPE_ABORT_CONTROL … #define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX … #define mmOTG1_OTG_INTERLACE_CONTROL … #define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX … #define mmOTG1_OTG_INTERLACE_STATUS … #define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX … #define mmOTG1_OTG_FIELD_INDICATION_CONTROL … #define mmOTG1_OTG_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmOTG1_OTG_PIXEL_DATA_READBACK0 … #define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define mmOTG1_OTG_PIXEL_DATA_READBACK1 … #define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define mmOTG1_OTG_STATUS … #define mmOTG1_OTG_STATUS_BASE_IDX … #define mmOTG1_OTG_STATUS_POSITION … #define mmOTG1_OTG_STATUS_POSITION_BASE_IDX … #define mmOTG1_OTG_NOM_VERT_POSITION … #define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX … #define mmOTG1_OTG_STATUS_FRAME_COUNT … #define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define mmOTG1_OTG_STATUS_VF_COUNT … #define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX … #define mmOTG1_OTG_STATUS_HV_COUNT … #define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX … #define mmOTG1_OTG_COUNT_CONTROL … #define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX … #define mmOTG1_OTG_COUNT_RESET … #define mmOTG1_OTG_COUNT_RESET_BASE_IDX … #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmOTG1_OTG_VERT_SYNC_CONTROL … #define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define mmOTG1_OTG_STEREO_STATUS … #define mmOTG1_OTG_STEREO_STATUS_BASE_IDX … #define mmOTG1_OTG_STEREO_CONTROL … #define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX … #define mmOTG1_OTG_SNAPSHOT_STATUS … #define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX … #define mmOTG1_OTG_SNAPSHOT_CONTROL … #define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define mmOTG1_OTG_SNAPSHOT_POSITION … #define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX … #define mmOTG1_OTG_SNAPSHOT_FRAME … #define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX … #define mmOTG1_OTG_INTERRUPT_CONTROL … #define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX … #define mmOTG1_OTG_UPDATE_LOCK … #define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX … #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL … #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmOTG1_OTG_TEST_PATTERN_CONTROL … #define mmOTG1_OTG_TEST_PATTERN_CONTROL_BASE_IDX … #define mmOTG1_OTG_TEST_PATTERN_PARAMETERS … #define mmOTG1_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmOTG1_OTG_TEST_PATTERN_COLOR … #define mmOTG1_OTG_TEST_PATTERN_COLOR_BASE_IDX … #define mmOTG1_OTG_MASTER_EN … #define mmOTG1_OTG_MASTER_EN_BASE_IDX … #define mmOTG1_OTG_BLANK_DATA_COLOR … #define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX … #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT … #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmOTG1_OTG_BLACK_COLOR … #define mmOTG1_OTG_BLACK_COLOR_BASE_IDX … #define mmOTG1_OTG_BLACK_COLOR_EXT … #define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION … #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL … #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION … #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL … #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION … #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL … #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC_CNTL … #define mmOTG1_OTG_CRC_CNTL_BASE_IDX … #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL … #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL … #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL … #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL … #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC0_DATA_RG … #define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX … #define mmOTG1_OTG_CRC0_DATA_B … #define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX … #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL … #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL … #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL … #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL … #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC1_DATA_RG … #define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX … #define mmOTG1_OTG_CRC1_DATA_B … #define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX … #define mmOTG1_OTG_CRC2_DATA_RG … #define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX … #define mmOTG1_OTG_CRC2_DATA_B … #define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX … #define mmOTG1_OTG_CRC3_DATA_RG … #define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX … #define mmOTG1_OTG_CRC3_DATA_B … #define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX … #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK … #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmOTG1_OTG_STATIC_SCREEN_CONTROL … #define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmOTG1_OTG_3D_STRUCTURE_CONTROL … #define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmOTG1_OTG_GSL_VSYNC_GAP … #define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX … #define mmOTG1_OTG_MASTER_UPDATE_MODE … #define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define mmOTG1_OTG_CLOCK_CONTROL … #define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX … #define mmOTG1_OTG_VSTARTUP_PARAM … #define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX … #define mmOTG1_OTG_VUPDATE_PARAM … #define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX … #define mmOTG1_OTG_VREADY_PARAM … #define mmOTG1_OTG_VREADY_PARAM_BASE_IDX … #define mmOTG1_OTG_GLOBAL_SYNC_STATUS … #define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define mmOTG1_OTG_MASTER_UPDATE_LOCK … #define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define mmOTG1_OTG_GSL_CONTROL … #define mmOTG1_OTG_GSL_CONTROL_BASE_IDX … #define mmOTG1_OTG_GSL_WINDOW_X … #define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX … #define mmOTG1_OTG_GSL_WINDOW_Y … #define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX … #define mmOTG1_OTG_VUPDATE_KEEPOUT … #define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define mmOTG1_OTG_GLOBAL_CONTROL0 … #define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX … #define mmOTG1_OTG_GLOBAL_CONTROL1 … #define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX … #define mmOTG1_OTG_GLOBAL_CONTROL2 … #define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX … #define mmOTG1_OTG_GLOBAL_CONTROL3 … #define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX … #define mmOTG1_OTG_TRIG_MANUAL_CONTROL … #define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define mmOTG1_OTG_MANUAL_FLOW_CONTROL … #define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX … #define mmOTG1_OTG_RANGE_TIMING_INT_STATUS … #define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmOTG1_OTG_DRR_CONTROL … #define mmOTG1_OTG_DRR_CONTROL_BASE_IDX … #define mmOTG1_OTG_REQUEST_CONTROL … #define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX … #define mmOTG1_OTG_SPARE_REGISTER … #define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_otg2_dispdec // base address: 0x400 #define mmOTG2_OTG_H_TOTAL … #define mmOTG2_OTG_H_TOTAL_BASE_IDX … #define mmOTG2_OTG_H_BLANK_START_END … #define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX … #define mmOTG2_OTG_H_SYNC_A … #define mmOTG2_OTG_H_SYNC_A_BASE_IDX … #define mmOTG2_OTG_H_SYNC_A_CNTL … #define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX … #define mmOTG2_OTG_H_TIMING_CNTL … #define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX … #define mmOTG2_OTG_V_TOTAL … #define mmOTG2_OTG_V_TOTAL_BASE_IDX … #define mmOTG2_OTG_V_TOTAL_MIN … #define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX … #define mmOTG2_OTG_V_TOTAL_MAX … #define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX … #define mmOTG2_OTG_V_TOTAL_MID … #define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX … #define mmOTG2_OTG_V_TOTAL_CONTROL … #define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX … #define mmOTG2_OTG_V_TOTAL_INT_STATUS … #define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS … #define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmOTG2_OTG_V_BLANK_START_END … #define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX … #define mmOTG2_OTG_V_SYNC_A … #define mmOTG2_OTG_V_SYNC_A_BASE_IDX … #define mmOTG2_OTG_V_SYNC_A_CNTL … #define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX … #define mmOTG2_OTG_TRIGA_CNTL … #define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX … #define mmOTG2_OTG_TRIGA_MANUAL_TRIG … #define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmOTG2_OTG_TRIGB_CNTL … #define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX … #define mmOTG2_OTG_TRIGB_MANUAL_TRIG … #define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL … #define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmOTG2_OTG_FLOW_CONTROL … #define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX … #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE … #define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmOTG2_OTG_AVSYNC_COUNTER … #define mmOTG2_OTG_AVSYNC_COUNTER_BASE_IDX … #define mmOTG2_OTG_CONTROL … #define mmOTG2_OTG_CONTROL_BASE_IDX … #define mmOTG2_OTG_BLANK_CONTROL … #define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX … #define mmOTG2_OTG_PIPE_ABORT_CONTROL … #define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX … #define mmOTG2_OTG_INTERLACE_CONTROL … #define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX … #define mmOTG2_OTG_INTERLACE_STATUS … #define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX … #define mmOTG2_OTG_FIELD_INDICATION_CONTROL … #define mmOTG2_OTG_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmOTG2_OTG_PIXEL_DATA_READBACK0 … #define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define mmOTG2_OTG_PIXEL_DATA_READBACK1 … #define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define mmOTG2_OTG_STATUS … #define mmOTG2_OTG_STATUS_BASE_IDX … #define mmOTG2_OTG_STATUS_POSITION … #define mmOTG2_OTG_STATUS_POSITION_BASE_IDX … #define mmOTG2_OTG_NOM_VERT_POSITION … #define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX … #define mmOTG2_OTG_STATUS_FRAME_COUNT … #define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define mmOTG2_OTG_STATUS_VF_COUNT … #define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX … #define mmOTG2_OTG_STATUS_HV_COUNT … #define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX … #define mmOTG2_OTG_COUNT_CONTROL … #define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX … #define mmOTG2_OTG_COUNT_RESET … #define mmOTG2_OTG_COUNT_RESET_BASE_IDX … #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmOTG2_OTG_VERT_SYNC_CONTROL … #define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define mmOTG2_OTG_STEREO_STATUS … #define mmOTG2_OTG_STEREO_STATUS_BASE_IDX … #define mmOTG2_OTG_STEREO_CONTROL … #define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX … #define mmOTG2_OTG_SNAPSHOT_STATUS … #define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX … #define mmOTG2_OTG_SNAPSHOT_CONTROL … #define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define mmOTG2_OTG_SNAPSHOT_POSITION … #define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX … #define mmOTG2_OTG_SNAPSHOT_FRAME … #define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX … #define mmOTG2_OTG_INTERRUPT_CONTROL … #define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX … #define mmOTG2_OTG_UPDATE_LOCK … #define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX … #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL … #define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmOTG2_OTG_TEST_PATTERN_CONTROL … #define mmOTG2_OTG_TEST_PATTERN_CONTROL_BASE_IDX … #define mmOTG2_OTG_TEST_PATTERN_PARAMETERS … #define mmOTG2_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmOTG2_OTG_TEST_PATTERN_COLOR … #define mmOTG2_OTG_TEST_PATTERN_COLOR_BASE_IDX … #define mmOTG2_OTG_MASTER_EN … #define mmOTG2_OTG_MASTER_EN_BASE_IDX … #define mmOTG2_OTG_BLANK_DATA_COLOR … #define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX … #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT … #define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmOTG2_OTG_BLACK_COLOR … #define mmOTG2_OTG_BLACK_COLOR_BASE_IDX … #define mmOTG2_OTG_BLACK_COLOR_EXT … #define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX … #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION … #define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL … #define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION … #define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL … #define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION … #define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL … #define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmOTG2_OTG_CRC_CNTL … #define mmOTG2_OTG_CRC_CNTL_BASE_IDX … #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL … #define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL … #define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL … #define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL … #define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG2_OTG_CRC0_DATA_RG … #define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX … #define mmOTG2_OTG_CRC0_DATA_B … #define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX … #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL … #define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL … #define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL … #define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL … #define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG2_OTG_CRC1_DATA_RG … #define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX … #define mmOTG2_OTG_CRC1_DATA_B … #define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX … #define mmOTG2_OTG_CRC2_DATA_RG … #define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX … #define mmOTG2_OTG_CRC2_DATA_B … #define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX … #define mmOTG2_OTG_CRC3_DATA_RG … #define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX … #define mmOTG2_OTG_CRC3_DATA_B … #define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX … #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK … #define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmOTG2_OTG_STATIC_SCREEN_CONTROL … #define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmOTG2_OTG_3D_STRUCTURE_CONTROL … #define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmOTG2_OTG_GSL_VSYNC_GAP … #define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX … #define mmOTG2_OTG_MASTER_UPDATE_MODE … #define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define mmOTG2_OTG_CLOCK_CONTROL … #define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX … #define mmOTG2_OTG_VSTARTUP_PARAM … #define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX … #define mmOTG2_OTG_VUPDATE_PARAM … #define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX … #define mmOTG2_OTG_VREADY_PARAM … #define mmOTG2_OTG_VREADY_PARAM_BASE_IDX … #define mmOTG2_OTG_GLOBAL_SYNC_STATUS … #define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define mmOTG2_OTG_MASTER_UPDATE_LOCK … #define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define mmOTG2_OTG_GSL_CONTROL … #define mmOTG2_OTG_GSL_CONTROL_BASE_IDX … #define mmOTG2_OTG_GSL_WINDOW_X … #define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX … #define mmOTG2_OTG_GSL_WINDOW_Y … #define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX … #define mmOTG2_OTG_VUPDATE_KEEPOUT … #define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define mmOTG2_OTG_GLOBAL_CONTROL0 … #define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX … #define mmOTG2_OTG_GLOBAL_CONTROL1 … #define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX … #define mmOTG2_OTG_GLOBAL_CONTROL2 … #define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX … #define mmOTG2_OTG_GLOBAL_CONTROL3 … #define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX … #define mmOTG2_OTG_TRIG_MANUAL_CONTROL … #define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define mmOTG2_OTG_MANUAL_FLOW_CONTROL … #define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX … #define mmOTG2_OTG_RANGE_TIMING_INT_STATUS … #define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmOTG2_OTG_DRR_CONTROL … #define mmOTG2_OTG_DRR_CONTROL_BASE_IDX … #define mmOTG2_OTG_REQUEST_CONTROL … #define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX … #define mmOTG2_OTG_SPARE_REGISTER … #define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_otg3_dispdec // base address: 0x600 #define mmOTG3_OTG_H_TOTAL … #define mmOTG3_OTG_H_TOTAL_BASE_IDX … #define mmOTG3_OTG_H_BLANK_START_END … #define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX … #define mmOTG3_OTG_H_SYNC_A … #define mmOTG3_OTG_H_SYNC_A_BASE_IDX … #define mmOTG3_OTG_H_SYNC_A_CNTL … #define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX … #define mmOTG3_OTG_H_TIMING_CNTL … #define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX … #define mmOTG3_OTG_V_TOTAL … #define mmOTG3_OTG_V_TOTAL_BASE_IDX … #define mmOTG3_OTG_V_TOTAL_MIN … #define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX … #define mmOTG3_OTG_V_TOTAL_MAX … #define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX … #define mmOTG3_OTG_V_TOTAL_MID … #define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX … #define mmOTG3_OTG_V_TOTAL_CONTROL … #define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX … #define mmOTG3_OTG_V_TOTAL_INT_STATUS … #define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS … #define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmOTG3_OTG_V_BLANK_START_END … #define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX … #define mmOTG3_OTG_V_SYNC_A … #define mmOTG3_OTG_V_SYNC_A_BASE_IDX … #define mmOTG3_OTG_V_SYNC_A_CNTL … #define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX … #define mmOTG3_OTG_TRIGA_CNTL … #define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX … #define mmOTG3_OTG_TRIGA_MANUAL_TRIG … #define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmOTG3_OTG_TRIGB_CNTL … #define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX … #define mmOTG3_OTG_TRIGB_MANUAL_TRIG … #define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL … #define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmOTG3_OTG_FLOW_CONTROL … #define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX … #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE … #define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmOTG3_OTG_AVSYNC_COUNTER … #define mmOTG3_OTG_AVSYNC_COUNTER_BASE_IDX … #define mmOTG3_OTG_CONTROL … #define mmOTG3_OTG_CONTROL_BASE_IDX … #define mmOTG3_OTG_BLANK_CONTROL … #define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX … #define mmOTG3_OTG_PIPE_ABORT_CONTROL … #define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX … #define mmOTG3_OTG_INTERLACE_CONTROL … #define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX … #define mmOTG3_OTG_INTERLACE_STATUS … #define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX … #define mmOTG3_OTG_FIELD_INDICATION_CONTROL … #define mmOTG3_OTG_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmOTG3_OTG_PIXEL_DATA_READBACK0 … #define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define mmOTG3_OTG_PIXEL_DATA_READBACK1 … #define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define mmOTG3_OTG_STATUS … #define mmOTG3_OTG_STATUS_BASE_IDX … #define mmOTG3_OTG_STATUS_POSITION … #define mmOTG3_OTG_STATUS_POSITION_BASE_IDX … #define mmOTG3_OTG_NOM_VERT_POSITION … #define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX … #define mmOTG3_OTG_STATUS_FRAME_COUNT … #define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define mmOTG3_OTG_STATUS_VF_COUNT … #define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX … #define mmOTG3_OTG_STATUS_HV_COUNT … #define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX … #define mmOTG3_OTG_COUNT_CONTROL … #define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX … #define mmOTG3_OTG_COUNT_RESET … #define mmOTG3_OTG_COUNT_RESET_BASE_IDX … #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmOTG3_OTG_VERT_SYNC_CONTROL … #define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define mmOTG3_OTG_STEREO_STATUS … #define mmOTG3_OTG_STEREO_STATUS_BASE_IDX … #define mmOTG3_OTG_STEREO_CONTROL … #define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX … #define mmOTG3_OTG_SNAPSHOT_STATUS … #define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX … #define mmOTG3_OTG_SNAPSHOT_CONTROL … #define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define mmOTG3_OTG_SNAPSHOT_POSITION … #define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX … #define mmOTG3_OTG_SNAPSHOT_FRAME … #define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX … #define mmOTG3_OTG_INTERRUPT_CONTROL … #define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX … #define mmOTG3_OTG_UPDATE_LOCK … #define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX … #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL … #define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmOTG3_OTG_TEST_PATTERN_CONTROL … #define mmOTG3_OTG_TEST_PATTERN_CONTROL_BASE_IDX … #define mmOTG3_OTG_TEST_PATTERN_PARAMETERS … #define mmOTG3_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmOTG3_OTG_TEST_PATTERN_COLOR … #define mmOTG3_OTG_TEST_PATTERN_COLOR_BASE_IDX … #define mmOTG3_OTG_MASTER_EN … #define mmOTG3_OTG_MASTER_EN_BASE_IDX … #define mmOTG3_OTG_BLANK_DATA_COLOR … #define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX … #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT … #define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmOTG3_OTG_BLACK_COLOR … #define mmOTG3_OTG_BLACK_COLOR_BASE_IDX … #define mmOTG3_OTG_BLACK_COLOR_EXT … #define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX … #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION … #define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL … #define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION … #define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL … #define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION … #define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL … #define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmOTG3_OTG_CRC_CNTL … #define mmOTG3_OTG_CRC_CNTL_BASE_IDX … #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL … #define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL … #define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL … #define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL … #define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG3_OTG_CRC0_DATA_RG … #define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX … #define mmOTG3_OTG_CRC0_DATA_B … #define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX … #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL … #define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL … #define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL … #define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL … #define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG3_OTG_CRC1_DATA_RG … #define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX … #define mmOTG3_OTG_CRC1_DATA_B … #define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX … #define mmOTG3_OTG_CRC2_DATA_RG … #define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX … #define mmOTG3_OTG_CRC2_DATA_B … #define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX … #define mmOTG3_OTG_CRC3_DATA_RG … #define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX … #define mmOTG3_OTG_CRC3_DATA_B … #define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX … #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK … #define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmOTG3_OTG_STATIC_SCREEN_CONTROL … #define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmOTG3_OTG_3D_STRUCTURE_CONTROL … #define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmOTG3_OTG_GSL_VSYNC_GAP … #define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX … #define mmOTG3_OTG_MASTER_UPDATE_MODE … #define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define mmOTG3_OTG_CLOCK_CONTROL … #define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX … #define mmOTG3_OTG_VSTARTUP_PARAM … #define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX … #define mmOTG3_OTG_VUPDATE_PARAM … #define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX … #define mmOTG3_OTG_VREADY_PARAM … #define mmOTG3_OTG_VREADY_PARAM_BASE_IDX … #define mmOTG3_OTG_GLOBAL_SYNC_STATUS … #define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define mmOTG3_OTG_MASTER_UPDATE_LOCK … #define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define mmOTG3_OTG_GSL_CONTROL … #define mmOTG3_OTG_GSL_CONTROL_BASE_IDX … #define mmOTG3_OTG_GSL_WINDOW_X … #define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX … #define mmOTG3_OTG_GSL_WINDOW_Y … #define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX … #define mmOTG3_OTG_VUPDATE_KEEPOUT … #define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define mmOTG3_OTG_GLOBAL_CONTROL0 … #define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX … #define mmOTG3_OTG_GLOBAL_CONTROL1 … #define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX … #define mmOTG3_OTG_GLOBAL_CONTROL2 … #define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX … #define mmOTG3_OTG_GLOBAL_CONTROL3 … #define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX … #define mmOTG3_OTG_TRIG_MANUAL_CONTROL … #define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define mmOTG3_OTG_MANUAL_FLOW_CONTROL … #define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX … #define mmOTG3_OTG_RANGE_TIMING_INT_STATUS … #define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmOTG3_OTG_DRR_CONTROL … #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX … #define mmOTG3_OTG_REQUEST_CONTROL … #define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX … #define mmOTG3_OTG_SPARE_REGISTER … #define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_otg4_dispdec // base address: 0x800 #define mmOTG4_OTG_H_TOTAL … #define mmOTG4_OTG_H_TOTAL_BASE_IDX … #define mmOTG4_OTG_H_BLANK_START_END … #define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX … #define mmOTG4_OTG_H_SYNC_A … #define mmOTG4_OTG_H_SYNC_A_BASE_IDX … #define mmOTG4_OTG_H_SYNC_A_CNTL … #define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX … #define mmOTG4_OTG_H_TIMING_CNTL … #define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX … #define mmOTG4_OTG_V_TOTAL … #define mmOTG4_OTG_V_TOTAL_BASE_IDX … #define mmOTG4_OTG_V_TOTAL_MIN … #define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX … #define mmOTG4_OTG_V_TOTAL_MAX … #define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX … #define mmOTG4_OTG_V_TOTAL_MID … #define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX … #define mmOTG4_OTG_V_TOTAL_CONTROL … #define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX … #define mmOTG4_OTG_V_TOTAL_INT_STATUS … #define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS … #define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmOTG4_OTG_V_BLANK_START_END … #define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX … #define mmOTG4_OTG_V_SYNC_A … #define mmOTG4_OTG_V_SYNC_A_BASE_IDX … #define mmOTG4_OTG_V_SYNC_A_CNTL … #define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX … #define mmOTG4_OTG_TRIGA_CNTL … #define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX … #define mmOTG4_OTG_TRIGA_MANUAL_TRIG … #define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmOTG4_OTG_TRIGB_CNTL … #define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX … #define mmOTG4_OTG_TRIGB_MANUAL_TRIG … #define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL … #define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmOTG4_OTG_FLOW_CONTROL … #define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX … #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE … #define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmOTG4_OTG_AVSYNC_COUNTER … #define mmOTG4_OTG_AVSYNC_COUNTER_BASE_IDX … #define mmOTG4_OTG_CONTROL … #define mmOTG4_OTG_CONTROL_BASE_IDX … #define mmOTG4_OTG_BLANK_CONTROL … #define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX … #define mmOTG4_OTG_PIPE_ABORT_CONTROL … #define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX … #define mmOTG4_OTG_INTERLACE_CONTROL … #define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX … #define mmOTG4_OTG_INTERLACE_STATUS … #define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX … #define mmOTG4_OTG_FIELD_INDICATION_CONTROL … #define mmOTG4_OTG_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmOTG4_OTG_PIXEL_DATA_READBACK0 … #define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define mmOTG4_OTG_PIXEL_DATA_READBACK1 … #define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define mmOTG4_OTG_STATUS … #define mmOTG4_OTG_STATUS_BASE_IDX … #define mmOTG4_OTG_STATUS_POSITION … #define mmOTG4_OTG_STATUS_POSITION_BASE_IDX … #define mmOTG4_OTG_NOM_VERT_POSITION … #define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX … #define mmOTG4_OTG_STATUS_FRAME_COUNT … #define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define mmOTG4_OTG_STATUS_VF_COUNT … #define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX … #define mmOTG4_OTG_STATUS_HV_COUNT … #define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX … #define mmOTG4_OTG_COUNT_CONTROL … #define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX … #define mmOTG4_OTG_COUNT_RESET … #define mmOTG4_OTG_COUNT_RESET_BASE_IDX … #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmOTG4_OTG_VERT_SYNC_CONTROL … #define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define mmOTG4_OTG_STEREO_STATUS … #define mmOTG4_OTG_STEREO_STATUS_BASE_IDX … #define mmOTG4_OTG_STEREO_CONTROL … #define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX … #define mmOTG4_OTG_SNAPSHOT_STATUS … #define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX … #define mmOTG4_OTG_SNAPSHOT_CONTROL … #define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define mmOTG4_OTG_SNAPSHOT_POSITION … #define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX … #define mmOTG4_OTG_SNAPSHOT_FRAME … #define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX … #define mmOTG4_OTG_INTERRUPT_CONTROL … #define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX … #define mmOTG4_OTG_UPDATE_LOCK … #define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX … #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL … #define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmOTG4_OTG_TEST_PATTERN_CONTROL … #define mmOTG4_OTG_TEST_PATTERN_CONTROL_BASE_IDX … #define mmOTG4_OTG_TEST_PATTERN_PARAMETERS … #define mmOTG4_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmOTG4_OTG_TEST_PATTERN_COLOR … #define mmOTG4_OTG_TEST_PATTERN_COLOR_BASE_IDX … #define mmOTG4_OTG_MASTER_EN … #define mmOTG4_OTG_MASTER_EN_BASE_IDX … #define mmOTG4_OTG_BLANK_DATA_COLOR … #define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX … #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT … #define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmOTG4_OTG_BLACK_COLOR … #define mmOTG4_OTG_BLACK_COLOR_BASE_IDX … #define mmOTG4_OTG_BLACK_COLOR_EXT … #define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX … #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION … #define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL … #define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION … #define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL … #define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION … #define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL … #define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmOTG4_OTG_CRC_CNTL … #define mmOTG4_OTG_CRC_CNTL_BASE_IDX … #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL … #define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL … #define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL … #define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL … #define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG4_OTG_CRC0_DATA_RG … #define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX … #define mmOTG4_OTG_CRC0_DATA_B … #define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX … #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL … #define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL … #define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL … #define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL … #define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG4_OTG_CRC1_DATA_RG … #define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX … #define mmOTG4_OTG_CRC1_DATA_B … #define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX … #define mmOTG4_OTG_CRC2_DATA_RG … #define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX … #define mmOTG4_OTG_CRC2_DATA_B … #define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX … #define mmOTG4_OTG_CRC3_DATA_RG … #define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX … #define mmOTG4_OTG_CRC3_DATA_B … #define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX … #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK … #define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmOTG4_OTG_STATIC_SCREEN_CONTROL … #define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmOTG4_OTG_3D_STRUCTURE_CONTROL … #define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmOTG4_OTG_GSL_VSYNC_GAP … #define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX … #define mmOTG4_OTG_MASTER_UPDATE_MODE … #define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define mmOTG4_OTG_CLOCK_CONTROL … #define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX … #define mmOTG4_OTG_VSTARTUP_PARAM … #define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX … #define mmOTG4_OTG_VUPDATE_PARAM … #define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX … #define mmOTG4_OTG_VREADY_PARAM … #define mmOTG4_OTG_VREADY_PARAM_BASE_IDX … #define mmOTG4_OTG_GLOBAL_SYNC_STATUS … #define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define mmOTG4_OTG_MASTER_UPDATE_LOCK … #define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define mmOTG4_OTG_GSL_CONTROL … #define mmOTG4_OTG_GSL_CONTROL_BASE_IDX … #define mmOTG4_OTG_GSL_WINDOW_X … #define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX … #define mmOTG4_OTG_GSL_WINDOW_Y … #define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX … #define mmOTG4_OTG_VUPDATE_KEEPOUT … #define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define mmOTG4_OTG_GLOBAL_CONTROL0 … #define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX … #define mmOTG4_OTG_GLOBAL_CONTROL1 … #define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX … #define mmOTG4_OTG_GLOBAL_CONTROL2 … #define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX … #define mmOTG4_OTG_GLOBAL_CONTROL3 … #define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX … #define mmOTG4_OTG_TRIG_MANUAL_CONTROL … #define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define mmOTG4_OTG_MANUAL_FLOW_CONTROL … #define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX … #define mmOTG4_OTG_RANGE_TIMING_INT_STATUS … #define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmOTG4_OTG_DRR_CONTROL … #define mmOTG4_OTG_DRR_CONTROL_BASE_IDX … #define mmOTG4_OTG_REQUEST_CONTROL … #define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX … #define mmOTG4_OTG_SPARE_REGISTER … #define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_otg5_dispdec // base address: 0xa00 #define mmOTG5_OTG_H_TOTAL … #define mmOTG5_OTG_H_TOTAL_BASE_IDX … #define mmOTG5_OTG_H_BLANK_START_END … #define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX … #define mmOTG5_OTG_H_SYNC_A … #define mmOTG5_OTG_H_SYNC_A_BASE_IDX … #define mmOTG5_OTG_H_SYNC_A_CNTL … #define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX … #define mmOTG5_OTG_H_TIMING_CNTL … #define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX … #define mmOTG5_OTG_V_TOTAL … #define mmOTG5_OTG_V_TOTAL_BASE_IDX … #define mmOTG5_OTG_V_TOTAL_MIN … #define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX … #define mmOTG5_OTG_V_TOTAL_MAX … #define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX … #define mmOTG5_OTG_V_TOTAL_MID … #define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX … #define mmOTG5_OTG_V_TOTAL_CONTROL … #define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX … #define mmOTG5_OTG_V_TOTAL_INT_STATUS … #define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define mmOTG5_OTG_VSYNC_NOM_INT_STATUS … #define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmOTG5_OTG_V_BLANK_START_END … #define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX … #define mmOTG5_OTG_V_SYNC_A … #define mmOTG5_OTG_V_SYNC_A_BASE_IDX … #define mmOTG5_OTG_V_SYNC_A_CNTL … #define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX … #define mmOTG5_OTG_TRIGA_CNTL … #define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX … #define mmOTG5_OTG_TRIGA_MANUAL_TRIG … #define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmOTG5_OTG_TRIGB_CNTL … #define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX … #define mmOTG5_OTG_TRIGB_MANUAL_TRIG … #define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL … #define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmOTG5_OTG_FLOW_CONTROL … #define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX … #define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE … #define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmOTG5_OTG_AVSYNC_COUNTER … #define mmOTG5_OTG_AVSYNC_COUNTER_BASE_IDX … #define mmOTG5_OTG_CONTROL … #define mmOTG5_OTG_CONTROL_BASE_IDX … #define mmOTG5_OTG_BLANK_CONTROL … #define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX … #define mmOTG5_OTG_PIPE_ABORT_CONTROL … #define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX … #define mmOTG5_OTG_INTERLACE_CONTROL … #define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX … #define mmOTG5_OTG_INTERLACE_STATUS … #define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX … #define mmOTG5_OTG_FIELD_INDICATION_CONTROL … #define mmOTG5_OTG_FIELD_INDICATION_CONTROL_BASE_IDX … #define mmOTG5_OTG_PIXEL_DATA_READBACK0 … #define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define mmOTG5_OTG_PIXEL_DATA_READBACK1 … #define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define mmOTG5_OTG_STATUS … #define mmOTG5_OTG_STATUS_BASE_IDX … #define mmOTG5_OTG_STATUS_POSITION … #define mmOTG5_OTG_STATUS_POSITION_BASE_IDX … #define mmOTG5_OTG_NOM_VERT_POSITION … #define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX … #define mmOTG5_OTG_STATUS_FRAME_COUNT … #define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define mmOTG5_OTG_STATUS_VF_COUNT … #define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX … #define mmOTG5_OTG_STATUS_HV_COUNT … #define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX … #define mmOTG5_OTG_COUNT_CONTROL … #define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX … #define mmOTG5_OTG_COUNT_RESET … #define mmOTG5_OTG_COUNT_RESET_BASE_IDX … #define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmOTG5_OTG_VERT_SYNC_CONTROL … #define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define mmOTG5_OTG_STEREO_STATUS … #define mmOTG5_OTG_STEREO_STATUS_BASE_IDX … #define mmOTG5_OTG_STEREO_CONTROL … #define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX … #define mmOTG5_OTG_SNAPSHOT_STATUS … #define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX … #define mmOTG5_OTG_SNAPSHOT_CONTROL … #define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define mmOTG5_OTG_SNAPSHOT_POSITION … #define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX … #define mmOTG5_OTG_SNAPSHOT_FRAME … #define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX … #define mmOTG5_OTG_INTERRUPT_CONTROL … #define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX … #define mmOTG5_OTG_UPDATE_LOCK … #define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX … #define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL … #define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmOTG5_OTG_TEST_PATTERN_CONTROL … #define mmOTG5_OTG_TEST_PATTERN_CONTROL_BASE_IDX … #define mmOTG5_OTG_TEST_PATTERN_PARAMETERS … #define mmOTG5_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX … #define mmOTG5_OTG_TEST_PATTERN_COLOR … #define mmOTG5_OTG_TEST_PATTERN_COLOR_BASE_IDX … #define mmOTG5_OTG_MASTER_EN … #define mmOTG5_OTG_MASTER_EN_BASE_IDX … #define mmOTG5_OTG_BLANK_DATA_COLOR … #define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX … #define mmOTG5_OTG_BLANK_DATA_COLOR_EXT … #define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmOTG5_OTG_BLACK_COLOR … #define mmOTG5_OTG_BLACK_COLOR_BASE_IDX … #define mmOTG5_OTG_BLACK_COLOR_EXT … #define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX … #define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION … #define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL … #define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION … #define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL … #define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION … #define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL … #define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmOTG5_OTG_CRC_CNTL … #define mmOTG5_OTG_CRC_CNTL_BASE_IDX … #define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL … #define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL … #define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL … #define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL … #define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG5_OTG_CRC0_DATA_RG … #define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX … #define mmOTG5_OTG_CRC0_DATA_B … #define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX … #define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL … #define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL … #define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL … #define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL … #define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG5_OTG_CRC1_DATA_RG … #define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX … #define mmOTG5_OTG_CRC1_DATA_B … #define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX … #define mmOTG5_OTG_CRC2_DATA_RG … #define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX … #define mmOTG5_OTG_CRC2_DATA_B … #define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX … #define mmOTG5_OTG_CRC3_DATA_RG … #define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX … #define mmOTG5_OTG_CRC3_DATA_B … #define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX … #define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK … #define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmOTG5_OTG_STATIC_SCREEN_CONTROL … #define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmOTG5_OTG_3D_STRUCTURE_CONTROL … #define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmOTG5_OTG_GSL_VSYNC_GAP … #define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX … #define mmOTG5_OTG_MASTER_UPDATE_MODE … #define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define mmOTG5_OTG_CLOCK_CONTROL … #define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX … #define mmOTG5_OTG_VSTARTUP_PARAM … #define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX … #define mmOTG5_OTG_VUPDATE_PARAM … #define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX … #define mmOTG5_OTG_VREADY_PARAM … #define mmOTG5_OTG_VREADY_PARAM_BASE_IDX … #define mmOTG5_OTG_GLOBAL_SYNC_STATUS … #define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define mmOTG5_OTG_MASTER_UPDATE_LOCK … #define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define mmOTG5_OTG_GSL_CONTROL … #define mmOTG5_OTG_GSL_CONTROL_BASE_IDX … #define mmOTG5_OTG_GSL_WINDOW_X … #define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX … #define mmOTG5_OTG_GSL_WINDOW_Y … #define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX … #define mmOTG5_OTG_VUPDATE_KEEPOUT … #define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define mmOTG5_OTG_GLOBAL_CONTROL0 … #define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX … #define mmOTG5_OTG_GLOBAL_CONTROL1 … #define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX … #define mmOTG5_OTG_GLOBAL_CONTROL2 … #define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX … #define mmOTG5_OTG_GLOBAL_CONTROL3 … #define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX … #define mmOTG5_OTG_TRIG_MANUAL_CONTROL … #define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define mmOTG5_OTG_MANUAL_FLOW_CONTROL … #define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX … #define mmOTG5_OTG_RANGE_TIMING_INT_STATUS … #define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX … #define mmOTG5_OTG_DRR_CONTROL … #define mmOTG5_OTG_DRR_CONTROL_BASE_IDX … #define mmOTG5_OTG_REQUEST_CONTROL … #define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX … #define mmOTG5_OTG_SPARE_REGISTER … #define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_optc_misc_dispdec // base address: 0x0 #define mmDWB_SOURCE_SELECT … #define mmDWB_SOURCE_SELECT_BASE_IDX … #define mmGSL_SOURCE_SELECT … #define mmGSL_SOURCE_SELECT_BASE_IDX … #define mmOPTC_CLOCK_CONTROL … #define mmOPTC_CLOCK_CONTROL_BASE_IDX … #define mmOPTC_MISC_SPARE_REGISTER … #define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX … // addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec // base address: 0x79a8 #define mmDC_PERFMON18_PERFCOUNTER_CNTL … #define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON18_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON18_PERFCOUNTER_STATE … #define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON18_PERFMON_CNTL … #define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON18_PERFMON_CNTL2 … #define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON18_PERFMON_CVALUE_LOW … #define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON18_PERFMON_HI … #define mmDC_PERFMON18_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON18_PERFMON_LOW … #define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dio_dac_dispdec // base address: 0x0 #define mmDAC_ENABLE … #define mmDAC_ENABLE_BASE_IDX … #define mmDAC_SOURCE_SELECT … #define mmDAC_SOURCE_SELECT_BASE_IDX … #define mmDAC_CRC_EN … #define mmDAC_CRC_EN_BASE_IDX … #define mmDAC_CRC_CONTROL … #define mmDAC_CRC_CONTROL_BASE_IDX … #define mmDAC_CRC_SIG_RGB_MASK … #define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX … #define mmDAC_CRC_SIG_CONTROL_MASK … #define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX … #define mmDAC_CRC_SIG_RGB … #define mmDAC_CRC_SIG_RGB_BASE_IDX … #define mmDAC_CRC_SIG_CONTROL … #define mmDAC_CRC_SIG_CONTROL_BASE_IDX … #define mmDAC_SYNC_TRISTATE_CONTROL … #define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX … #define mmDAC_STEREOSYNC_SELECT … #define mmDAC_STEREOSYNC_SELECT_BASE_IDX … #define mmDAC_AUTODETECT_CONTROL … #define mmDAC_AUTODETECT_CONTROL_BASE_IDX … #define mmDAC_AUTODETECT_CONTROL2 … #define mmDAC_AUTODETECT_CONTROL2_BASE_IDX … #define mmDAC_AUTODETECT_CONTROL3 … #define mmDAC_AUTODETECT_CONTROL3_BASE_IDX … #define mmDAC_AUTODETECT_STATUS … #define mmDAC_AUTODETECT_STATUS_BASE_IDX … #define mmDAC_AUTODETECT_INT_CONTROL … #define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX … #define mmDAC_FORCE_OUTPUT_CNTL … #define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX … #define mmDAC_FORCE_DATA … #define mmDAC_FORCE_DATA_BASE_IDX … #define mmDAC_POWERDOWN … #define mmDAC_POWERDOWN_BASE_IDX … #define mmDAC_CONTROL … #define mmDAC_CONTROL_BASE_IDX … #define mmDAC_COMPARATOR_ENABLE … #define mmDAC_COMPARATOR_ENABLE_BASE_IDX … #define mmDAC_COMPARATOR_OUTPUT … #define mmDAC_COMPARATOR_OUTPUT_BASE_IDX … #define mmDAC_PWR_CNTL … #define mmDAC_PWR_CNTL_BASE_IDX … #define mmDAC_DFT_CONFIG … #define mmDAC_DFT_CONFIG_BASE_IDX … #define mmDAC_FIFO_STATUS … #define mmDAC_FIFO_STATUS_BASE_IDX … // addressBlock: dce_dc_dio_dout_i2c_dispdec // base address: 0x0 #define mmDC_I2C_CONTROL … #define mmDC_I2C_CONTROL_BASE_IDX … #define mmDC_I2C_ARBITRATION … #define mmDC_I2C_ARBITRATION_BASE_IDX … #define mmDC_I2C_INTERRUPT_CONTROL … #define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX … #define mmDC_I2C_SW_STATUS … #define mmDC_I2C_SW_STATUS_BASE_IDX … #define mmDC_I2C_DDC1_HW_STATUS … #define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC2_HW_STATUS … #define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC3_HW_STATUS … #define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC4_HW_STATUS … #define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC5_HW_STATUS … #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC6_HW_STATUS … #define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC1_SPEED … #define mmDC_I2C_DDC1_SPEED_BASE_IDX … #define mmDC_I2C_DDC1_SETUP … #define mmDC_I2C_DDC1_SETUP_BASE_IDX … #define mmDC_I2C_DDC2_SPEED … #define mmDC_I2C_DDC2_SPEED_BASE_IDX … #define mmDC_I2C_DDC2_SETUP … #define mmDC_I2C_DDC2_SETUP_BASE_IDX … #define mmDC_I2C_DDC3_SPEED … #define mmDC_I2C_DDC3_SPEED_BASE_IDX … #define mmDC_I2C_DDC3_SETUP … #define mmDC_I2C_DDC3_SETUP_BASE_IDX … #define mmDC_I2C_DDC4_SPEED … #define mmDC_I2C_DDC4_SPEED_BASE_IDX … #define mmDC_I2C_DDC4_SETUP … #define mmDC_I2C_DDC4_SETUP_BASE_IDX … #define mmDC_I2C_DDC5_SPEED … #define mmDC_I2C_DDC5_SPEED_BASE_IDX … #define mmDC_I2C_DDC5_SETUP … #define mmDC_I2C_DDC5_SETUP_BASE_IDX … #define mmDC_I2C_DDC6_SPEED … #define mmDC_I2C_DDC6_SPEED_BASE_IDX … #define mmDC_I2C_DDC6_SETUP … #define mmDC_I2C_DDC6_SETUP_BASE_IDX … #define mmDC_I2C_TRANSACTION0 … #define mmDC_I2C_TRANSACTION0_BASE_IDX … #define mmDC_I2C_TRANSACTION1 … #define mmDC_I2C_TRANSACTION1_BASE_IDX … #define mmDC_I2C_TRANSACTION2 … #define mmDC_I2C_TRANSACTION2_BASE_IDX … #define mmDC_I2C_TRANSACTION3 … #define mmDC_I2C_TRANSACTION3_BASE_IDX … #define mmDC_I2C_DATA … #define mmDC_I2C_DATA_BASE_IDX … #define mmDC_I2C_DDCVGA_HW_STATUS … #define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDCVGA_SPEED … #define mmDC_I2C_DDCVGA_SPEED_BASE_IDX … #define mmDC_I2C_DDCVGA_SETUP … #define mmDC_I2C_DDCVGA_SETUP_BASE_IDX … #define mmDC_I2C_EDID_DETECT_CTRL … #define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX … #define mmDC_I2C_READ_REQUEST_INTERRUPT … #define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX … // addressBlock: dce_dc_dio_generic_i2c_dispdec // base address: 0x0 #define mmGENERIC_I2C_CONTROL … #define mmGENERIC_I2C_CONTROL_BASE_IDX … #define mmGENERIC_I2C_INTERRUPT_CONTROL … #define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX … #define mmGENERIC_I2C_STATUS … #define mmGENERIC_I2C_STATUS_BASE_IDX … #define mmGENERIC_I2C_SPEED … #define mmGENERIC_I2C_SPEED_BASE_IDX … #define mmGENERIC_I2C_SETUP … #define mmGENERIC_I2C_SETUP_BASE_IDX … #define mmGENERIC_I2C_TRANSACTION … #define mmGENERIC_I2C_TRANSACTION_BASE_IDX … #define mmGENERIC_I2C_DATA … #define mmGENERIC_I2C_DATA_BASE_IDX … #define mmGENERIC_I2C_PIN_SELECTION … #define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX … // addressBlock: dce_dc_dio_dio_misc_dispdec // base address: 0x0 #define mmDIO_SCRATCH0 … #define mmDIO_SCRATCH0_BASE_IDX … #define mmDIO_SCRATCH1 … #define mmDIO_SCRATCH1_BASE_IDX … #define mmDIO_SCRATCH2 … #define mmDIO_SCRATCH2_BASE_IDX … #define mmDIO_SCRATCH3 … #define mmDIO_SCRATCH3_BASE_IDX … #define mmDIO_SCRATCH4 … #define mmDIO_SCRATCH4_BASE_IDX … #define mmDIO_SCRATCH5 … #define mmDIO_SCRATCH5_BASE_IDX … #define mmDIO_SCRATCH6 … #define mmDIO_SCRATCH6_BASE_IDX … #define mmDIO_SCRATCH7 … #define mmDIO_SCRATCH7_BASE_IDX … #define mmDCE_VCE_CONTROL … #define mmDCE_VCE_CONTROL_BASE_IDX … #define mmDIO_MEM_PWR_STATUS … #define mmDIO_MEM_PWR_STATUS_BASE_IDX … #define mmDIO_MEM_PWR_CTRL … #define mmDIO_MEM_PWR_CTRL_BASE_IDX … #define mmDIO_MEM_PWR_CTRL2 … #define mmDIO_MEM_PWR_CTRL2_BASE_IDX … #define mmDIO_CLK_CNTL … #define mmDIO_CLK_CNTL_BASE_IDX … #define mmDIO_POWER_MANAGEMENT_CNTL … #define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX … #define mmDIO_STEREOSYNC_SEL … #define mmDIO_STEREOSYNC_SEL_BASE_IDX … #define mmDIO_SOFT_RESET … #define mmDIO_SOFT_RESET_BASE_IDX … #define mmDIG_SOFT_RESET … #define mmDIG_SOFT_RESET_BASE_IDX … #define mmDIO_MEM_PWR_STATUS1 … #define mmDIO_MEM_PWR_STATUS1_BASE_IDX … #define mmDIO_CLK_CNTL2 … #define mmDIO_CLK_CNTL2_BASE_IDX … #define mmDIO_CLK_CNTL3 … #define mmDIO_CLK_CNTL3_BASE_IDX … #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL … #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX … #define mmDIO_PSP_INTERRUPT_STATUS … #define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX … #define mmDIO_PSP_INTERRUPT_CLEAR … #define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX … #define mmDIO_GENERIC_INTERRUPT_MESSAGE … #define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX … #define mmDIO_GENERIC_INTERRUPT_CLEAR … #define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX … // addressBlock: dce_dc_dio_hpd0_dispdec // base address: 0x0 #define mmHPD0_DC_HPD_INT_STATUS … #define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD0_DC_HPD_INT_CONTROL … #define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD0_DC_HPD_CONTROL … #define mmHPD0_DC_HPD_CONTROL_BASE_IDX … #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_dio_hpd1_dispdec // base address: 0x20 #define mmHPD1_DC_HPD_INT_STATUS … #define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD1_DC_HPD_INT_CONTROL … #define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD1_DC_HPD_CONTROL … #define mmHPD1_DC_HPD_CONTROL_BASE_IDX … #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_dio_hpd2_dispdec // base address: 0x40 #define mmHPD2_DC_HPD_INT_STATUS … #define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD2_DC_HPD_INT_CONTROL … #define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD2_DC_HPD_CONTROL … #define mmHPD2_DC_HPD_CONTROL_BASE_IDX … #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_dio_hpd3_dispdec // base address: 0x60 #define mmHPD3_DC_HPD_INT_STATUS … #define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD3_DC_HPD_INT_CONTROL … #define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD3_DC_HPD_CONTROL … #define mmHPD3_DC_HPD_CONTROL_BASE_IDX … #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_dio_hpd4_dispdec // base address: 0x80 #define mmHPD4_DC_HPD_INT_STATUS … #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD4_DC_HPD_INT_CONTROL … #define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD4_DC_HPD_CONTROL … #define mmHPD4_DC_HPD_CONTROL_BASE_IDX … #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_dio_hpd5_dispdec // base address: 0xa0 #define mmHPD5_DC_HPD_INT_STATUS … #define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD5_DC_HPD_INT_CONTROL … #define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD5_DC_HPD_CONTROL … #define mmHPD5_DC_HPD_CONTROL_BASE_IDX … #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec // base address: 0x7d10 #define mmDC_PERFMON19_PERFCOUNTER_CNTL … #define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX … #define mmDC_PERFMON19_PERFCOUNTER_CNTL2 … #define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX … #define mmDC_PERFMON19_PERFCOUNTER_STATE … #define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX … #define mmDC_PERFMON19_PERFMON_CNTL … #define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX … #define mmDC_PERFMON19_PERFMON_CNTL2 … #define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX … #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC … #define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX … #define mmDC_PERFMON19_PERFMON_CVALUE_LOW … #define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX … #define mmDC_PERFMON19_PERFMON_HI … #define mmDC_PERFMON19_PERFMON_HI_BASE_IDX … #define mmDC_PERFMON19_PERFMON_LOW … #define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX … // addressBlock: dce_dc_dio_dp_aux0_dispdec // base address: 0x0 #define mmDP_AUX0_AUX_CONTROL … #define mmDP_AUX0_AUX_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_SW_CONTROL … #define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_ARB_CONTROL … #define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_INTERRUPT_CONTROL … #define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_SW_STATUS … #define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_LS_STATUS … #define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_SW_DATA … #define mmDP_AUX0_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX0_AUX_LS_DATA … #define mmDP_AUX0_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_TX_CONTROL … #define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_TX_STATUS … #define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_RX_STATUS … #define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_GTC_SYNC_STATUS … #define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dio_dp_aux1_dispdec // base address: 0x70 #define mmDP_AUX1_AUX_CONTROL … #define mmDP_AUX1_AUX_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_SW_CONTROL … #define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_ARB_CONTROL … #define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_INTERRUPT_CONTROL … #define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_SW_STATUS … #define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_LS_STATUS … #define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_SW_DATA … #define mmDP_AUX1_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX1_AUX_LS_DATA … #define mmDP_AUX1_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_TX_CONTROL … #define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_TX_STATUS … #define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_RX_STATUS … #define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_GTC_SYNC_STATUS … #define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dio_dp_aux2_dispdec // base address: 0xe0 #define mmDP_AUX2_AUX_CONTROL … #define mmDP_AUX2_AUX_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_SW_CONTROL … #define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_ARB_CONTROL … #define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_INTERRUPT_CONTROL … #define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_SW_STATUS … #define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX2_AUX_LS_STATUS … #define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX2_AUX_SW_DATA … #define mmDP_AUX2_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX2_AUX_LS_DATA … #define mmDP_AUX2_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_TX_CONTROL … #define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_TX_STATUS … #define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX2_AUX_DPHY_RX_STATUS … #define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX2_AUX_GTC_SYNC_STATUS … #define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dio_dp_aux3_dispdec // base address: 0x150 #define mmDP_AUX3_AUX_CONTROL … #define mmDP_AUX3_AUX_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_SW_CONTROL … #define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_ARB_CONTROL … #define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_INTERRUPT_CONTROL … #define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_SW_STATUS … #define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX3_AUX_LS_STATUS … #define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX3_AUX_SW_DATA … #define mmDP_AUX3_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX3_AUX_LS_DATA … #define mmDP_AUX3_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_TX_CONTROL … #define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_TX_STATUS … #define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX3_AUX_DPHY_RX_STATUS … #define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX3_AUX_GTC_SYNC_STATUS … #define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dio_dp_aux4_dispdec // base address: 0x1c0 #define mmDP_AUX4_AUX_CONTROL … #define mmDP_AUX4_AUX_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_SW_CONTROL … #define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_ARB_CONTROL … #define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_INTERRUPT_CONTROL … #define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_SW_STATUS … #define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX4_AUX_LS_STATUS … #define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX4_AUX_SW_DATA … #define mmDP_AUX4_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX4_AUX_LS_DATA … #define mmDP_AUX4_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_TX_CONTROL … #define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_TX_STATUS … #define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX4_AUX_DPHY_RX_STATUS … #define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX4_AUX_GTC_SYNC_STATUS … #define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dio_dp_aux5_dispdec // base address: 0x230 #define mmDP_AUX5_AUX_CONTROL … #define mmDP_AUX5_AUX_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_SW_CONTROL … #define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_ARB_CONTROL … #define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_INTERRUPT_CONTROL … #define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_SW_STATUS … #define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX5_AUX_LS_STATUS … #define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX5_AUX_SW_DATA … #define mmDP_AUX5_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX5_AUX_LS_DATA … #define mmDP_AUX5_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_TX_CONTROL … #define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_TX_STATUS … #define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX5_AUX_DPHY_RX_STATUS … #define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX5_AUX_GTC_SYNC_STATUS … #define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dio_dp_aux6_dispdec // base address: 0x2a0 #define mmDP_AUX6_AUX_CONTROL … #define mmDP_AUX6_AUX_CONTROL_BASE_IDX … #define mmDP_AUX6_AUX_SW_CONTROL … #define mmDP_AUX6_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX6_AUX_ARB_CONTROL … #define mmDP_AUX6_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX6_AUX_INTERRUPT_CONTROL … #define mmDP_AUX6_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX6_AUX_SW_STATUS … #define mmDP_AUX6_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX6_AUX_LS_STATUS … #define mmDP_AUX6_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX6_AUX_SW_DATA … #define mmDP_AUX6_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX6_AUX_LS_DATA … #define mmDP_AUX6_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX6_AUX_DPHY_TX_CONTROL … #define mmDP_AUX6_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX6_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX6_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX6_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX6_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX6_AUX_DPHY_TX_STATUS … #define mmDP_AUX6_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX6_AUX_DPHY_RX_STATUS … #define mmDP_AUX6_AUX_DPHY_RX_STATUS_BASE_IDX … #define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL … #define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX … #define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS … #define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX … #define mmDP_AUX6_AUX_GTC_SYNC_STATUS … #define mmDP_AUX6_AUX_GTC_SYNC_STATUS_BASE_IDX … // addressBlock: dce_dc_dio_dig0_dispdec // base address: 0x0 #define mmDIG0_DIG_FE_CNTL … #define mmDIG0_DIG_FE_CNTL_BASE_IDX … #define mmDIG0_DIG_OUTPUT_CRC_CNTL … #define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG0_DIG_OUTPUT_CRC_RESULT … #define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG0_DIG_CLOCK_PATTERN … #define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG0_DIG_TEST_PATTERN … #define mmDIG0_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG0_DIG_RANDOM_PATTERN_SEED … #define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG0_DIG_FIFO_STATUS … #define mmDIG0_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG0_HDMI_CONTROL … #define mmDIG0_HDMI_CONTROL_BASE_IDX … #define mmDIG0_HDMI_STATUS … #define mmDIG0_HDMI_STATUS_BASE_IDX … #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG0_HDMI_ACR_PACKET_CONTROL … #define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG0_HDMI_VBI_PACKET_CONTROL … #define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG0_HDMI_INFOFRAME_CONTROL0 … #define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG0_HDMI_INFOFRAME_CONTROL1 … #define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG0_AFMT_INTERRUPT_STATUS … #define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG0_HDMI_GC … #define mmDIG0_HDMI_GC_BASE_IDX … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG0_AFMT_ISRC1_0 … #define mmDIG0_AFMT_ISRC1_0_BASE_IDX … #define mmDIG0_AFMT_ISRC1_1 … #define mmDIG0_AFMT_ISRC1_1_BASE_IDX … #define mmDIG0_AFMT_ISRC1_2 … #define mmDIG0_AFMT_ISRC1_2_BASE_IDX … #define mmDIG0_AFMT_ISRC1_3 … #define mmDIG0_AFMT_ISRC1_3_BASE_IDX … #define mmDIG0_AFMT_ISRC1_4 … #define mmDIG0_AFMT_ISRC1_4_BASE_IDX … #define mmDIG0_AFMT_ISRC2_0 … #define mmDIG0_AFMT_ISRC2_0_BASE_IDX … #define mmDIG0_AFMT_ISRC2_1 … #define mmDIG0_AFMT_ISRC2_1_BASE_IDX … #define mmDIG0_AFMT_ISRC2_2 … #define mmDIG0_AFMT_ISRC2_2_BASE_IDX … #define mmDIG0_AFMT_ISRC2_3 … #define mmDIG0_AFMT_ISRC2_3_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define mmDIG0_HDMI_DB_CONTROL … #define mmDIG0_HDMI_DB_CONTROL_BASE_IDX … #define mmDIG0_AFMT_MPEG_INFO0 … #define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG0_AFMT_MPEG_INFO1 … #define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG0_AFMT_GENERIC_HDR … #define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG0_AFMT_GENERIC_0 … #define mmDIG0_AFMT_GENERIC_0_BASE_IDX … #define mmDIG0_AFMT_GENERIC_1 … #define mmDIG0_AFMT_GENERIC_1_BASE_IDX … #define mmDIG0_AFMT_GENERIC_2 … #define mmDIG0_AFMT_GENERIC_2_BASE_IDX … #define mmDIG0_AFMT_GENERIC_3 … #define mmDIG0_AFMT_GENERIC_3_BASE_IDX … #define mmDIG0_AFMT_GENERIC_4 … #define mmDIG0_AFMT_GENERIC_4_BASE_IDX … #define mmDIG0_AFMT_GENERIC_5 … #define mmDIG0_AFMT_GENERIC_5_BASE_IDX … #define mmDIG0_AFMT_GENERIC_6 … #define mmDIG0_AFMT_GENERIC_6_BASE_IDX … #define mmDIG0_AFMT_GENERIC_7 … #define mmDIG0_AFMT_GENERIC_7_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG0_HDMI_ACR_32_0 … #define mmDIG0_HDMI_ACR_32_0_BASE_IDX … #define mmDIG0_HDMI_ACR_32_1 … #define mmDIG0_HDMI_ACR_32_1_BASE_IDX … #define mmDIG0_HDMI_ACR_44_0 … #define mmDIG0_HDMI_ACR_44_0_BASE_IDX … #define mmDIG0_HDMI_ACR_44_1 … #define mmDIG0_HDMI_ACR_44_1_BASE_IDX … #define mmDIG0_HDMI_ACR_48_0 … #define mmDIG0_HDMI_ACR_48_0_BASE_IDX … #define mmDIG0_HDMI_ACR_48_1 … #define mmDIG0_HDMI_ACR_48_1_BASE_IDX … #define mmDIG0_HDMI_ACR_STATUS_0 … #define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG0_HDMI_ACR_STATUS_1 … #define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG0_AFMT_AUDIO_INFO0 … #define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG0_AFMT_AUDIO_INFO1 … #define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG0_AFMT_60958_0 … #define mmDIG0_AFMT_60958_0_BASE_IDX … #define mmDIG0_AFMT_60958_1 … #define mmDIG0_AFMT_60958_1_BASE_IDX … #define mmDIG0_AFMT_AUDIO_CRC_CONTROL … #define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL0 … #define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL1 … #define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL2 … #define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL3 … #define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG0_AFMT_60958_2 … #define mmDIG0_AFMT_60958_2_BASE_IDX … #define mmDIG0_AFMT_AUDIO_CRC_RESULT … #define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG0_AFMT_STATUS … #define mmDIG0_AFMT_STATUS_BASE_IDX … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG0_AFMT_VBI_PACKET_CONTROL … #define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG0_AFMT_INFOFRAME_CONTROL0 … #define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG0_AFMT_AUDIO_SRC_CONTROL … #define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG0_DIG_BE_CNTL … #define mmDIG0_DIG_BE_CNTL_BASE_IDX … #define mmDIG0_DIG_BE_EN_CNTL … #define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG0_TMDS_CNTL … #define mmDIG0_TMDS_CNTL_BASE_IDX … #define mmDIG0_TMDS_CONTROL_CHAR … #define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG0_TMDS_CONTROL0_FEEDBACK … #define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG0_TMDS_CTL_BITS … #define mmDIG0_TMDS_CTL_BITS_BASE_IDX … #define mmDIG0_TMDS_DCBALANCER_CONTROL … #define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG0_TMDS_CTL2_3_GEN_CNTL … #define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG0_DIG_VERSION … #define mmDIG0_DIG_VERSION_BASE_IDX … #define mmDIG0_DIG_LANE_ENABLE … #define mmDIG0_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG0_AFMT_CNTL … #define mmDIG0_AFMT_CNTL_BASE_IDX … #define mmDIG0_AFMT_VBI_PACKET_CONTROL1 … #define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX … // addressBlock: dce_dc_dio_dp0_dispdec // base address: 0x0 #define mmDP0_DP_LINK_CNTL … #define mmDP0_DP_LINK_CNTL_BASE_IDX … #define mmDP0_DP_PIXEL_FORMAT … #define mmDP0_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP0_DP_MSA_COLORIMETRY … #define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP0_DP_CONFIG … #define mmDP0_DP_CONFIG_BASE_IDX … #define mmDP0_DP_VID_STREAM_CNTL … #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP0_DP_STEER_FIFO … #define mmDP0_DP_STEER_FIFO_BASE_IDX … #define mmDP0_DP_MSA_MISC … #define mmDP0_DP_MSA_MISC_BASE_IDX … #define mmDP0_DP_VID_TIMING … #define mmDP0_DP_VID_TIMING_BASE_IDX … #define mmDP0_DP_VID_N … #define mmDP0_DP_VID_N_BASE_IDX … #define mmDP0_DP_VID_M … #define mmDP0_DP_VID_M_BASE_IDX … #define mmDP0_DP_LINK_FRAMING_CNTL … #define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP0_DP_HBR2_EYE_PATTERN … #define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP0_DP_VID_MSA_VBID … #define mmDP0_DP_VID_MSA_VBID_BASE_IDX … #define mmDP0_DP_VID_INTERRUPT_CNTL … #define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CNTL … #define mmDP0_DP_DPHY_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP0_DP_DPHY_SYM0 … #define mmDP0_DP_DPHY_SYM0_BASE_IDX … #define mmDP0_DP_DPHY_SYM1 … #define mmDP0_DP_DPHY_SYM1_BASE_IDX … #define mmDP0_DP_DPHY_SYM2 … #define mmDP0_DP_DPHY_SYM2_BASE_IDX … #define mmDP0_DP_DPHY_8B10B_CNTL … #define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_PRBS_CNTL … #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_SCRAM_CNTL … #define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CRC_EN … #define mmDP0_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP0_DP_DPHY_CRC_CNTL … #define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CRC_RESULT … #define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP0_DP_DPHY_CRC_MST_CNTL … #define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CRC_MST_STATUS … #define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP0_DP_DPHY_FAST_TRAINING … #define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP0_DP_SEC_CNTL … #define mmDP0_DP_SEC_CNTL_BASE_IDX … #define mmDP0_DP_SEC_CNTL1 … #define mmDP0_DP_SEC_CNTL1_BASE_IDX … #define mmDP0_DP_SEC_FRAMING1 … #define mmDP0_DP_SEC_FRAMING1_BASE_IDX … #define mmDP0_DP_SEC_FRAMING2 … #define mmDP0_DP_SEC_FRAMING2_BASE_IDX … #define mmDP0_DP_SEC_FRAMING3 … #define mmDP0_DP_SEC_FRAMING3_BASE_IDX … #define mmDP0_DP_SEC_FRAMING4 … #define mmDP0_DP_SEC_FRAMING4_BASE_IDX … #define mmDP0_DP_SEC_AUD_N … #define mmDP0_DP_SEC_AUD_N_BASE_IDX … #define mmDP0_DP_SEC_AUD_N_READBACK … #define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP0_DP_SEC_AUD_M … #define mmDP0_DP_SEC_AUD_M_BASE_IDX … #define mmDP0_DP_SEC_AUD_M_READBACK … #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP0_DP_SEC_TIMESTAMP … #define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP0_DP_SEC_PACKET_CNTL … #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP0_DP_MSE_RATE_CNTL … #define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP0_DP_MSE_RATE_UPDATE … #define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP0_DP_MSE_SAT0 … #define mmDP0_DP_MSE_SAT0_BASE_IDX … #define mmDP0_DP_MSE_SAT1 … #define mmDP0_DP_MSE_SAT1_BASE_IDX … #define mmDP0_DP_MSE_SAT2 … #define mmDP0_DP_MSE_SAT2_BASE_IDX … #define mmDP0_DP_MSE_SAT_UPDATE … #define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP0_DP_MSE_LINK_TIMING … #define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP0_DP_MSE_MISC_CNTL … #define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP0_DP_MSE_SAT0_STATUS … #define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP0_DP_MSE_SAT1_STATUS … #define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP0_DP_MSE_SAT2_STATUS … #define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX … #define mmDP0_DP_MSA_TIMING_PARAM1 … #define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX … #define mmDP0_DP_MSA_TIMING_PARAM2 … #define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX … #define mmDP0_DP_MSA_TIMING_PARAM3 … #define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX … #define mmDP0_DP_MSA_TIMING_PARAM4 … #define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … #define mmDP0_DP_MSO_CNTL … #define mmDP0_DP_MSO_CNTL_BASE_IDX … #define mmDP0_DP_MSO_CNTL1 … #define mmDP0_DP_MSO_CNTL1_BASE_IDX … #define mmDP0_DP_DSC_CNTL … #define mmDP0_DP_DSC_CNTL_BASE_IDX … #define mmDP0_DP_SEC_CNTL2 … #define mmDP0_DP_SEC_CNTL2_BASE_IDX … #define mmDP0_DP_SEC_CNTL3 … #define mmDP0_DP_SEC_CNTL3_BASE_IDX … #define mmDP0_DP_SEC_CNTL4 … #define mmDP0_DP_SEC_CNTL4_BASE_IDX … #define mmDP0_DP_SEC_CNTL5 … #define mmDP0_DP_SEC_CNTL5_BASE_IDX … #define mmDP0_DP_SEC_CNTL6 … #define mmDP0_DP_SEC_CNTL6_BASE_IDX … #define mmDP0_DP_SEC_CNTL7 … #define mmDP0_DP_SEC_CNTL7_BASE_IDX … #define mmDP0_DP_DB_CNTL … #define mmDP0_DP_DB_CNTL_BASE_IDX … #define mmDP0_DP_MSA_VBID_MISC … #define mmDP0_DP_MSA_VBID_MISC_BASE_IDX … // addressBlock: dce_dc_dio_dig1_dispdec // base address: 0x400 #define mmDIG1_DIG_FE_CNTL … #define mmDIG1_DIG_FE_CNTL_BASE_IDX … #define mmDIG1_DIG_OUTPUT_CRC_CNTL … #define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG1_DIG_OUTPUT_CRC_RESULT … #define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG1_DIG_CLOCK_PATTERN … #define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG1_DIG_TEST_PATTERN … #define mmDIG1_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG1_DIG_RANDOM_PATTERN_SEED … #define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG1_DIG_FIFO_STATUS … #define mmDIG1_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG1_HDMI_CONTROL … #define mmDIG1_HDMI_CONTROL_BASE_IDX … #define mmDIG1_HDMI_STATUS … #define mmDIG1_HDMI_STATUS_BASE_IDX … #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG1_HDMI_ACR_PACKET_CONTROL … #define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG1_HDMI_VBI_PACKET_CONTROL … #define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG1_HDMI_INFOFRAME_CONTROL0 … #define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG1_HDMI_INFOFRAME_CONTROL1 … #define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG1_AFMT_INTERRUPT_STATUS … #define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG1_HDMI_GC … #define mmDIG1_HDMI_GC_BASE_IDX … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG1_AFMT_ISRC1_0 … #define mmDIG1_AFMT_ISRC1_0_BASE_IDX … #define mmDIG1_AFMT_ISRC1_1 … #define mmDIG1_AFMT_ISRC1_1_BASE_IDX … #define mmDIG1_AFMT_ISRC1_2 … #define mmDIG1_AFMT_ISRC1_2_BASE_IDX … #define mmDIG1_AFMT_ISRC1_3 … #define mmDIG1_AFMT_ISRC1_3_BASE_IDX … #define mmDIG1_AFMT_ISRC1_4 … #define mmDIG1_AFMT_ISRC1_4_BASE_IDX … #define mmDIG1_AFMT_ISRC2_0 … #define mmDIG1_AFMT_ISRC2_0_BASE_IDX … #define mmDIG1_AFMT_ISRC2_1 … #define mmDIG1_AFMT_ISRC2_1_BASE_IDX … #define mmDIG1_AFMT_ISRC2_2 … #define mmDIG1_AFMT_ISRC2_2_BASE_IDX … #define mmDIG1_AFMT_ISRC2_3 … #define mmDIG1_AFMT_ISRC2_3_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define mmDIG1_HDMI_DB_CONTROL … #define mmDIG1_HDMI_DB_CONTROL_BASE_IDX … #define mmDIG1_AFMT_MPEG_INFO0 … #define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG1_AFMT_MPEG_INFO1 … #define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG1_AFMT_GENERIC_HDR … #define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG1_AFMT_GENERIC_0 … #define mmDIG1_AFMT_GENERIC_0_BASE_IDX … #define mmDIG1_AFMT_GENERIC_1 … #define mmDIG1_AFMT_GENERIC_1_BASE_IDX … #define mmDIG1_AFMT_GENERIC_2 … #define mmDIG1_AFMT_GENERIC_2_BASE_IDX … #define mmDIG1_AFMT_GENERIC_3 … #define mmDIG1_AFMT_GENERIC_3_BASE_IDX … #define mmDIG1_AFMT_GENERIC_4 … #define mmDIG1_AFMT_GENERIC_4_BASE_IDX … #define mmDIG1_AFMT_GENERIC_5 … #define mmDIG1_AFMT_GENERIC_5_BASE_IDX … #define mmDIG1_AFMT_GENERIC_6 … #define mmDIG1_AFMT_GENERIC_6_BASE_IDX … #define mmDIG1_AFMT_GENERIC_7 … #define mmDIG1_AFMT_GENERIC_7_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG1_HDMI_ACR_32_0 … #define mmDIG1_HDMI_ACR_32_0_BASE_IDX … #define mmDIG1_HDMI_ACR_32_1 … #define mmDIG1_HDMI_ACR_32_1_BASE_IDX … #define mmDIG1_HDMI_ACR_44_0 … #define mmDIG1_HDMI_ACR_44_0_BASE_IDX … #define mmDIG1_HDMI_ACR_44_1 … #define mmDIG1_HDMI_ACR_44_1_BASE_IDX … #define mmDIG1_HDMI_ACR_48_0 … #define mmDIG1_HDMI_ACR_48_0_BASE_IDX … #define mmDIG1_HDMI_ACR_48_1 … #define mmDIG1_HDMI_ACR_48_1_BASE_IDX … #define mmDIG1_HDMI_ACR_STATUS_0 … #define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG1_HDMI_ACR_STATUS_1 … #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG1_AFMT_AUDIO_INFO0 … #define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG1_AFMT_AUDIO_INFO1 … #define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG1_AFMT_60958_0 … #define mmDIG1_AFMT_60958_0_BASE_IDX … #define mmDIG1_AFMT_60958_1 … #define mmDIG1_AFMT_60958_1_BASE_IDX … #define mmDIG1_AFMT_AUDIO_CRC_CONTROL … #define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL0 … #define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL1 … #define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL2 … #define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL3 … #define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG1_AFMT_60958_2 … #define mmDIG1_AFMT_60958_2_BASE_IDX … #define mmDIG1_AFMT_AUDIO_CRC_RESULT … #define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG1_AFMT_STATUS … #define mmDIG1_AFMT_STATUS_BASE_IDX … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG1_AFMT_VBI_PACKET_CONTROL … #define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG1_AFMT_INFOFRAME_CONTROL0 … #define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG1_AFMT_AUDIO_SRC_CONTROL … #define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG1_DIG_BE_CNTL … #define mmDIG1_DIG_BE_CNTL_BASE_IDX … #define mmDIG1_DIG_BE_EN_CNTL … #define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG1_TMDS_CNTL … #define mmDIG1_TMDS_CNTL_BASE_IDX … #define mmDIG1_TMDS_CONTROL_CHAR … #define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG1_TMDS_CONTROL0_FEEDBACK … #define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG1_TMDS_CTL_BITS … #define mmDIG1_TMDS_CTL_BITS_BASE_IDX … #define mmDIG1_TMDS_DCBALANCER_CONTROL … #define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG1_TMDS_CTL0_1_GEN_CNTL … #define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG1_TMDS_CTL2_3_GEN_CNTL … #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG1_DIG_VERSION … #define mmDIG1_DIG_VERSION_BASE_IDX … #define mmDIG1_DIG_LANE_ENABLE … #define mmDIG1_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG1_AFMT_CNTL … #define mmDIG1_AFMT_CNTL_BASE_IDX … #define mmDIG1_AFMT_VBI_PACKET_CONTROL1 … #define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX … // addressBlock: dce_dc_dio_dp1_dispdec // base address: 0x400 #define mmDP1_DP_LINK_CNTL … #define mmDP1_DP_LINK_CNTL_BASE_IDX … #define mmDP1_DP_PIXEL_FORMAT … #define mmDP1_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP1_DP_MSA_COLORIMETRY … #define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP1_DP_CONFIG … #define mmDP1_DP_CONFIG_BASE_IDX … #define mmDP1_DP_VID_STREAM_CNTL … #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP1_DP_STEER_FIFO … #define mmDP1_DP_STEER_FIFO_BASE_IDX … #define mmDP1_DP_MSA_MISC … #define mmDP1_DP_MSA_MISC_BASE_IDX … #define mmDP1_DP_VID_TIMING … #define mmDP1_DP_VID_TIMING_BASE_IDX … #define mmDP1_DP_VID_N … #define mmDP1_DP_VID_N_BASE_IDX … #define mmDP1_DP_VID_M … #define mmDP1_DP_VID_M_BASE_IDX … #define mmDP1_DP_LINK_FRAMING_CNTL … #define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP1_DP_HBR2_EYE_PATTERN … #define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP1_DP_VID_MSA_VBID … #define mmDP1_DP_VID_MSA_VBID_BASE_IDX … #define mmDP1_DP_VID_INTERRUPT_CNTL … #define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CNTL … #define mmDP1_DP_DPHY_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP1_DP_DPHY_SYM0 … #define mmDP1_DP_DPHY_SYM0_BASE_IDX … #define mmDP1_DP_DPHY_SYM1 … #define mmDP1_DP_DPHY_SYM1_BASE_IDX … #define mmDP1_DP_DPHY_SYM2 … #define mmDP1_DP_DPHY_SYM2_BASE_IDX … #define mmDP1_DP_DPHY_8B10B_CNTL … #define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_PRBS_CNTL … #define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_SCRAM_CNTL … #define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CRC_EN … #define mmDP1_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP1_DP_DPHY_CRC_CNTL … #define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CRC_RESULT … #define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP1_DP_DPHY_CRC_MST_CNTL … #define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CRC_MST_STATUS … #define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP1_DP_DPHY_FAST_TRAINING … #define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP1_DP_SEC_CNTL … #define mmDP1_DP_SEC_CNTL_BASE_IDX … #define mmDP1_DP_SEC_CNTL1 … #define mmDP1_DP_SEC_CNTL1_BASE_IDX … #define mmDP1_DP_SEC_FRAMING1 … #define mmDP1_DP_SEC_FRAMING1_BASE_IDX … #define mmDP1_DP_SEC_FRAMING2 … #define mmDP1_DP_SEC_FRAMING2_BASE_IDX … #define mmDP1_DP_SEC_FRAMING3 … #define mmDP1_DP_SEC_FRAMING3_BASE_IDX … #define mmDP1_DP_SEC_FRAMING4 … #define mmDP1_DP_SEC_FRAMING4_BASE_IDX … #define mmDP1_DP_SEC_AUD_N … #define mmDP1_DP_SEC_AUD_N_BASE_IDX … #define mmDP1_DP_SEC_AUD_N_READBACK … #define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP1_DP_SEC_AUD_M … #define mmDP1_DP_SEC_AUD_M_BASE_IDX … #define mmDP1_DP_SEC_AUD_M_READBACK … #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP1_DP_SEC_TIMESTAMP … #define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP1_DP_SEC_PACKET_CNTL … #define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP1_DP_MSE_RATE_CNTL … #define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP1_DP_MSE_RATE_UPDATE … #define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP1_DP_MSE_SAT0 … #define mmDP1_DP_MSE_SAT0_BASE_IDX … #define mmDP1_DP_MSE_SAT1 … #define mmDP1_DP_MSE_SAT1_BASE_IDX … #define mmDP1_DP_MSE_SAT2 … #define mmDP1_DP_MSE_SAT2_BASE_IDX … #define mmDP1_DP_MSE_SAT_UPDATE … #define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP1_DP_MSE_LINK_TIMING … #define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP1_DP_MSE_MISC_CNTL … #define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP1_DP_MSE_SAT0_STATUS … #define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP1_DP_MSE_SAT1_STATUS … #define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP1_DP_MSE_SAT2_STATUS … #define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX … #define mmDP1_DP_MSA_TIMING_PARAM1 … #define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX … #define mmDP1_DP_MSA_TIMING_PARAM2 … #define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX … #define mmDP1_DP_MSA_TIMING_PARAM3 … #define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX … #define mmDP1_DP_MSA_TIMING_PARAM4 … #define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX … #define mmDP1_DP_MSO_CNTL … #define mmDP1_DP_MSO_CNTL_BASE_IDX … #define mmDP1_DP_MSO_CNTL1 … #define mmDP1_DP_MSO_CNTL1_BASE_IDX … #define mmDP1_DP_DSC_CNTL … #define mmDP1_DP_DSC_CNTL_BASE_IDX … #define mmDP1_DP_SEC_CNTL2 … #define mmDP1_DP_SEC_CNTL2_BASE_IDX … #define mmDP1_DP_SEC_CNTL3 … #define mmDP1_DP_SEC_CNTL3_BASE_IDX … #define mmDP1_DP_SEC_CNTL4 … #define mmDP1_DP_SEC_CNTL4_BASE_IDX … #define mmDP1_DP_SEC_CNTL5 … #define mmDP1_DP_SEC_CNTL5_BASE_IDX … #define mmDP1_DP_SEC_CNTL6 … #define mmDP1_DP_SEC_CNTL6_BASE_IDX … #define mmDP1_DP_SEC_CNTL7 … #define mmDP1_DP_SEC_CNTL7_BASE_IDX … #define mmDP1_DP_DB_CNTL … #define mmDP1_DP_DB_CNTL_BASE_IDX … #define mmDP1_DP_MSA_VBID_MISC … #define mmDP1_DP_MSA_VBID_MISC_BASE_IDX … // addressBlock: dce_dc_dio_dig2_dispdec // base address: 0x800 #define mmDIG2_DIG_FE_CNTL … #define mmDIG2_DIG_FE_CNTL_BASE_IDX … #define mmDIG2_DIG_OUTPUT_CRC_CNTL … #define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG2_DIG_OUTPUT_CRC_RESULT … #define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG2_DIG_CLOCK_PATTERN … #define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG2_DIG_TEST_PATTERN … #define mmDIG2_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG2_DIG_RANDOM_PATTERN_SEED … #define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG2_DIG_FIFO_STATUS … #define mmDIG2_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG2_HDMI_CONTROL … #define mmDIG2_HDMI_CONTROL_BASE_IDX … #define mmDIG2_HDMI_STATUS … #define mmDIG2_HDMI_STATUS_BASE_IDX … #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG2_HDMI_ACR_PACKET_CONTROL … #define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG2_HDMI_VBI_PACKET_CONTROL … #define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG2_HDMI_INFOFRAME_CONTROL0 … #define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG2_HDMI_INFOFRAME_CONTROL1 … #define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG2_AFMT_INTERRUPT_STATUS … #define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG2_HDMI_GC … #define mmDIG2_HDMI_GC_BASE_IDX … #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG2_AFMT_ISRC1_0 … #define mmDIG2_AFMT_ISRC1_0_BASE_IDX … #define mmDIG2_AFMT_ISRC1_1 … #define mmDIG2_AFMT_ISRC1_1_BASE_IDX … #define mmDIG2_AFMT_ISRC1_2 … #define mmDIG2_AFMT_ISRC1_2_BASE_IDX … #define mmDIG2_AFMT_ISRC1_3 … #define mmDIG2_AFMT_ISRC1_3_BASE_IDX … #define mmDIG2_AFMT_ISRC1_4 … #define mmDIG2_AFMT_ISRC1_4_BASE_IDX … #define mmDIG2_AFMT_ISRC2_0 … #define mmDIG2_AFMT_ISRC2_0_BASE_IDX … #define mmDIG2_AFMT_ISRC2_1 … #define mmDIG2_AFMT_ISRC2_1_BASE_IDX … #define mmDIG2_AFMT_ISRC2_2 … #define mmDIG2_AFMT_ISRC2_2_BASE_IDX … #define mmDIG2_AFMT_ISRC2_3 … #define mmDIG2_AFMT_ISRC2_3_BASE_IDX … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define mmDIG2_HDMI_DB_CONTROL … #define mmDIG2_HDMI_DB_CONTROL_BASE_IDX … #define mmDIG2_AFMT_MPEG_INFO0 … #define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG2_AFMT_MPEG_INFO1 … #define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG2_AFMT_GENERIC_HDR … #define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG2_AFMT_GENERIC_0 … #define mmDIG2_AFMT_GENERIC_0_BASE_IDX … #define mmDIG2_AFMT_GENERIC_1 … #define mmDIG2_AFMT_GENERIC_1_BASE_IDX … #define mmDIG2_AFMT_GENERIC_2 … #define mmDIG2_AFMT_GENERIC_2_BASE_IDX … #define mmDIG2_AFMT_GENERIC_3 … #define mmDIG2_AFMT_GENERIC_3_BASE_IDX … #define mmDIG2_AFMT_GENERIC_4 … #define mmDIG2_AFMT_GENERIC_4_BASE_IDX … #define mmDIG2_AFMT_GENERIC_5 … #define mmDIG2_AFMT_GENERIC_5_BASE_IDX … #define mmDIG2_AFMT_GENERIC_6 … #define mmDIG2_AFMT_GENERIC_6_BASE_IDX … #define mmDIG2_AFMT_GENERIC_7 … #define mmDIG2_AFMT_GENERIC_7_BASE_IDX … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG2_HDMI_ACR_32_0 … #define mmDIG2_HDMI_ACR_32_0_BASE_IDX … #define mmDIG2_HDMI_ACR_32_1 … #define mmDIG2_HDMI_ACR_32_1_BASE_IDX … #define mmDIG2_HDMI_ACR_44_0 … #define mmDIG2_HDMI_ACR_44_0_BASE_IDX … #define mmDIG2_HDMI_ACR_44_1 … #define mmDIG2_HDMI_ACR_44_1_BASE_IDX … #define mmDIG2_HDMI_ACR_48_0 … #define mmDIG2_HDMI_ACR_48_0_BASE_IDX … #define mmDIG2_HDMI_ACR_48_1 … #define mmDIG2_HDMI_ACR_48_1_BASE_IDX … #define mmDIG2_HDMI_ACR_STATUS_0 … #define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG2_HDMI_ACR_STATUS_1 … #define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG2_AFMT_AUDIO_INFO0 … #define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG2_AFMT_AUDIO_INFO1 … #define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG2_AFMT_60958_0 … #define mmDIG2_AFMT_60958_0_BASE_IDX … #define mmDIG2_AFMT_60958_1 … #define mmDIG2_AFMT_60958_1_BASE_IDX … #define mmDIG2_AFMT_AUDIO_CRC_CONTROL … #define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG2_AFMT_RAMP_CONTROL0 … #define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG2_AFMT_RAMP_CONTROL1 … #define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG2_AFMT_RAMP_CONTROL2 … #define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG2_AFMT_RAMP_CONTROL3 … #define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG2_AFMT_60958_2 … #define mmDIG2_AFMT_60958_2_BASE_IDX … #define mmDIG2_AFMT_AUDIO_CRC_RESULT … #define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG2_AFMT_STATUS … #define mmDIG2_AFMT_STATUS_BASE_IDX … #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG2_AFMT_VBI_PACKET_CONTROL … #define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG2_AFMT_INFOFRAME_CONTROL0 … #define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG2_AFMT_AUDIO_SRC_CONTROL … #define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG2_DIG_BE_CNTL … #define mmDIG2_DIG_BE_CNTL_BASE_IDX … #define mmDIG2_DIG_BE_EN_CNTL … #define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG2_TMDS_CNTL … #define mmDIG2_TMDS_CNTL_BASE_IDX … #define mmDIG2_TMDS_CONTROL_CHAR … #define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG2_TMDS_CONTROL0_FEEDBACK … #define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG2_TMDS_CTL_BITS … #define mmDIG2_TMDS_CTL_BITS_BASE_IDX … #define mmDIG2_TMDS_DCBALANCER_CONTROL … #define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG2_TMDS_CTL0_1_GEN_CNTL … #define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG2_TMDS_CTL2_3_GEN_CNTL … #define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG2_DIG_VERSION … #define mmDIG2_DIG_VERSION_BASE_IDX … #define mmDIG2_DIG_LANE_ENABLE … #define mmDIG2_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG2_AFMT_CNTL … #define mmDIG2_AFMT_CNTL_BASE_IDX … #define mmDIG2_AFMT_VBI_PACKET_CONTROL1 … #define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX … // addressBlock: dce_dc_dio_dp2_dispdec // base address: 0x800 #define mmDP2_DP_LINK_CNTL … #define mmDP2_DP_LINK_CNTL_BASE_IDX … #define mmDP2_DP_PIXEL_FORMAT … #define mmDP2_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP2_DP_MSA_COLORIMETRY … #define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP2_DP_CONFIG … #define mmDP2_DP_CONFIG_BASE_IDX … #define mmDP2_DP_VID_STREAM_CNTL … #define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP2_DP_STEER_FIFO … #define mmDP2_DP_STEER_FIFO_BASE_IDX … #define mmDP2_DP_MSA_MISC … #define mmDP2_DP_MSA_MISC_BASE_IDX … #define mmDP2_DP_VID_TIMING … #define mmDP2_DP_VID_TIMING_BASE_IDX … #define mmDP2_DP_VID_N … #define mmDP2_DP_VID_N_BASE_IDX … #define mmDP2_DP_VID_M … #define mmDP2_DP_VID_M_BASE_IDX … #define mmDP2_DP_LINK_FRAMING_CNTL … #define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP2_DP_HBR2_EYE_PATTERN … #define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP2_DP_VID_MSA_VBID … #define mmDP2_DP_VID_MSA_VBID_BASE_IDX … #define mmDP2_DP_VID_INTERRUPT_CNTL … #define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_CNTL … #define mmDP2_DP_DPHY_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP2_DP_DPHY_SYM0 … #define mmDP2_DP_DPHY_SYM0_BASE_IDX … #define mmDP2_DP_DPHY_SYM1 … #define mmDP2_DP_DPHY_SYM1_BASE_IDX … #define mmDP2_DP_DPHY_SYM2 … #define mmDP2_DP_DPHY_SYM2_BASE_IDX … #define mmDP2_DP_DPHY_8B10B_CNTL … #define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_PRBS_CNTL … #define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_SCRAM_CNTL … #define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_CRC_EN … #define mmDP2_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP2_DP_DPHY_CRC_CNTL … #define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_CRC_RESULT … #define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP2_DP_DPHY_CRC_MST_CNTL … #define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_CRC_MST_STATUS … #define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP2_DP_DPHY_FAST_TRAINING … #define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP2_DP_SEC_CNTL … #define mmDP2_DP_SEC_CNTL_BASE_IDX … #define mmDP2_DP_SEC_CNTL1 … #define mmDP2_DP_SEC_CNTL1_BASE_IDX … #define mmDP2_DP_SEC_FRAMING1 … #define mmDP2_DP_SEC_FRAMING1_BASE_IDX … #define mmDP2_DP_SEC_FRAMING2 … #define mmDP2_DP_SEC_FRAMING2_BASE_IDX … #define mmDP2_DP_SEC_FRAMING3 … #define mmDP2_DP_SEC_FRAMING3_BASE_IDX … #define mmDP2_DP_SEC_FRAMING4 … #define mmDP2_DP_SEC_FRAMING4_BASE_IDX … #define mmDP2_DP_SEC_AUD_N … #define mmDP2_DP_SEC_AUD_N_BASE_IDX … #define mmDP2_DP_SEC_AUD_N_READBACK … #define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP2_DP_SEC_AUD_M … #define mmDP2_DP_SEC_AUD_M_BASE_IDX … #define mmDP2_DP_SEC_AUD_M_READBACK … #define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP2_DP_SEC_TIMESTAMP … #define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP2_DP_SEC_PACKET_CNTL … #define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP2_DP_MSE_RATE_CNTL … #define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP2_DP_MSE_RATE_UPDATE … #define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP2_DP_MSE_SAT0 … #define mmDP2_DP_MSE_SAT0_BASE_IDX … #define mmDP2_DP_MSE_SAT1 … #define mmDP2_DP_MSE_SAT1_BASE_IDX … #define mmDP2_DP_MSE_SAT2 … #define mmDP2_DP_MSE_SAT2_BASE_IDX … #define mmDP2_DP_MSE_SAT_UPDATE … #define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP2_DP_MSE_LINK_TIMING … #define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP2_DP_MSE_MISC_CNTL … #define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP2_DP_MSE_SAT0_STATUS … #define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP2_DP_MSE_SAT1_STATUS … #define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP2_DP_MSE_SAT2_STATUS … #define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX … #define mmDP2_DP_MSA_TIMING_PARAM1 … #define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX … #define mmDP2_DP_MSA_TIMING_PARAM2 … #define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX … #define mmDP2_DP_MSA_TIMING_PARAM3 … #define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX … #define mmDP2_DP_MSA_TIMING_PARAM4 … #define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX … #define mmDP2_DP_MSO_CNTL … #define mmDP2_DP_MSO_CNTL_BASE_IDX … #define mmDP2_DP_MSO_CNTL1 … #define mmDP2_DP_MSO_CNTL1_BASE_IDX … #define mmDP2_DP_DSC_CNTL … #define mmDP2_DP_DSC_CNTL_BASE_IDX … #define mmDP2_DP_SEC_CNTL2 … #define mmDP2_DP_SEC_CNTL2_BASE_IDX … #define mmDP2_DP_SEC_CNTL3 … #define mmDP2_DP_SEC_CNTL3_BASE_IDX … #define mmDP2_DP_SEC_CNTL4 … #define mmDP2_DP_SEC_CNTL4_BASE_IDX … #define mmDP2_DP_SEC_CNTL5 … #define mmDP2_DP_SEC_CNTL5_BASE_IDX … #define mmDP2_DP_SEC_CNTL6 … #define mmDP2_DP_SEC_CNTL6_BASE_IDX … #define mmDP2_DP_SEC_CNTL7 … #define mmDP2_DP_SEC_CNTL7_BASE_IDX … #define mmDP2_DP_DB_CNTL … #define mmDP2_DP_DB_CNTL_BASE_IDX … #define mmDP2_DP_MSA_VBID_MISC … #define mmDP2_DP_MSA_VBID_MISC_BASE_IDX … // addressBlock: dce_dc_dio_dig3_dispdec // base address: 0xc00 #define mmDIG3_DIG_FE_CNTL … #define mmDIG3_DIG_FE_CNTL_BASE_IDX … #define mmDIG3_DIG_OUTPUT_CRC_CNTL … #define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG3_DIG_OUTPUT_CRC_RESULT … #define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG3_DIG_CLOCK_PATTERN … #define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG3_DIG_TEST_PATTERN … #define mmDIG3_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG3_DIG_RANDOM_PATTERN_SEED … #define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG3_DIG_FIFO_STATUS … #define mmDIG3_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG3_HDMI_CONTROL … #define mmDIG3_HDMI_CONTROL_BASE_IDX … #define mmDIG3_HDMI_STATUS … #define mmDIG3_HDMI_STATUS_BASE_IDX … #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG3_HDMI_ACR_PACKET_CONTROL … #define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG3_HDMI_VBI_PACKET_CONTROL … #define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG3_HDMI_INFOFRAME_CONTROL0 … #define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG3_HDMI_INFOFRAME_CONTROL1 … #define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG3_AFMT_INTERRUPT_STATUS … #define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG3_HDMI_GC … #define mmDIG3_HDMI_GC_BASE_IDX … #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG3_AFMT_ISRC1_0 … #define mmDIG3_AFMT_ISRC1_0_BASE_IDX … #define mmDIG3_AFMT_ISRC1_1 … #define mmDIG3_AFMT_ISRC1_1_BASE_IDX … #define mmDIG3_AFMT_ISRC1_2 … #define mmDIG3_AFMT_ISRC1_2_BASE_IDX … #define mmDIG3_AFMT_ISRC1_3 … #define mmDIG3_AFMT_ISRC1_3_BASE_IDX … #define mmDIG3_AFMT_ISRC1_4 … #define mmDIG3_AFMT_ISRC1_4_BASE_IDX … #define mmDIG3_AFMT_ISRC2_0 … #define mmDIG3_AFMT_ISRC2_0_BASE_IDX … #define mmDIG3_AFMT_ISRC2_1 … #define mmDIG3_AFMT_ISRC2_1_BASE_IDX … #define mmDIG3_AFMT_ISRC2_2 … #define mmDIG3_AFMT_ISRC2_2_BASE_IDX … #define mmDIG3_AFMT_ISRC2_3 … #define mmDIG3_AFMT_ISRC2_3_BASE_IDX … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define mmDIG3_HDMI_DB_CONTROL … #define mmDIG3_HDMI_DB_CONTROL_BASE_IDX … #define mmDIG3_AFMT_MPEG_INFO0 … #define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG3_AFMT_MPEG_INFO1 … #define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG3_AFMT_GENERIC_HDR … #define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG3_AFMT_GENERIC_0 … #define mmDIG3_AFMT_GENERIC_0_BASE_IDX … #define mmDIG3_AFMT_GENERIC_1 … #define mmDIG3_AFMT_GENERIC_1_BASE_IDX … #define mmDIG3_AFMT_GENERIC_2 … #define mmDIG3_AFMT_GENERIC_2_BASE_IDX … #define mmDIG3_AFMT_GENERIC_3 … #define mmDIG3_AFMT_GENERIC_3_BASE_IDX … #define mmDIG3_AFMT_GENERIC_4 … #define mmDIG3_AFMT_GENERIC_4_BASE_IDX … #define mmDIG3_AFMT_GENERIC_5 … #define mmDIG3_AFMT_GENERIC_5_BASE_IDX … #define mmDIG3_AFMT_GENERIC_6 … #define mmDIG3_AFMT_GENERIC_6_BASE_IDX … #define mmDIG3_AFMT_GENERIC_7 … #define mmDIG3_AFMT_GENERIC_7_BASE_IDX … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG3_HDMI_ACR_32_0 … #define mmDIG3_HDMI_ACR_32_0_BASE_IDX … #define mmDIG3_HDMI_ACR_32_1 … #define mmDIG3_HDMI_ACR_32_1_BASE_IDX … #define mmDIG3_HDMI_ACR_44_0 … #define mmDIG3_HDMI_ACR_44_0_BASE_IDX … #define mmDIG3_HDMI_ACR_44_1 … #define mmDIG3_HDMI_ACR_44_1_BASE_IDX … #define mmDIG3_HDMI_ACR_48_0 … #define mmDIG3_HDMI_ACR_48_0_BASE_IDX … #define mmDIG3_HDMI_ACR_48_1 … #define mmDIG3_HDMI_ACR_48_1_BASE_IDX … #define mmDIG3_HDMI_ACR_STATUS_0 … #define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG3_HDMI_ACR_STATUS_1 … #define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG3_AFMT_AUDIO_INFO0 … #define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG3_AFMT_AUDIO_INFO1 … #define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG3_AFMT_60958_0 … #define mmDIG3_AFMT_60958_0_BASE_IDX … #define mmDIG3_AFMT_60958_1 … #define mmDIG3_AFMT_60958_1_BASE_IDX … #define mmDIG3_AFMT_AUDIO_CRC_CONTROL … #define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG3_AFMT_RAMP_CONTROL0 … #define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG3_AFMT_RAMP_CONTROL1 … #define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG3_AFMT_RAMP_CONTROL2 … #define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG3_AFMT_RAMP_CONTROL3 … #define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG3_AFMT_60958_2 … #define mmDIG3_AFMT_60958_2_BASE_IDX … #define mmDIG3_AFMT_AUDIO_CRC_RESULT … #define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG3_AFMT_STATUS … #define mmDIG3_AFMT_STATUS_BASE_IDX … #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG3_AFMT_VBI_PACKET_CONTROL … #define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG3_AFMT_INFOFRAME_CONTROL0 … #define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG3_AFMT_AUDIO_SRC_CONTROL … #define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG3_DIG_BE_CNTL … #define mmDIG3_DIG_BE_CNTL_BASE_IDX … #define mmDIG3_DIG_BE_EN_CNTL … #define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG3_TMDS_CNTL … #define mmDIG3_TMDS_CNTL_BASE_IDX … #define mmDIG3_TMDS_CONTROL_CHAR … #define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG3_TMDS_CONTROL0_FEEDBACK … #define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG3_TMDS_CTL_BITS … #define mmDIG3_TMDS_CTL_BITS_BASE_IDX … #define mmDIG3_TMDS_DCBALANCER_CONTROL … #define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG3_TMDS_CTL0_1_GEN_CNTL … #define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG3_TMDS_CTL2_3_GEN_CNTL … #define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG3_DIG_VERSION … #define mmDIG3_DIG_VERSION_BASE_IDX … #define mmDIG3_DIG_LANE_ENABLE … #define mmDIG3_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG3_AFMT_CNTL … #define mmDIG3_AFMT_CNTL_BASE_IDX … #define mmDIG3_AFMT_VBI_PACKET_CONTROL1 … #define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX … // addressBlock: dce_dc_dio_dp3_dispdec // base address: 0xc00 #define mmDP3_DP_LINK_CNTL … #define mmDP3_DP_LINK_CNTL_BASE_IDX … #define mmDP3_DP_PIXEL_FORMAT … #define mmDP3_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP3_DP_MSA_COLORIMETRY … #define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP3_DP_CONFIG … #define mmDP3_DP_CONFIG_BASE_IDX … #define mmDP3_DP_VID_STREAM_CNTL … #define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP3_DP_STEER_FIFO … #define mmDP3_DP_STEER_FIFO_BASE_IDX … #define mmDP3_DP_MSA_MISC … #define mmDP3_DP_MSA_MISC_BASE_IDX … #define mmDP3_DP_VID_TIMING … #define mmDP3_DP_VID_TIMING_BASE_IDX … #define mmDP3_DP_VID_N … #define mmDP3_DP_VID_N_BASE_IDX … #define mmDP3_DP_VID_M … #define mmDP3_DP_VID_M_BASE_IDX … #define mmDP3_DP_LINK_FRAMING_CNTL … #define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP3_DP_HBR2_EYE_PATTERN … #define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP3_DP_VID_MSA_VBID … #define mmDP3_DP_VID_MSA_VBID_BASE_IDX … #define mmDP3_DP_VID_INTERRUPT_CNTL … #define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_CNTL … #define mmDP3_DP_DPHY_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP3_DP_DPHY_SYM0 … #define mmDP3_DP_DPHY_SYM0_BASE_IDX … #define mmDP3_DP_DPHY_SYM1 … #define mmDP3_DP_DPHY_SYM1_BASE_IDX … #define mmDP3_DP_DPHY_SYM2 … #define mmDP3_DP_DPHY_SYM2_BASE_IDX … #define mmDP3_DP_DPHY_8B10B_CNTL … #define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_PRBS_CNTL … #define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_SCRAM_CNTL … #define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_CRC_EN … #define mmDP3_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP3_DP_DPHY_CRC_CNTL … #define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_CRC_RESULT … #define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP3_DP_DPHY_CRC_MST_CNTL … #define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_CRC_MST_STATUS … #define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP3_DP_DPHY_FAST_TRAINING … #define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP3_DP_SEC_CNTL … #define mmDP3_DP_SEC_CNTL_BASE_IDX … #define mmDP3_DP_SEC_CNTL1 … #define mmDP3_DP_SEC_CNTL1_BASE_IDX … #define mmDP3_DP_SEC_FRAMING1 … #define mmDP3_DP_SEC_FRAMING1_BASE_IDX … #define mmDP3_DP_SEC_FRAMING2 … #define mmDP3_DP_SEC_FRAMING2_BASE_IDX … #define mmDP3_DP_SEC_FRAMING3 … #define mmDP3_DP_SEC_FRAMING3_BASE_IDX … #define mmDP3_DP_SEC_FRAMING4 … #define mmDP3_DP_SEC_FRAMING4_BASE_IDX … #define mmDP3_DP_SEC_AUD_N … #define mmDP3_DP_SEC_AUD_N_BASE_IDX … #define mmDP3_DP_SEC_AUD_N_READBACK … #define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP3_DP_SEC_AUD_M … #define mmDP3_DP_SEC_AUD_M_BASE_IDX … #define mmDP3_DP_SEC_AUD_M_READBACK … #define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP3_DP_SEC_TIMESTAMP … #define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP3_DP_SEC_PACKET_CNTL … #define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP3_DP_MSE_RATE_CNTL … #define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP3_DP_MSE_RATE_UPDATE … #define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP3_DP_MSE_SAT0 … #define mmDP3_DP_MSE_SAT0_BASE_IDX … #define mmDP3_DP_MSE_SAT1 … #define mmDP3_DP_MSE_SAT1_BASE_IDX … #define mmDP3_DP_MSE_SAT2 … #define mmDP3_DP_MSE_SAT2_BASE_IDX … #define mmDP3_DP_MSE_SAT_UPDATE … #define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP3_DP_MSE_LINK_TIMING … #define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP3_DP_MSE_MISC_CNTL … #define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP3_DP_MSE_SAT0_STATUS … #define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP3_DP_MSE_SAT1_STATUS … #define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP3_DP_MSE_SAT2_STATUS … #define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX … #define mmDP3_DP_MSA_TIMING_PARAM1 … #define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX … #define mmDP3_DP_MSA_TIMING_PARAM2 … #define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX … #define mmDP3_DP_MSA_TIMING_PARAM3 … #define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX … #define mmDP3_DP_MSA_TIMING_PARAM4 … #define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX … #define mmDP3_DP_MSO_CNTL … #define mmDP3_DP_MSO_CNTL_BASE_IDX … #define mmDP3_DP_MSO_CNTL1 … #define mmDP3_DP_MSO_CNTL1_BASE_IDX … #define mmDP3_DP_DSC_CNTL … #define mmDP3_DP_DSC_CNTL_BASE_IDX … #define mmDP3_DP_SEC_CNTL2 … #define mmDP3_DP_SEC_CNTL2_BASE_IDX … #define mmDP3_DP_SEC_CNTL3 … #define mmDP3_DP_SEC_CNTL3_BASE_IDX … #define mmDP3_DP_SEC_CNTL4 … #define mmDP3_DP_SEC_CNTL4_BASE_IDX … #define mmDP3_DP_SEC_CNTL5 … #define mmDP3_DP_SEC_CNTL5_BASE_IDX … #define mmDP3_DP_SEC_CNTL6 … #define mmDP3_DP_SEC_CNTL6_BASE_IDX … #define mmDP3_DP_SEC_CNTL7 … #define mmDP3_DP_SEC_CNTL7_BASE_IDX … #define mmDP3_DP_DB_CNTL … #define mmDP3_DP_DB_CNTL_BASE_IDX … #define mmDP3_DP_MSA_VBID_MISC … #define mmDP3_DP_MSA_VBID_MISC_BASE_IDX … // addressBlock: dce_dc_dio_dig4_dispdec // base address: 0x1000 #define mmDIG4_DIG_FE_CNTL … #define mmDIG4_DIG_FE_CNTL_BASE_IDX … #define mmDIG4_DIG_OUTPUT_CRC_CNTL … #define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG4_DIG_OUTPUT_CRC_RESULT … #define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG4_DIG_CLOCK_PATTERN … #define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG4_DIG_TEST_PATTERN … #define mmDIG4_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG4_DIG_RANDOM_PATTERN_SEED … #define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG4_DIG_FIFO_STATUS … #define mmDIG4_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG4_HDMI_CONTROL … #define mmDIG4_HDMI_CONTROL_BASE_IDX … #define mmDIG4_HDMI_STATUS … #define mmDIG4_HDMI_STATUS_BASE_IDX … #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG4_HDMI_ACR_PACKET_CONTROL … #define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG4_HDMI_VBI_PACKET_CONTROL … #define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG4_HDMI_INFOFRAME_CONTROL0 … #define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG4_HDMI_INFOFRAME_CONTROL1 … #define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG4_AFMT_INTERRUPT_STATUS … #define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG4_HDMI_GC … #define mmDIG4_HDMI_GC_BASE_IDX … #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG4_AFMT_ISRC1_0 … #define mmDIG4_AFMT_ISRC1_0_BASE_IDX … #define mmDIG4_AFMT_ISRC1_1 … #define mmDIG4_AFMT_ISRC1_1_BASE_IDX … #define mmDIG4_AFMT_ISRC1_2 … #define mmDIG4_AFMT_ISRC1_2_BASE_IDX … #define mmDIG4_AFMT_ISRC1_3 … #define mmDIG4_AFMT_ISRC1_3_BASE_IDX … #define mmDIG4_AFMT_ISRC1_4 … #define mmDIG4_AFMT_ISRC1_4_BASE_IDX … #define mmDIG4_AFMT_ISRC2_0 … #define mmDIG4_AFMT_ISRC2_0_BASE_IDX … #define mmDIG4_AFMT_ISRC2_1 … #define mmDIG4_AFMT_ISRC2_1_BASE_IDX … #define mmDIG4_AFMT_ISRC2_2 … #define mmDIG4_AFMT_ISRC2_2_BASE_IDX … #define mmDIG4_AFMT_ISRC2_3 … #define mmDIG4_AFMT_ISRC2_3_BASE_IDX … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define mmDIG4_HDMI_DB_CONTROL … #define mmDIG4_HDMI_DB_CONTROL_BASE_IDX … #define mmDIG4_AFMT_MPEG_INFO0 … #define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG4_AFMT_MPEG_INFO1 … #define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG4_AFMT_GENERIC_HDR … #define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG4_AFMT_GENERIC_0 … #define mmDIG4_AFMT_GENERIC_0_BASE_IDX … #define mmDIG4_AFMT_GENERIC_1 … #define mmDIG4_AFMT_GENERIC_1_BASE_IDX … #define mmDIG4_AFMT_GENERIC_2 … #define mmDIG4_AFMT_GENERIC_2_BASE_IDX … #define mmDIG4_AFMT_GENERIC_3 … #define mmDIG4_AFMT_GENERIC_3_BASE_IDX … #define mmDIG4_AFMT_GENERIC_4 … #define mmDIG4_AFMT_GENERIC_4_BASE_IDX … #define mmDIG4_AFMT_GENERIC_5 … #define mmDIG4_AFMT_GENERIC_5_BASE_IDX … #define mmDIG4_AFMT_GENERIC_6 … #define mmDIG4_AFMT_GENERIC_6_BASE_IDX … #define mmDIG4_AFMT_GENERIC_7 … #define mmDIG4_AFMT_GENERIC_7_BASE_IDX … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG4_HDMI_ACR_32_0 … #define mmDIG4_HDMI_ACR_32_0_BASE_IDX … #define mmDIG4_HDMI_ACR_32_1 … #define mmDIG4_HDMI_ACR_32_1_BASE_IDX … #define mmDIG4_HDMI_ACR_44_0 … #define mmDIG4_HDMI_ACR_44_0_BASE_IDX … #define mmDIG4_HDMI_ACR_44_1 … #define mmDIG4_HDMI_ACR_44_1_BASE_IDX … #define mmDIG4_HDMI_ACR_48_0 … #define mmDIG4_HDMI_ACR_48_0_BASE_IDX … #define mmDIG4_HDMI_ACR_48_1 … #define mmDIG4_HDMI_ACR_48_1_BASE_IDX … #define mmDIG4_HDMI_ACR_STATUS_0 … #define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG4_HDMI_ACR_STATUS_1 … #define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG4_AFMT_AUDIO_INFO0 … #define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG4_AFMT_AUDIO_INFO1 … #define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG4_AFMT_60958_0 … #define mmDIG4_AFMT_60958_0_BASE_IDX … #define mmDIG4_AFMT_60958_1 … #define mmDIG4_AFMT_60958_1_BASE_IDX … #define mmDIG4_AFMT_AUDIO_CRC_CONTROL … #define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG4_AFMT_RAMP_CONTROL0 … #define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG4_AFMT_RAMP_CONTROL1 … #define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG4_AFMT_RAMP_CONTROL2 … #define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG4_AFMT_RAMP_CONTROL3 … #define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG4_AFMT_60958_2 … #define mmDIG4_AFMT_60958_2_BASE_IDX … #define mmDIG4_AFMT_AUDIO_CRC_RESULT … #define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG4_AFMT_STATUS … #define mmDIG4_AFMT_STATUS_BASE_IDX … #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG4_AFMT_VBI_PACKET_CONTROL … #define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG4_AFMT_INFOFRAME_CONTROL0 … #define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG4_AFMT_AUDIO_SRC_CONTROL … #define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG4_DIG_BE_CNTL … #define mmDIG4_DIG_BE_CNTL_BASE_IDX … #define mmDIG4_DIG_BE_EN_CNTL … #define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG4_TMDS_CNTL … #define mmDIG4_TMDS_CNTL_BASE_IDX … #define mmDIG4_TMDS_CONTROL_CHAR … #define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG4_TMDS_CONTROL0_FEEDBACK … #define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG4_TMDS_CTL_BITS … #define mmDIG4_TMDS_CTL_BITS_BASE_IDX … #define mmDIG4_TMDS_DCBALANCER_CONTROL … #define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG4_TMDS_CTL0_1_GEN_CNTL … #define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG4_TMDS_CTL2_3_GEN_CNTL … #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG4_DIG_VERSION … #define mmDIG4_DIG_VERSION_BASE_IDX … #define mmDIG4_DIG_LANE_ENABLE … #define mmDIG4_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG4_AFMT_CNTL … #define mmDIG4_AFMT_CNTL_BASE_IDX … #define mmDIG4_AFMT_VBI_PACKET_CONTROL1 … #define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX … // addressBlock: dce_dc_dio_dp4_dispdec // base address: 0x1000 #define mmDP4_DP_LINK_CNTL … #define mmDP4_DP_LINK_CNTL_BASE_IDX … #define mmDP4_DP_PIXEL_FORMAT … #define mmDP4_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP4_DP_MSA_COLORIMETRY … #define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP4_DP_CONFIG … #define mmDP4_DP_CONFIG_BASE_IDX … #define mmDP4_DP_VID_STREAM_CNTL … #define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP4_DP_STEER_FIFO … #define mmDP4_DP_STEER_FIFO_BASE_IDX … #define mmDP4_DP_MSA_MISC … #define mmDP4_DP_MSA_MISC_BASE_IDX … #define mmDP4_DP_VID_TIMING … #define mmDP4_DP_VID_TIMING_BASE_IDX … #define mmDP4_DP_VID_N … #define mmDP4_DP_VID_N_BASE_IDX … #define mmDP4_DP_VID_M … #define mmDP4_DP_VID_M_BASE_IDX … #define mmDP4_DP_LINK_FRAMING_CNTL … #define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP4_DP_HBR2_EYE_PATTERN … #define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP4_DP_VID_MSA_VBID … #define mmDP4_DP_VID_MSA_VBID_BASE_IDX … #define mmDP4_DP_VID_INTERRUPT_CNTL … #define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_CNTL … #define mmDP4_DP_DPHY_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP4_DP_DPHY_SYM0 … #define mmDP4_DP_DPHY_SYM0_BASE_IDX … #define mmDP4_DP_DPHY_SYM1 … #define mmDP4_DP_DPHY_SYM1_BASE_IDX … #define mmDP4_DP_DPHY_SYM2 … #define mmDP4_DP_DPHY_SYM2_BASE_IDX … #define mmDP4_DP_DPHY_8B10B_CNTL … #define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_PRBS_CNTL … #define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_SCRAM_CNTL … #define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_CRC_EN … #define mmDP4_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP4_DP_DPHY_CRC_CNTL … #define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_CRC_RESULT … #define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP4_DP_DPHY_CRC_MST_CNTL … #define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_CRC_MST_STATUS … #define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP4_DP_DPHY_FAST_TRAINING … #define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP4_DP_SEC_CNTL … #define mmDP4_DP_SEC_CNTL_BASE_IDX … #define mmDP4_DP_SEC_CNTL1 … #define mmDP4_DP_SEC_CNTL1_BASE_IDX … #define mmDP4_DP_SEC_FRAMING1 … #define mmDP4_DP_SEC_FRAMING1_BASE_IDX … #define mmDP4_DP_SEC_FRAMING2 … #define mmDP4_DP_SEC_FRAMING2_BASE_IDX … #define mmDP4_DP_SEC_FRAMING3 … #define mmDP4_DP_SEC_FRAMING3_BASE_IDX … #define mmDP4_DP_SEC_FRAMING4 … #define mmDP4_DP_SEC_FRAMING4_BASE_IDX … #define mmDP4_DP_SEC_AUD_N … #define mmDP4_DP_SEC_AUD_N_BASE_IDX … #define mmDP4_DP_SEC_AUD_N_READBACK … #define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP4_DP_SEC_AUD_M … #define mmDP4_DP_SEC_AUD_M_BASE_IDX … #define mmDP4_DP_SEC_AUD_M_READBACK … #define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP4_DP_SEC_TIMESTAMP … #define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP4_DP_SEC_PACKET_CNTL … #define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP4_DP_MSE_RATE_CNTL … #define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP4_DP_MSE_RATE_UPDATE … #define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP4_DP_MSE_SAT0 … #define mmDP4_DP_MSE_SAT0_BASE_IDX … #define mmDP4_DP_MSE_SAT1 … #define mmDP4_DP_MSE_SAT1_BASE_IDX … #define mmDP4_DP_MSE_SAT2 … #define mmDP4_DP_MSE_SAT2_BASE_IDX … #define mmDP4_DP_MSE_SAT_UPDATE … #define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP4_DP_MSE_LINK_TIMING … #define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP4_DP_MSE_MISC_CNTL … #define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP4_DP_MSE_SAT0_STATUS … #define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP4_DP_MSE_SAT1_STATUS … #define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP4_DP_MSE_SAT2_STATUS … #define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX … #define mmDP4_DP_MSA_TIMING_PARAM1 … #define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX … #define mmDP4_DP_MSA_TIMING_PARAM2 … #define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX … #define mmDP4_DP_MSA_TIMING_PARAM3 … #define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX … #define mmDP4_DP_MSA_TIMING_PARAM4 … #define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX … #define mmDP4_DP_MSO_CNTL … #define mmDP4_DP_MSO_CNTL_BASE_IDX … #define mmDP4_DP_MSO_CNTL1 … #define mmDP4_DP_MSO_CNTL1_BASE_IDX … #define mmDP4_DP_DSC_CNTL … #define mmDP4_DP_DSC_CNTL_BASE_IDX … #define mmDP4_DP_SEC_CNTL2 … #define mmDP4_DP_SEC_CNTL2_BASE_IDX … #define mmDP4_DP_SEC_CNTL3 … #define mmDP4_DP_SEC_CNTL3_BASE_IDX … #define mmDP4_DP_SEC_CNTL4 … #define mmDP4_DP_SEC_CNTL4_BASE_IDX … #define mmDP4_DP_SEC_CNTL5 … #define mmDP4_DP_SEC_CNTL5_BASE_IDX … #define mmDP4_DP_SEC_CNTL6 … #define mmDP4_DP_SEC_CNTL6_BASE_IDX … #define mmDP4_DP_SEC_CNTL7 … #define mmDP4_DP_SEC_CNTL7_BASE_IDX … #define mmDP4_DP_DB_CNTL … #define mmDP4_DP_DB_CNTL_BASE_IDX … #define mmDP4_DP_MSA_VBID_MISC … #define mmDP4_DP_MSA_VBID_MISC_BASE_IDX … // addressBlock: dce_dc_dio_dig5_dispdec // base address: 0x1400 #define mmDIG5_DIG_FE_CNTL … #define mmDIG5_DIG_FE_CNTL_BASE_IDX … #define mmDIG5_DIG_OUTPUT_CRC_CNTL … #define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG5_DIG_OUTPUT_CRC_RESULT … #define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG5_DIG_CLOCK_PATTERN … #define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG5_DIG_TEST_PATTERN … #define mmDIG5_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG5_DIG_RANDOM_PATTERN_SEED … #define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG5_DIG_FIFO_STATUS … #define mmDIG5_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG5_HDMI_CONTROL … #define mmDIG5_HDMI_CONTROL_BASE_IDX … #define mmDIG5_HDMI_STATUS … #define mmDIG5_HDMI_STATUS_BASE_IDX … #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG5_HDMI_ACR_PACKET_CONTROL … #define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG5_HDMI_VBI_PACKET_CONTROL … #define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG5_HDMI_INFOFRAME_CONTROL0 … #define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG5_HDMI_INFOFRAME_CONTROL1 … #define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG5_AFMT_INTERRUPT_STATUS … #define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG5_HDMI_GC … #define mmDIG5_HDMI_GC_BASE_IDX … #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG5_AFMT_ISRC1_0 … #define mmDIG5_AFMT_ISRC1_0_BASE_IDX … #define mmDIG5_AFMT_ISRC1_1 … #define mmDIG5_AFMT_ISRC1_1_BASE_IDX … #define mmDIG5_AFMT_ISRC1_2 … #define mmDIG5_AFMT_ISRC1_2_BASE_IDX … #define mmDIG5_AFMT_ISRC1_3 … #define mmDIG5_AFMT_ISRC1_3_BASE_IDX … #define mmDIG5_AFMT_ISRC1_4 … #define mmDIG5_AFMT_ISRC1_4_BASE_IDX … #define mmDIG5_AFMT_ISRC2_0 … #define mmDIG5_AFMT_ISRC2_0_BASE_IDX … #define mmDIG5_AFMT_ISRC2_1 … #define mmDIG5_AFMT_ISRC2_1_BASE_IDX … #define mmDIG5_AFMT_ISRC2_2 … #define mmDIG5_AFMT_ISRC2_2_BASE_IDX … #define mmDIG5_AFMT_ISRC2_3 … #define mmDIG5_AFMT_ISRC2_3_BASE_IDX … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define mmDIG5_HDMI_DB_CONTROL … #define mmDIG5_HDMI_DB_CONTROL_BASE_IDX … #define mmDIG5_AFMT_MPEG_INFO0 … #define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG5_AFMT_MPEG_INFO1 … #define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG5_AFMT_GENERIC_HDR … #define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG5_AFMT_GENERIC_0 … #define mmDIG5_AFMT_GENERIC_0_BASE_IDX … #define mmDIG5_AFMT_GENERIC_1 … #define mmDIG5_AFMT_GENERIC_1_BASE_IDX … #define mmDIG5_AFMT_GENERIC_2 … #define mmDIG5_AFMT_GENERIC_2_BASE_IDX … #define mmDIG5_AFMT_GENERIC_3 … #define mmDIG5_AFMT_GENERIC_3_BASE_IDX … #define mmDIG5_AFMT_GENERIC_4 … #define mmDIG5_AFMT_GENERIC_4_BASE_IDX … #define mmDIG5_AFMT_GENERIC_5 … #define mmDIG5_AFMT_GENERIC_5_BASE_IDX … #define mmDIG5_AFMT_GENERIC_6 … #define mmDIG5_AFMT_GENERIC_6_BASE_IDX … #define mmDIG5_AFMT_GENERIC_7 … #define mmDIG5_AFMT_GENERIC_7_BASE_IDX … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG5_HDMI_ACR_32_0 … #define mmDIG5_HDMI_ACR_32_0_BASE_IDX … #define mmDIG5_HDMI_ACR_32_1 … #define mmDIG5_HDMI_ACR_32_1_BASE_IDX … #define mmDIG5_HDMI_ACR_44_0 … #define mmDIG5_HDMI_ACR_44_0_BASE_IDX … #define mmDIG5_HDMI_ACR_44_1 … #define mmDIG5_HDMI_ACR_44_1_BASE_IDX … #define mmDIG5_HDMI_ACR_48_0 … #define mmDIG5_HDMI_ACR_48_0_BASE_IDX … #define mmDIG5_HDMI_ACR_48_1 … #define mmDIG5_HDMI_ACR_48_1_BASE_IDX … #define mmDIG5_HDMI_ACR_STATUS_0 … #define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG5_HDMI_ACR_STATUS_1 … #define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG5_AFMT_AUDIO_INFO0 … #define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG5_AFMT_AUDIO_INFO1 … #define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG5_AFMT_60958_0 … #define mmDIG5_AFMT_60958_0_BASE_IDX … #define mmDIG5_AFMT_60958_1 … #define mmDIG5_AFMT_60958_1_BASE_IDX … #define mmDIG5_AFMT_AUDIO_CRC_CONTROL … #define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG5_AFMT_RAMP_CONTROL0 … #define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG5_AFMT_RAMP_CONTROL1 … #define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG5_AFMT_RAMP_CONTROL2 … #define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG5_AFMT_RAMP_CONTROL3 … #define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG5_AFMT_60958_2 … #define mmDIG5_AFMT_60958_2_BASE_IDX … #define mmDIG5_AFMT_AUDIO_CRC_RESULT … #define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG5_AFMT_STATUS … #define mmDIG5_AFMT_STATUS_BASE_IDX … #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG5_AFMT_VBI_PACKET_CONTROL … #define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG5_AFMT_INFOFRAME_CONTROL0 … #define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG5_AFMT_AUDIO_SRC_CONTROL … #define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG5_DIG_BE_CNTL … #define mmDIG5_DIG_BE_CNTL_BASE_IDX … #define mmDIG5_DIG_BE_EN_CNTL … #define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG5_TMDS_CNTL … #define mmDIG5_TMDS_CNTL_BASE_IDX … #define mmDIG5_TMDS_CONTROL_CHAR … #define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG5_TMDS_CONTROL0_FEEDBACK … #define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG5_TMDS_CTL_BITS … #define mmDIG5_TMDS_CTL_BITS_BASE_IDX … #define mmDIG5_TMDS_DCBALANCER_CONTROL … #define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG5_TMDS_CTL0_1_GEN_CNTL … #define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG5_TMDS_CTL2_3_GEN_CNTL … #define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG5_DIG_VERSION … #define mmDIG5_DIG_VERSION_BASE_IDX … #define mmDIG5_DIG_LANE_ENABLE … #define mmDIG5_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG5_AFMT_CNTL … #define mmDIG5_AFMT_CNTL_BASE_IDX … #define mmDIG5_AFMT_VBI_PACKET_CONTROL1 … #define mmDIG5_AFMT_VBI_PACKET_CONTROL1_BASE_IDX … // addressBlock: dce_dc_dio_dp5_dispdec // base address: 0x1400 #define mmDP5_DP_LINK_CNTL … #define mmDP5_DP_LINK_CNTL_BASE_IDX … #define mmDP5_DP_PIXEL_FORMAT … #define mmDP5_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP5_DP_MSA_COLORIMETRY … #define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP5_DP_CONFIG … #define mmDP5_DP_CONFIG_BASE_IDX … #define mmDP5_DP_VID_STREAM_CNTL … #define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP5_DP_STEER_FIFO … #define mmDP5_DP_STEER_FIFO_BASE_IDX … #define mmDP5_DP_MSA_MISC … #define mmDP5_DP_MSA_MISC_BASE_IDX … #define mmDP5_DP_VID_TIMING … #define mmDP5_DP_VID_TIMING_BASE_IDX … #define mmDP5_DP_VID_N … #define mmDP5_DP_VID_N_BASE_IDX … #define mmDP5_DP_VID_M … #define mmDP5_DP_VID_M_BASE_IDX … #define mmDP5_DP_LINK_FRAMING_CNTL … #define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP5_DP_HBR2_EYE_PATTERN … #define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP5_DP_VID_MSA_VBID … #define mmDP5_DP_VID_MSA_VBID_BASE_IDX … #define mmDP5_DP_VID_INTERRUPT_CNTL … #define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_CNTL … #define mmDP5_DP_DPHY_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP5_DP_DPHY_SYM0 … #define mmDP5_DP_DPHY_SYM0_BASE_IDX … #define mmDP5_DP_DPHY_SYM1 … #define mmDP5_DP_DPHY_SYM1_BASE_IDX … #define mmDP5_DP_DPHY_SYM2 … #define mmDP5_DP_DPHY_SYM2_BASE_IDX … #define mmDP5_DP_DPHY_8B10B_CNTL … #define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_PRBS_CNTL … #define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_SCRAM_CNTL … #define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_CRC_EN … #define mmDP5_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP5_DP_DPHY_CRC_CNTL … #define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_CRC_RESULT … #define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP5_DP_DPHY_CRC_MST_CNTL … #define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_CRC_MST_STATUS … #define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP5_DP_DPHY_FAST_TRAINING … #define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP5_DP_SEC_CNTL … #define mmDP5_DP_SEC_CNTL_BASE_IDX … #define mmDP5_DP_SEC_CNTL1 … #define mmDP5_DP_SEC_CNTL1_BASE_IDX … #define mmDP5_DP_SEC_FRAMING1 … #define mmDP5_DP_SEC_FRAMING1_BASE_IDX … #define mmDP5_DP_SEC_FRAMING2 … #define mmDP5_DP_SEC_FRAMING2_BASE_IDX … #define mmDP5_DP_SEC_FRAMING3 … #define mmDP5_DP_SEC_FRAMING3_BASE_IDX … #define mmDP5_DP_SEC_FRAMING4 … #define mmDP5_DP_SEC_FRAMING4_BASE_IDX … #define mmDP5_DP_SEC_AUD_N … #define mmDP5_DP_SEC_AUD_N_BASE_IDX … #define mmDP5_DP_SEC_AUD_N_READBACK … #define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP5_DP_SEC_AUD_M … #define mmDP5_DP_SEC_AUD_M_BASE_IDX … #define mmDP5_DP_SEC_AUD_M_READBACK … #define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP5_DP_SEC_TIMESTAMP … #define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP5_DP_SEC_PACKET_CNTL … #define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP5_DP_MSE_RATE_CNTL … #define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP5_DP_MSE_RATE_UPDATE … #define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP5_DP_MSE_SAT0 … #define mmDP5_DP_MSE_SAT0_BASE_IDX … #define mmDP5_DP_MSE_SAT1 … #define mmDP5_DP_MSE_SAT1_BASE_IDX … #define mmDP5_DP_MSE_SAT2 … #define mmDP5_DP_MSE_SAT2_BASE_IDX … #define mmDP5_DP_MSE_SAT_UPDATE … #define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP5_DP_MSE_LINK_TIMING … #define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP5_DP_MSE_MISC_CNTL … #define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP5_DP_MSE_SAT0_STATUS … #define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP5_DP_MSE_SAT1_STATUS … #define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP5_DP_MSE_SAT2_STATUS … #define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX … #define mmDP5_DP_MSA_TIMING_PARAM1 … #define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX … #define mmDP5_DP_MSA_TIMING_PARAM2 … #define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX … #define mmDP5_DP_MSA_TIMING_PARAM3 … #define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX … #define mmDP5_DP_MSA_TIMING_PARAM4 … #define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX … #define mmDP5_DP_MSO_CNTL … #define mmDP5_DP_MSO_CNTL_BASE_IDX … #define mmDP5_DP_MSO_CNTL1 … #define mmDP5_DP_MSO_CNTL1_BASE_IDX … #define mmDP5_DP_DSC_CNTL … #define mmDP5_DP_DSC_CNTL_BASE_IDX … #define mmDP5_DP_SEC_CNTL2 … #define mmDP5_DP_SEC_CNTL2_BASE_IDX … #define mmDP5_DP_SEC_CNTL3 … #define mmDP5_DP_SEC_CNTL3_BASE_IDX … #define mmDP5_DP_SEC_CNTL4 … #define mmDP5_DP_SEC_CNTL4_BASE_IDX … #define mmDP5_DP_SEC_CNTL5 … #define mmDP5_DP_SEC_CNTL5_BASE_IDX … #define mmDP5_DP_SEC_CNTL6 … #define mmDP5_DP_SEC_CNTL6_BASE_IDX … #define mmDP5_DP_SEC_CNTL7 … #define mmDP5_DP_SEC_CNTL7_BASE_IDX … #define mmDP5_DP_DB_CNTL … #define mmDP5_DP_DB_CNTL_BASE_IDX … #define mmDP5_DP_MSA_VBID_MISC … #define mmDP5_DP_MSA_VBID_MISC_BASE_IDX … // addressBlock: dce_dc_dio_dig6_dispdec // base address: 0x1800 #define mmDIG6_DIG_FE_CNTL … #define mmDIG6_DIG_FE_CNTL_BASE_IDX … #define mmDIG6_DIG_OUTPUT_CRC_CNTL … #define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG6_DIG_OUTPUT_CRC_RESULT … #define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG6_DIG_CLOCK_PATTERN … #define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG6_DIG_TEST_PATTERN … #define mmDIG6_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG6_DIG_RANDOM_PATTERN_SEED … #define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG6_DIG_FIFO_STATUS … #define mmDIG6_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG6_HDMI_CONTROL … #define mmDIG6_HDMI_CONTROL_BASE_IDX … #define mmDIG6_HDMI_STATUS … #define mmDIG6_HDMI_STATUS_BASE_IDX … #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG6_HDMI_ACR_PACKET_CONTROL … #define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG6_HDMI_VBI_PACKET_CONTROL … #define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG6_HDMI_INFOFRAME_CONTROL0 … #define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG6_HDMI_INFOFRAME_CONTROL1 … #define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG6_AFMT_INTERRUPT_STATUS … #define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG6_HDMI_GC … #define mmDIG6_HDMI_GC_BASE_IDX … #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG6_AFMT_ISRC1_0 … #define mmDIG6_AFMT_ISRC1_0_BASE_IDX … #define mmDIG6_AFMT_ISRC1_1 … #define mmDIG6_AFMT_ISRC1_1_BASE_IDX … #define mmDIG6_AFMT_ISRC1_2 … #define mmDIG6_AFMT_ISRC1_2_BASE_IDX … #define mmDIG6_AFMT_ISRC1_3 … #define mmDIG6_AFMT_ISRC1_3_BASE_IDX … #define mmDIG6_AFMT_ISRC1_4 … #define mmDIG6_AFMT_ISRC1_4_BASE_IDX … #define mmDIG6_AFMT_ISRC2_0 … #define mmDIG6_AFMT_ISRC2_0_BASE_IDX … #define mmDIG6_AFMT_ISRC2_1 … #define mmDIG6_AFMT_ISRC2_1_BASE_IDX … #define mmDIG6_AFMT_ISRC2_2 … #define mmDIG6_AFMT_ISRC2_2_BASE_IDX … #define mmDIG6_AFMT_ISRC2_3 … #define mmDIG6_AFMT_ISRC2_3_BASE_IDX … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2 … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3 … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define mmDIG6_HDMI_DB_CONTROL … #define mmDIG6_HDMI_DB_CONTROL_BASE_IDX … #define mmDIG6_AFMT_MPEG_INFO0 … #define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG6_AFMT_MPEG_INFO1 … #define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG6_AFMT_GENERIC_HDR … #define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG6_AFMT_GENERIC_0 … #define mmDIG6_AFMT_GENERIC_0_BASE_IDX … #define mmDIG6_AFMT_GENERIC_1 … #define mmDIG6_AFMT_GENERIC_1_BASE_IDX … #define mmDIG6_AFMT_GENERIC_2 … #define mmDIG6_AFMT_GENERIC_2_BASE_IDX … #define mmDIG6_AFMT_GENERIC_3 … #define mmDIG6_AFMT_GENERIC_3_BASE_IDX … #define mmDIG6_AFMT_GENERIC_4 … #define mmDIG6_AFMT_GENERIC_4_BASE_IDX … #define mmDIG6_AFMT_GENERIC_5 … #define mmDIG6_AFMT_GENERIC_5_BASE_IDX … #define mmDIG6_AFMT_GENERIC_6 … #define mmDIG6_AFMT_GENERIC_6_BASE_IDX … #define mmDIG6_AFMT_GENERIC_7 … #define mmDIG6_AFMT_GENERIC_7_BASE_IDX … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG6_HDMI_ACR_32_0 … #define mmDIG6_HDMI_ACR_32_0_BASE_IDX … #define mmDIG6_HDMI_ACR_32_1 … #define mmDIG6_HDMI_ACR_32_1_BASE_IDX … #define mmDIG6_HDMI_ACR_44_0 … #define mmDIG6_HDMI_ACR_44_0_BASE_IDX … #define mmDIG6_HDMI_ACR_44_1 … #define mmDIG6_HDMI_ACR_44_1_BASE_IDX … #define mmDIG6_HDMI_ACR_48_0 … #define mmDIG6_HDMI_ACR_48_0_BASE_IDX … #define mmDIG6_HDMI_ACR_48_1 … #define mmDIG6_HDMI_ACR_48_1_BASE_IDX … #define mmDIG6_HDMI_ACR_STATUS_0 … #define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG6_HDMI_ACR_STATUS_1 … #define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG6_AFMT_AUDIO_INFO0 … #define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG6_AFMT_AUDIO_INFO1 … #define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG6_AFMT_60958_0 … #define mmDIG6_AFMT_60958_0_BASE_IDX … #define mmDIG6_AFMT_60958_1 … #define mmDIG6_AFMT_60958_1_BASE_IDX … #define mmDIG6_AFMT_AUDIO_CRC_CONTROL … #define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG6_AFMT_RAMP_CONTROL0 … #define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG6_AFMT_RAMP_CONTROL1 … #define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG6_AFMT_RAMP_CONTROL2 … #define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG6_AFMT_RAMP_CONTROL3 … #define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG6_AFMT_60958_2 … #define mmDIG6_AFMT_60958_2_BASE_IDX … #define mmDIG6_AFMT_AUDIO_CRC_RESULT … #define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG6_AFMT_STATUS … #define mmDIG6_AFMT_STATUS_BASE_IDX … #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG6_AFMT_VBI_PACKET_CONTROL … #define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG6_AFMT_INFOFRAME_CONTROL0 … #define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG6_AFMT_AUDIO_SRC_CONTROL … #define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG6_DIG_BE_CNTL … #define mmDIG6_DIG_BE_CNTL_BASE_IDX … #define mmDIG6_DIG_BE_EN_CNTL … #define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG6_TMDS_CNTL … #define mmDIG6_TMDS_CNTL_BASE_IDX … #define mmDIG6_TMDS_CONTROL_CHAR … #define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG6_TMDS_CONTROL0_FEEDBACK … #define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG6_TMDS_CTL_BITS … #define mmDIG6_TMDS_CTL_BITS_BASE_IDX … #define mmDIG6_TMDS_DCBALANCER_CONTROL … #define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG6_TMDS_CTL0_1_GEN_CNTL … #define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG6_TMDS_CTL2_3_GEN_CNTL … #define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG6_DIG_VERSION … #define mmDIG6_DIG_VERSION_BASE_IDX … #define mmDIG6_DIG_LANE_ENABLE … #define mmDIG6_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG6_AFMT_CNTL … #define mmDIG6_AFMT_CNTL_BASE_IDX … #define mmDIG6_AFMT_VBI_PACKET_CONTROL1 … #define mmDIG6_AFMT_VBI_PACKET_CONTROL1_BASE_IDX … // addressBlock: dce_dc_dio_dp6_dispdec // base address: 0x1800 #define mmDP6_DP_LINK_CNTL … #define mmDP6_DP_LINK_CNTL_BASE_IDX … #define mmDP6_DP_PIXEL_FORMAT … #define mmDP6_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP6_DP_MSA_COLORIMETRY … #define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP6_DP_CONFIG … #define mmDP6_DP_CONFIG_BASE_IDX … #define mmDP6_DP_VID_STREAM_CNTL … #define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP6_DP_STEER_FIFO … #define mmDP6_DP_STEER_FIFO_BASE_IDX … #define mmDP6_DP_MSA_MISC … #define mmDP6_DP_MSA_MISC_BASE_IDX … #define mmDP6_DP_VID_TIMING … #define mmDP6_DP_VID_TIMING_BASE_IDX … #define mmDP6_DP_VID_N … #define mmDP6_DP_VID_N_BASE_IDX … #define mmDP6_DP_VID_M … #define mmDP6_DP_VID_M_BASE_IDX … #define mmDP6_DP_LINK_FRAMING_CNTL … #define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP6_DP_HBR2_EYE_PATTERN … #define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP6_DP_VID_MSA_VBID … #define mmDP6_DP_VID_MSA_VBID_BASE_IDX … #define mmDP6_DP_VID_INTERRUPT_CNTL … #define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_CNTL … #define mmDP6_DP_DPHY_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP6_DP_DPHY_SYM0 … #define mmDP6_DP_DPHY_SYM0_BASE_IDX … #define mmDP6_DP_DPHY_SYM1 … #define mmDP6_DP_DPHY_SYM1_BASE_IDX … #define mmDP6_DP_DPHY_SYM2 … #define mmDP6_DP_DPHY_SYM2_BASE_IDX … #define mmDP6_DP_DPHY_8B10B_CNTL … #define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_PRBS_CNTL … #define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_SCRAM_CNTL … #define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_CRC_EN … #define mmDP6_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP6_DP_DPHY_CRC_CNTL … #define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_CRC_RESULT … #define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP6_DP_DPHY_CRC_MST_CNTL … #define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_CRC_MST_STATUS … #define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP6_DP_DPHY_FAST_TRAINING … #define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP6_DP_SEC_CNTL … #define mmDP6_DP_SEC_CNTL_BASE_IDX … #define mmDP6_DP_SEC_CNTL1 … #define mmDP6_DP_SEC_CNTL1_BASE_IDX … #define mmDP6_DP_SEC_FRAMING1 … #define mmDP6_DP_SEC_FRAMING1_BASE_IDX … #define mmDP6_DP_SEC_FRAMING2 … #define mmDP6_DP_SEC_FRAMING2_BASE_IDX … #define mmDP6_DP_SEC_FRAMING3 … #define mmDP6_DP_SEC_FRAMING3_BASE_IDX … #define mmDP6_DP_SEC_FRAMING4 … #define mmDP6_DP_SEC_FRAMING4_BASE_IDX … #define mmDP6_DP_SEC_AUD_N … #define mmDP6_DP_SEC_AUD_N_BASE_IDX … #define mmDP6_DP_SEC_AUD_N_READBACK … #define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP6_DP_SEC_AUD_M … #define mmDP6_DP_SEC_AUD_M_BASE_IDX … #define mmDP6_DP_SEC_AUD_M_READBACK … #define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP6_DP_SEC_TIMESTAMP … #define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP6_DP_SEC_PACKET_CNTL … #define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP6_DP_MSE_RATE_CNTL … #define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP6_DP_MSE_RATE_UPDATE … #define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP6_DP_MSE_SAT0 … #define mmDP6_DP_MSE_SAT0_BASE_IDX … #define mmDP6_DP_MSE_SAT1 … #define mmDP6_DP_MSE_SAT1_BASE_IDX … #define mmDP6_DP_MSE_SAT2 … #define mmDP6_DP_MSE_SAT2_BASE_IDX … #define mmDP6_DP_MSE_SAT_UPDATE … #define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP6_DP_MSE_LINK_TIMING … #define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP6_DP_MSE_MISC_CNTL … #define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP6_DP_MSE_SAT0_STATUS … #define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP6_DP_MSE_SAT1_STATUS … #define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP6_DP_MSE_SAT2_STATUS … #define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX … #define mmDP6_DP_MSA_TIMING_PARAM1 … #define mmDP6_DP_MSA_TIMING_PARAM1_BASE_IDX … #define mmDP6_DP_MSA_TIMING_PARAM2 … #define mmDP6_DP_MSA_TIMING_PARAM2_BASE_IDX … #define mmDP6_DP_MSA_TIMING_PARAM3 … #define mmDP6_DP_MSA_TIMING_PARAM3_BASE_IDX … #define mmDP6_DP_MSA_TIMING_PARAM4 … #define mmDP6_DP_MSA_TIMING_PARAM4_BASE_IDX … #define mmDP6_DP_MSO_CNTL … #define mmDP6_DP_MSO_CNTL_BASE_IDX … #define mmDP6_DP_MSO_CNTL1 … #define mmDP6_DP_MSO_CNTL1_BASE_IDX … #define mmDP6_DP_DSC_CNTL … #define mmDP6_DP_DSC_CNTL_BASE_IDX … #define mmDP6_DP_SEC_CNTL2 … #define mmDP6_DP_SEC_CNTL2_BASE_IDX … #define mmDP6_DP_SEC_CNTL3 … #define mmDP6_DP_SEC_CNTL3_BASE_IDX … #define mmDP6_DP_SEC_CNTL4 … #define mmDP6_DP_SEC_CNTL4_BASE_IDX … #define mmDP6_DP_SEC_CNTL5 … #define mmDP6_DP_SEC_CNTL5_BASE_IDX … #define mmDP6_DP_SEC_CNTL6 … #define mmDP6_DP_SEC_CNTL6_BASE_IDX … #define mmDP6_DP_SEC_CNTL7 … #define mmDP6_DP_SEC_CNTL7_BASE_IDX … #define mmDP6_DP_DB_CNTL … #define mmDP6_DP_DB_CNTL_BASE_IDX … #define mmDP6_DP_MSA_VBID_MISC … #define mmDP6_DP_MSA_VBID_MISC_BASE_IDX … // addressBlock: dce_dc_dcio_dcio_dispdec // base address: 0x0 #define mmDC_GENERICA … #define mmDC_GENERICA_BASE_IDX … #define mmDC_GENERICB … #define mmDC_GENERICB_BASE_IDX … #define mmDC_REF_CLK_CNTL … #define mmDC_REF_CLK_CNTL_BASE_IDX … #define mmDC_GPIO_DEBUG … #define mmDC_GPIO_DEBUG_BASE_IDX … #define mmUNIPHYA_LINK_CNTL … #define mmUNIPHYA_LINK_CNTL_BASE_IDX … #define mmUNIPHYA_CHANNEL_XBAR_CNTL … #define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYB_LINK_CNTL … #define mmUNIPHYB_LINK_CNTL_BASE_IDX … #define mmUNIPHYB_CHANNEL_XBAR_CNTL … #define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYC_LINK_CNTL … #define mmUNIPHYC_LINK_CNTL_BASE_IDX … #define mmUNIPHYC_CHANNEL_XBAR_CNTL … #define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYD_LINK_CNTL … #define mmUNIPHYD_LINK_CNTL_BASE_IDX … #define mmUNIPHYD_CHANNEL_XBAR_CNTL … #define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYE_LINK_CNTL … #define mmUNIPHYE_LINK_CNTL_BASE_IDX … #define mmUNIPHYE_CHANNEL_XBAR_CNTL … #define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYF_LINK_CNTL … #define mmUNIPHYF_LINK_CNTL_BASE_IDX … #define mmUNIPHYF_CHANNEL_XBAR_CNTL … #define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYG_LINK_CNTL … #define mmUNIPHYG_LINK_CNTL_BASE_IDX … #define mmUNIPHYG_CHANNEL_XBAR_CNTL … #define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmDCIO_WRCMD_DELAY … #define mmDCIO_WRCMD_DELAY_BASE_IDX … #define mmDC_PINSTRAPS … #define mmDC_PINSTRAPS_BASE_IDX … #define mmDC_DVODATA_CONFIG … #define mmDC_DVODATA_CONFIG_BASE_IDX … #define mmLVTMA_PWRSEQ_CNTL … #define mmLVTMA_PWRSEQ_CNTL_BASE_IDX … #define mmLVTMA_PWRSEQ_STATE … #define mmLVTMA_PWRSEQ_STATE_BASE_IDX … #define mmLVTMA_PWRSEQ_REF_DIV … #define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX … #define mmLVTMA_PWRSEQ_DELAY1 … #define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX … #define mmLVTMA_PWRSEQ_DELAY2 … #define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX … #define mmBL_PWM_CNTL … #define mmBL_PWM_CNTL_BASE_IDX … #define mmBL_PWM_CNTL2 … #define mmBL_PWM_CNTL2_BASE_IDX … #define mmBL_PWM_PERIOD_CNTL … #define mmBL_PWM_PERIOD_CNTL_BASE_IDX … #define mmBL_PWM_GRP1_REG_LOCK … #define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX … #define mmDCIO_GSL_GENLK_PAD_CNTL … #define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX … #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL … #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX … #define mmDCIO_CLOCK_CNTL … #define mmDCIO_CLOCK_CNTL_BASE_IDX … #define mmDIO_OTG_EXT_VSYNC_CNTL … #define mmDIO_OTG_EXT_VSYNC_CNTL_BASE_IDX … #define mmDCIO_SOFT_RESET … #define mmDCIO_SOFT_RESET_BASE_IDX … #define mmDCIO_DPHY_SEL … #define mmDCIO_DPHY_SEL_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKA … #define mmUNIPHY_IMPCAL_LINKA_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKB … #define mmUNIPHY_IMPCAL_LINKB_BASE_IDX … #define mmUNIPHY_IMPCAL_PERIOD … #define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX … #define mmAUXP_IMPCAL … #define mmAUXP_IMPCAL_BASE_IDX … #define mmAUXN_IMPCAL … #define mmAUXN_IMPCAL_BASE_IDX … #define mmDCIO_IMPCAL_CNTL … #define mmDCIO_IMPCAL_CNTL_BASE_IDX … #define mmUNIPHY_IMPCAL_PSW_AB … #define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKC … #define mmUNIPHY_IMPCAL_LINKC_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKD … #define mmUNIPHY_IMPCAL_LINKD_BASE_IDX … #define mmDCIO_IMPCAL_CNTL_CD … #define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX … #define mmUNIPHY_IMPCAL_PSW_CD … #define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKE … #define mmUNIPHY_IMPCAL_LINKE_BASE_IDX … #define mmUNIPHY_IMPCAL_LINKF … #define mmUNIPHY_IMPCAL_LINKF_BASE_IDX … #define mmDCIO_IMPCAL_CNTL_EF … #define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX … #define mmUNIPHY_IMPCAL_PSW_EF … #define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX … #define mmDCIO_DPCS_TX_INTERRUPT … #define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX … #define mmDCIO_DPCS_RX_INTERRUPT … #define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX … #define mmDCIO_SEMAPHORE0 … #define mmDCIO_SEMAPHORE0_BASE_IDX … #define mmDCIO_SEMAPHORE1 … #define mmDCIO_SEMAPHORE1_BASE_IDX … #define mmDCIO_SEMAPHORE2 … #define mmDCIO_SEMAPHORE2_BASE_IDX … #define mmDCIO_SEMAPHORE3 … #define mmDCIO_SEMAPHORE3_BASE_IDX … #define mmDCIO_SEMAPHORE4 … #define mmDCIO_SEMAPHORE4_BASE_IDX … #define mmDCIO_SEMAPHORE5 … #define mmDCIO_SEMAPHORE5_BASE_IDX … #define mmDCIO_SEMAPHORE6 … #define mmDCIO_SEMAPHORE6_BASE_IDX … #define mmDCIO_SEMAPHORE7 … #define mmDCIO_SEMAPHORE7_BASE_IDX … #define mmDCIO_USBC_FLIP_EN_SEL … #define mmDCIO_USBC_FLIP_EN_SEL_BASE_IDX … // addressBlock: dce_dc_dcio_dcio_chip_dispdec // base address: 0x0 #define mmDC_GPIO_GENERIC_MASK … #define mmDC_GPIO_GENERIC_MASK_BASE_IDX … #define mmDC_GPIO_GENERIC_A … #define mmDC_GPIO_GENERIC_A_BASE_IDX … #define mmDC_GPIO_GENERIC_EN … #define mmDC_GPIO_GENERIC_EN_BASE_IDX … #define mmDC_GPIO_GENERIC_Y … #define mmDC_GPIO_GENERIC_Y_BASE_IDX … #define mmDC_GPIO_DVODATA_MASK … #define mmDC_GPIO_DVODATA_MASK_BASE_IDX … #define mmDC_GPIO_DVODATA_A … #define mmDC_GPIO_DVODATA_A_BASE_IDX … #define mmDC_GPIO_DVODATA_EN … #define mmDC_GPIO_DVODATA_EN_BASE_IDX … #define mmDC_GPIO_DVODATA_Y … #define mmDC_GPIO_DVODATA_Y_BASE_IDX … #define mmDC_GPIO_DDC1_MASK … #define mmDC_GPIO_DDC1_MASK_BASE_IDX … #define mmDC_GPIO_DDC1_A … #define mmDC_GPIO_DDC1_A_BASE_IDX … #define mmDC_GPIO_DDC1_EN … #define mmDC_GPIO_DDC1_EN_BASE_IDX … #define mmDC_GPIO_DDC1_Y … #define mmDC_GPIO_DDC1_Y_BASE_IDX … #define mmDC_GPIO_DDC2_MASK … #define mmDC_GPIO_DDC2_MASK_BASE_IDX … #define mmDC_GPIO_DDC2_A … #define mmDC_GPIO_DDC2_A_BASE_IDX … #define mmDC_GPIO_DDC2_EN … #define mmDC_GPIO_DDC2_EN_BASE_IDX … #define mmDC_GPIO_DDC2_Y … #define mmDC_GPIO_DDC2_Y_BASE_IDX … #define mmDC_GPIO_DDC3_MASK … #define mmDC_GPIO_DDC3_MASK_BASE_IDX … #define mmDC_GPIO_DDC3_A … #define mmDC_GPIO_DDC3_A_BASE_IDX … #define mmDC_GPIO_DDC3_EN … #define mmDC_GPIO_DDC3_EN_BASE_IDX … #define mmDC_GPIO_DDC3_Y … #define mmDC_GPIO_DDC3_Y_BASE_IDX … #define mmDC_GPIO_DDC4_MASK … #define mmDC_GPIO_DDC4_MASK_BASE_IDX … #define mmDC_GPIO_DDC4_A … #define mmDC_GPIO_DDC4_A_BASE_IDX … #define mmDC_GPIO_DDC4_EN … #define mmDC_GPIO_DDC4_EN_BASE_IDX … #define mmDC_GPIO_DDC4_Y … #define mmDC_GPIO_DDC4_Y_BASE_IDX … #define mmDC_GPIO_DDC5_MASK … #define mmDC_GPIO_DDC5_MASK_BASE_IDX … #define mmDC_GPIO_DDC5_A … #define mmDC_GPIO_DDC5_A_BASE_IDX … #define mmDC_GPIO_DDC5_EN … #define mmDC_GPIO_DDC5_EN_BASE_IDX … #define mmDC_GPIO_DDC5_Y … #define mmDC_GPIO_DDC5_Y_BASE_IDX … #define mmDC_GPIO_DDC6_MASK … #define mmDC_GPIO_DDC6_MASK_BASE_IDX … #define mmDC_GPIO_DDC6_A … #define mmDC_GPIO_DDC6_A_BASE_IDX … #define mmDC_GPIO_DDC6_EN … #define mmDC_GPIO_DDC6_EN_BASE_IDX … #define mmDC_GPIO_DDC6_Y … #define mmDC_GPIO_DDC6_Y_BASE_IDX … #define mmDC_GPIO_DDCVGA_MASK … #define mmDC_GPIO_DDCVGA_MASK_BASE_IDX … #define mmDC_GPIO_DDCVGA_A … #define mmDC_GPIO_DDCVGA_A_BASE_IDX … #define mmDC_GPIO_DDCVGA_EN … #define mmDC_GPIO_DDCVGA_EN_BASE_IDX … #define mmDC_GPIO_DDCVGA_Y … #define mmDC_GPIO_DDCVGA_Y_BASE_IDX … #define mmDC_GPIO_SYNCA_MASK … #define mmDC_GPIO_SYNCA_MASK_BASE_IDX … #define mmDC_GPIO_SYNCA_A … #define mmDC_GPIO_SYNCA_A_BASE_IDX … #define mmDC_GPIO_SYNCA_EN … #define mmDC_GPIO_SYNCA_EN_BASE_IDX … #define mmDC_GPIO_SYNCA_Y … #define mmDC_GPIO_SYNCA_Y_BASE_IDX … #define mmDC_GPIO_GENLK_MASK … #define mmDC_GPIO_GENLK_MASK_BASE_IDX … #define mmDC_GPIO_GENLK_A … #define mmDC_GPIO_GENLK_A_BASE_IDX … #define mmDC_GPIO_GENLK_EN … #define mmDC_GPIO_GENLK_EN_BASE_IDX … #define mmDC_GPIO_GENLK_Y … #define mmDC_GPIO_GENLK_Y_BASE_IDX … #define mmDC_GPIO_HPD_MASK … #define mmDC_GPIO_HPD_MASK_BASE_IDX … #define mmDC_GPIO_HPD_A … #define mmDC_GPIO_HPD_A_BASE_IDX … #define mmDC_GPIO_HPD_EN … #define mmDC_GPIO_HPD_EN_BASE_IDX … #define mmDC_GPIO_HPD_Y … #define mmDC_GPIO_HPD_Y_BASE_IDX … #define mmDC_GPIO_PWRSEQ_MASK … #define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX … #define mmDC_GPIO_PWRSEQ_A … #define mmDC_GPIO_PWRSEQ_A_BASE_IDX … #define mmDC_GPIO_PWRSEQ_EN … #define mmDC_GPIO_PWRSEQ_EN_BASE_IDX … #define mmDC_GPIO_PWRSEQ_Y … #define mmDC_GPIO_PWRSEQ_Y_BASE_IDX … #define mmDC_GPIO_PAD_STRENGTH_1 … #define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX … #define mmDC_GPIO_PAD_STRENGTH_2 … #define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX … #define mmPHY_AUX_CNTL … #define mmPHY_AUX_CNTL_BASE_IDX … #define mmDC_GPIO_I2CPAD_MASK … #define mmDC_GPIO_I2CPAD_MASK_BASE_IDX … #define mmDC_GPIO_I2CPAD_A … #define mmDC_GPIO_I2CPAD_A_BASE_IDX … #define mmDC_GPIO_I2CPAD_EN … #define mmDC_GPIO_I2CPAD_EN_BASE_IDX … #define mmDC_GPIO_I2CPAD_Y … #define mmDC_GPIO_I2CPAD_Y_BASE_IDX … #define mmDC_GPIO_I2CPAD_STRENGTH … #define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX … #define mmDVO_STRENGTH_CONTROL … #define mmDVO_STRENGTH_CONTROL_BASE_IDX … #define mmDVO_VREF_CONTROL … #define mmDVO_VREF_CONTROL_BASE_IDX … #define mmDVO_SKEW_ADJUST … #define mmDVO_SKEW_ADJUST_BASE_IDX … #define mmDC_GPIO_I2S_SPDIF_MASK … #define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX … #define mmDC_GPIO_I2S_SPDIF_A … #define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX … #define mmDC_GPIO_I2S_SPDIF_EN … #define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX … #define mmDC_GPIO_I2S_SPDIF_Y … #define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX … #define mmDC_GPIO_I2S_SPDIF_STRENGTH … #define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX … #define mmDC_GPIO_TX12_EN … #define mmDC_GPIO_TX12_EN_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_0 … #define mmDC_GPIO_AUX_CTRL_0_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_1 … #define mmDC_GPIO_AUX_CTRL_1_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_2 … #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX … #define mmDC_GPIO_RXEN … #define mmDC_GPIO_RXEN_BASE_IDX … #define mmDC_GPIO_PULLUPEN … #define mmDC_GPIO_PULLUPEN_BASE_IDX … // addressBlock: dce_dc_dcio_dcio_dac_dispdec // base address: 0x0 #define mmDAC_MACRO_CNTL_RESERVED0 … #define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDAC_MACRO_CNTL_RESERVED1 … #define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDAC_MACRO_CNTL_RESERVED2 … #define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDAC_MACRO_CNTL_RESERVED3 … #define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX … // addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec // base address: 0x0 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec // base address: 0x0 #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec // base address: 0x0 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec // base address: 0x0 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_VREG_CFG … #define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_DFT_OUT … #define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1 … #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL … #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL_BASE_IDX … // addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec // base address: 0x360 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec // base address: 0x360 #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec // base address: 0x360 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec // base address: 0x360 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_VREG_CFG … #define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_DFT_OUT … #define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1 … #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL … #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL_BASE_IDX … // addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec // base address: 0x6c0 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec // base address: 0x6c0 #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec // base address: 0x6c0 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec // base address: 0x6c0 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_VREG_CFG … #define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_DFT_OUT … #define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1 … #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL … #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL_BASE_IDX … // addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec // base address: 0xa20 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 … #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec // base address: 0xa20 #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 … #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 … #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 … #define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM … #define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT … #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL … #define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_TMDP … #define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS … #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL … #define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 … #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec // base address: 0xa20 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 … #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 … #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 … #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX … // addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec // base address: 0xa20 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 … #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE … #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE … #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_CAL_CTRL … #define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL … #define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_VREG_CFG … #define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_OBSERVE0 … #define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_OBSERVE1 … #define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_DFT_OUT … #define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1 … #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1_BASE_IDX … #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL … #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL_BASE_IDX … // addressBlock: dce_dc_dcio_dcio_zcal_dispdec // base address: 0x0 #define mmZCAL_MACRO_CNTL_RESERVED0 … #define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX … #define mmZCAL_MACRO_CNTL_RESERVED1 … #define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX … #define mmZCAL_MACRO_CNTL_RESERVED2 … #define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX … #define mmZCAL_MACRO_CNTL_RESERVED3 … #define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX … #define mmZCAL_MACRO_CNTL_RESERVED4 … #define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX … // addressBlock: dce_dc_zcal_dc_zcalregs_dispdec // base address: 0x0 #define mmCOMP_EN_CTL … #define mmCOMP_EN_CTL_BASE_IDX … #define mmCOMP_EN_DFX … #define mmCOMP_EN_DFX_BASE_IDX … #define mmZCAL_FUSES … #define mmZCAL_FUSES_BASE_IDX … // addressBlock: vga_vgaseqind // base address: 0x0 #define ixSEQ00 … #define ixSEQ01 … #define ixSEQ02 … #define ixSEQ03 … #define ixSEQ04 … // addressBlock: vga_vgacrtind // base address: 0x0 #define ixCRT00 … #define ixCRT01 … #define ixCRT02 … #define ixCRT03 … #define ixCRT04 … #define ixCRT05 … #define ixCRT06 … #define ixCRT07 … #define ixCRT08 … #define ixCRT09 … #define ixCRT0A … #define ixCRT0B … #define ixCRT0C … #define ixCRT0D … #define ixCRT0E … #define ixCRT0F … #define ixCRT10 … #define ixCRT11 … #define ixCRT12 … #define ixCRT13 … #define ixCRT14 … #define ixCRT15 … #define ixCRT16 … #define ixCRT17 … #define ixCRT18 … #define ixCRT1E … #define ixCRT1F … #define ixCRT22 … // addressBlock: vga_vgagrphind // base address: 0x0 #define ixGRA00 … #define ixGRA01 … #define ixGRA02 … #define ixGRA03 … #define ixGRA04 … #define ixGRA05 … #define ixGRA06 … #define ixGRA07 … #define ixGRA08 … // addressBlock: vga_vgaattrind // base address: 0x0 #define ixATTR00 … #define ixATTR01 … #define ixATTR02 … #define ixATTR03 … #define ixATTR04 … #define ixATTR05 … #define ixATTR06 … #define ixATTR07 … #define ixATTR08 … #define ixATTR09 … #define ixATTR0A … #define ixATTR0B … #define ixATTR0C … #define ixATTR0D … #define ixATTR0E … #define ixATTR0F … #define ixATTR10 … #define ixATTR11 … #define ixATTR12 … #define ixATTR13 … #define ixATTR14 … // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // base address: 0x0 // addressBlock: azendpoint_f2codecind // base address: 0x0 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 … #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY … #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC … #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX … #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO … #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB … #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH … // addressBlock: azendpoint_descriptorind // base address: 0x0 #define ixAUDIO_DESCRIPTOR0 … #define ixAUDIO_DESCRIPTOR1 … #define ixAUDIO_DESCRIPTOR2 … #define ixAUDIO_DESCRIPTOR3 … #define ixAUDIO_DESCRIPTOR4 … #define ixAUDIO_DESCRIPTOR5 … #define ixAUDIO_DESCRIPTOR6 … #define ixAUDIO_DESCRIPTOR7 … #define ixAUDIO_DESCRIPTOR8 … #define ixAUDIO_DESCRIPTOR9 … #define ixAUDIO_DESCRIPTOR10 … #define ixAUDIO_DESCRIPTOR11 … #define ixAUDIO_DESCRIPTOR12 … #define ixAUDIO_DESCRIPTOR13 … // addressBlock: azendpoint_sinkinfoind // base address: 0x0 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID … #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 … #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 … #define ixSINK_DESCRIPTION0 … #define ixSINK_DESCRIPTION1 … #define ixSINK_DESCRIPTION2 … #define ixSINK_DESCRIPTION3 … #define ixSINK_DESCRIPTION4 … #define ixSINK_DESCRIPTION5 … #define ixSINK_DESCRIPTION6 … #define ixSINK_DESCRIPTION7 … #define ixSINK_DESCRIPTION8 … #define ixSINK_DESCRIPTION9 … #define ixSINK_DESCRIPTION10 … #define ixSINK_DESCRIPTION11 … #define ixSINK_DESCRIPTION12 … #define ixSINK_DESCRIPTION13 … #define ixSINK_DESCRIPTION14 … #define ixSINK_DESCRIPTION15 … #define ixSINK_DESCRIPTION16 … #define ixSINK_DESCRIPTION17 … // addressBlock: azf0controller_azinputcrc0resultind // base address: 0x0 #define ixAZALIA_INPUT_CRC0_CHANNEL0 … #define ixAZALIA_INPUT_CRC0_CHANNEL1 … #define ixAZALIA_INPUT_CRC0_CHANNEL2 … #define ixAZALIA_INPUT_CRC0_CHANNEL3 … #define ixAZALIA_INPUT_CRC0_CHANNEL4 … #define ixAZALIA_INPUT_CRC0_CHANNEL5 … #define ixAZALIA_INPUT_CRC0_CHANNEL6 … #define ixAZALIA_INPUT_CRC0_CHANNEL7 … // addressBlock: azf0controller_azinputcrc1resultind // base address: 0x0 #define ixAZALIA_INPUT_CRC1_CHANNEL0 … #define ixAZALIA_INPUT_CRC1_CHANNEL1 … #define ixAZALIA_INPUT_CRC1_CHANNEL2 … #define ixAZALIA_INPUT_CRC1_CHANNEL3 … #define ixAZALIA_INPUT_CRC1_CHANNEL4 … #define ixAZALIA_INPUT_CRC1_CHANNEL5 … #define ixAZALIA_INPUT_CRC1_CHANNEL6 … #define ixAZALIA_INPUT_CRC1_CHANNEL7 … // addressBlock: azf0controller_azcrc0resultind // base address: 0x0 #define ixAZALIA_CRC0_CHANNEL0 … #define ixAZALIA_CRC0_CHANNEL1 … #define ixAZALIA_CRC0_CHANNEL2 … #define ixAZALIA_CRC0_CHANNEL3 … #define ixAZALIA_CRC0_CHANNEL4 … #define ixAZALIA_CRC0_CHANNEL5 … #define ixAZALIA_CRC0_CHANNEL6 … #define ixAZALIA_CRC0_CHANNEL7 … // addressBlock: azf0controller_azcrc1resultind // base address: 0x0 #define ixAZALIA_CRC1_CHANNEL0 … #define ixAZALIA_CRC1_CHANNEL1 … #define ixAZALIA_CRC1_CHANNEL2 … #define ixAZALIA_CRC1_CHANNEL3 … #define ixAZALIA_CRC1_CHANNEL4 … #define ixAZALIA_CRC1_CHANNEL5 … #define ixAZALIA_CRC1_CHANNEL6 … #define ixAZALIA_CRC1_CHANNEL7 … // addressBlock: azinputendpoint_f2codecind // base address: 0x0 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L … #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H … #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … // addressBlock: azroot_f2codecind // base address: 0x0 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID … #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID … #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION … #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS … #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES … // addressBlock: azf0stream0_streamind // base address: 0x0 #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream1_streamind // base address: 0x0 #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream2_streamind // base address: 0x0 #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream3_streamind // base address: 0x0 #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream4_streamind // base address: 0x0 #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream5_streamind // base address: 0x0 #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream6_streamind // base address: 0x0 #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream7_streamind // base address: 0x0 #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream8_streamind // base address: 0x0 #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream9_streamind // base address: 0x0 #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream10_streamind // base address: 0x0 #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream11_streamind // base address: 0x0 #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream12_streamind // base address: 0x0 #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream13_streamind // base address: 0x0 #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream14_streamind // base address: 0x0 #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0stream15_streamind // base address: 0x0 #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL … #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL … #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT … #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT … #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT … // addressBlock: azf0endpoint0_endpointind // base address: 0x0 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint1_endpointind // base address: 0x0 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint2_endpointind // base address: 0x0 #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint3_endpointind // base address: 0x0 #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint4_endpointind // base address: 0x0 #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint5_endpointind // base address: 0x0 #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint6_endpointind // base address: 0x0 #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint7_endpointind // base address: 0x0 #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0inputendpoint0_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint1_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint2_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint3_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint4_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint5_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint6_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint7_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … #endif
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