/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD */ #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ #include "dm_services.h" /* macro for register read/write * user of macro need to define * * CTX ==> macro to ptr to dc_context * eg. aud110->base.ctx * * REG ==> macro to location of register offset * eg. aud110->regs->reg */ #define REG_READ(reg_name) … #define REG_WRITE(reg_name, value) … #ifdef REG_SET #undef REG_SET #endif #ifdef REG_GET #undef REG_GET #endif /* macro to set register fields. */ #define REG_SET_N(reg_name, n, initial_val, ...) … #define FN(reg_name, field) … #define REG_SET(reg_name, initial_val, field, val) … #define REG_SET_2(reg, init_value, f1, v1, f2, v2) … #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) … #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) … #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f5, v5) … #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f5, v5, f6, v6) … #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f5, v5, f6, v6, f7, v7) … #define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f5, v5, f6, v6, f7, v7, f8, v8) … #define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ v5, f6, v6, f7, v7, f8, v8, f9, v9) … #define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) … /* macro to get register fields * read given register and fill in field value in output parameter */ #define REG_GET(reg_name, field, val) … #define REG_GET_2(reg_name, f1, v1, f2, v2) … #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) … #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) … #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) … #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) … #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) … #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) … /* macro to poll and wait for a register field to read back given value */ #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) … /* macro to update (read, modify, write) register fields */ #define REG_UPDATE_N(reg_name, n, ...) … #define REG_UPDATE(reg_name, field, val) … #define REG_UPDATE_2(reg, f1, v1, f2, v2) … #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) … #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) … #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) … #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) … #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) … #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) … #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) … #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) … #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ v10, f11, v11, f12, v12, f13, v13, f14, v14) … #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19) … #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19, f20, v20) … /* macro to update a register field to specified values in given sequences. * useful when toggling bits */ #define REG_UPDATE_SEQ_2(reg, f1, v1, f2, v2) … #define REG_UPDATE_SEQ_3(reg, f1, v1, f2, v2, f3, v3) … uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr, uint8_t shift, uint32_t mask, uint32_t *field_value); uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2); uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3); uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4); uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5); uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6); uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7); uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7, uint8_t shift8, uint32_t mask8, uint32_t *field_value8); /* indirect register access */ #define IX_REG_SET_N(index_reg_name, data_reg_name, index, n, initial_val, ...) … #define IX_REG_SET_2(index_reg_name, data_reg_name, index, init_value, f1, v1, f2, v2) … #define IX_REG_READ(index_reg_name, data_reg_name, index) … #define IX_REG_GET_N(index_reg_name, data_reg_name, index, n, ...) … #define IX_REG_GET(index_reg_name, data_reg_name, index, field, val) … #define IX_REG_UPDATE_N(index_reg_name, data_reg_name, index, n, ...) … #define IX_REG_UPDATE_2(index_reg_name, data_reg_name, index, f1, v1, f2, v2) … void generic_write_indirect_reg(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, uint32_t data); uint32_t generic_read_indirect_reg(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index); uint32_t generic_indirect_reg_get(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, int n, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, ...); uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); /* indirect register access * underlying implementation determines which index/data pair to be used * in a synchronous way */ #define IX_REG_SET_N_SYNC(index, n, initial_val, ...) … #define IX_REG_SET_2_SYNC(index, init_value, f1, v1, f2, v2) … #define IX_REG_GET_N_SYNC(index, n, ...) … #define IX_REG_GET_SYNC(index, field, val) … uint32_t generic_indirect_reg_get_sync(const struct dc_context *ctx, uint32_t index, int n, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, ...); uint32_t generic_indirect_reg_update_ex_sync(const struct dc_context *ctx, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); /* register offload macros * * instead of MMIO to register directly, in some cases we want * to gather register sequence and execute the register sequence * from another thread so we optimize time required for lengthy ops */ /* start gathering register sequence */ #define REG_SEQ_START() … /* start execution of register sequence gathered since REG_SEQ_START */ #define REG_SEQ_SUBMIT() … /* wait for the last REG_SEQ_SUBMIT to finish */ #define REG_SEQ_WAIT_DONE() … #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */
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