/* * Copyright 2012-16 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef __DAL_CLK_MGR_H__ #define __DAL_CLK_MGR_H__ #include "dc.h" #include "dm_pp_smu.h" #define DCN_MINIMUM_DISPCLK_Khz … #define DCN_MINIMUM_DPPCLK_Khz … /* Constants */ #define DDR4_DRAM_WIDTH … #define WM_A … #define WM_B … #define WM_C … #define WM_D … #define WM_SET_COUNT … #define WM_1A … #define WM_1B … #define DCN_MINIMUM_DISPCLK_Khz … #define DCN_MINIMUM_DPPCLK_Khz … struct dcn3_clk_internal { … }; struct dcn35_clk_internal { … }; struct dcn301_clk_internal { … }; /* Will these bw structures be ASIC specific? */ #define MAX_NUM_DPM_LVL … #define WM_SET_COUNT … struct clk_limit_table_entry { … }; struct clk_limit_num_entries { … }; /* This table is contiguous */ struct clk_limit_table { … }; struct wm_range_table_entry { … }; struct nv_wm_range_entry { … }; struct clk_log_info { … }; struct clk_state_registers_and_bypass { … }; struct rv1_clk_internal { … }; struct rn_clk_internal { … }; /* For dtn logging and debugging */ struct clk_state_registers { … }; /* TODO: combine this with the above */ struct clk_bypass { … }; /* * This table is not contiguous, can have holes, each * entry correspond to one set of WM. For example if * we have 2 DPM and LPDDR, we will WM set A, B and * D occupied, C will be emptry. */ struct wm_table { … }; struct dummy_pstate_entry { … }; struct clk_bw_params { … }; /* Public interfaces */ struct clk_states { … }; struct clk_mgr_funcs { … }; struct clk_mgr { … }; /* forward declarations */ struct dccg; struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr); void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr); #endif /* __DAL_CLK_MGR_H__ */
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