/* * Copyright 2018 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef __DAL_CLK_MGR_INTERNAL_H__ #define __DAL_CLK_MGR_INTERNAL_H__ #include "clk_mgr.h" #include "dc.h" /* * only thing needed from here is MEMORY_TYPE_MULTIPLIER_CZ, which is also * used in resource, perhaps this should be defined somewhere more common. */ #include "resource.h" /* Starting DID for each range */ enum dentist_base_divider_id { … }; /* Starting point and step size for each divider range.*/ enum dentist_divider_range { … }; /* *************************************************************************************** ****************** Clock Manager Private Macros and Defines *************************** *************************************************************************************** */ /* Macros */ #define TO_CLK_MGR_INTERNAL(clk_mgr) … #define CTX … #define DC_LOGGER … #define CLK_BASE(inst) … #define CLK_SRI(reg_name, block, inst) … #define CLK_COMMON_REG_LIST_DCE_BASE() … #if defined(CONFIG_DRM_AMD_DC_SI) #define CLK_COMMON_REG_LIST_DCE60_BASE() … #endif #define CLK_COMMON_REG_LIST_DCN_BASE() … #define CLK_COMMON_REG_LIST_DCN_201() … #define CLK_REG_LIST_NV10() … #define CLK_REG_LIST_DCN3() … #define CLK_SF(reg_name, field_name, post_fix) … #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) … #if defined(CONFIG_DRM_AMD_DC_SI) #define CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) … #endif #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) … #define CLK_MASK_SH_LIST_RV1(mask_sh) … #define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) … #define CLK_MASK_SH_LIST_NV10(mask_sh) … #define CLK_COMMON_MASK_SH_LIST_DCN201_BASE(mask_sh) … #define CLK_REG_LIST_DCN32() … #define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) … #define CLK_REG_LIST_DCN321() … #define CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) … #define CLK_REG_LIST_DCN401() … #define CLK_COMMON_MASK_SH_LIST_DCN401(mask_sh) … #define CLK_REG_FIELD_LIST(type) … #define CLK20_REG_FIELD_LIST(type) … /* *************************************************************************************** ****************** Clock Manager Private Structures *********************************** *************************************************************************************** */ struct clk_mgr_registers { … }; struct clk_mgr_shift { … }; struct clk_mgr_mask { … }; enum clock_type { … }; struct state_dependent_clocks { … }; struct clk_mgr_internal { … }; struct clk_mgr_internal_funcs { … }; /* *************************************************************************************** ****************** Clock Manager Level Helper functions ******************************* *************************************************************************************** */ static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk) { … } static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support) { … } static inline int khz_to_mhz_ceil(int khz) { … } static inline int khz_to_mhz_floor(int khz) { … } int clk_mgr_helper_get_active_display_cnt( struct dc *dc, struct dc_state *context); int clk_mgr_helper_get_active_plane_cnt( struct dc *dc, struct dc_state *context); #endif //__DAL_CLK_MGR_INTERNAL_H__
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