/* * Copyright 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef _DCN32_RESOURCE_H_ #define _DCN32_RESOURCE_H_ #include "core_types.h" #define DCN3_2_DEFAULT_DET_SIZE … #define DCN3_2_MAX_DET_SIZE … #define DCN3_2_MIN_DET_SIZE … #define DCN3_2_MIN_COMPBUF_SIZE_KB … #define DCN3_2_DET_SEG_SIZE … #define DCN3_2_MALL_MBLK_SIZE_BYTES … #define DCN3_2_MBLK_WIDTH … #define DCN3_2_MBLK_HEIGHT_4BPE … #define DCN3_2_MBLK_HEIGHT_8BPE … #define DCN3_2_DCFCLK_DS_INIT_KHZ … #define SUBVP_HIGH_REFRESH_LIST_LEN … #define SUBVP_ACTIVE_MARGIN_LIST_LEN … #define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ … #define DCN3_2_VMIN_DISPCLK_HZ … #define MIN_SUBVP_DCFCLK_KHZ … #define TO_DCN32_RES_POOL(pool) … extern struct _vcs_dpi_ip_params_st dcn3_2_ip; extern struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc; struct subvp_high_refresh_list { … }; struct subvp_active_margin_list { … }; struct dcn32_resource_pool { … }; struct resource_pool *dcn32_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc); struct panel_cntl *dcn32_panel_cntl_create( const struct panel_cntl_init_data *init_data); bool dcn32_acquire_post_bldn_3dlut( struct resource_context *res_ctx, const struct resource_pool *pool, int mpcc_id, struct dc_3dlut **lut, struct dc_transfer_func **shaper); bool dcn32_release_post_bldn_3dlut( struct resource_context *res_ctx, const struct resource_pool *pool, struct dc_3dlut **lut, struct dc_transfer_func **shaper); void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int index); bool dcn32_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate); int dcn32_populate_dml_pipes_from_context( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate); void dcn32_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel); uint32_t dcn32_helper_calculate_mall_bytes_for_cursor( struct dc *dc, struct pipe_ctx *pipe_ctx, bool ignore_cursor_buf); uint32_t dcn32_helper_calculate_num_ways_for_subvp( struct dc *dc, struct dc_state *context); void dcn32_merge_pipes_for_subvp(struct dc *dc, struct dc_state *context); bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc, struct dc_state *context); bool dcn32_subvp_in_use(struct dc *dc, struct dc_state *context); bool dcn32_mpo_in_use(struct dc_state *context); bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context); bool dcn32_is_center_timing(struct pipe_ctx *pipe); bool dcn32_is_psr_capable(struct pipe_ctx *pipe); int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe( const struct resource_context *cur_res_ctx, struct resource_context *new_res_ctx, const struct resource_pool *pool, const struct pipe_ctx *new_opp_head); struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *opp_head_pipe); struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *otg_master); void dcn32_release_pipe(struct dc_state *context, struct pipe_ctx *pipe, const struct resource_pool *pool); void dcn32_determine_det_override(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes); void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes); struct dc_stream_state *dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context); bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe); bool dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe); unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans); double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context); bool dcn32_check_native_scaling_for_res(struct pipe_ctx *pipe, unsigned int width, unsigned int height); bool dcn32_subvp_drr_admissable(struct dc *dc, struct dc_state *context); bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int vlevel); void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes); void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context); unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes); /* definitions for run time init of reg offsets */ /* CLK SRC */ #define CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) … /* ABM */ #define ABM_DCN32_REG_LIST_RI(id) … /* Audio */ #define AUD_COMMON_REG_LIST_RI(id) … \ /* VPG */ #define VPG_DCN3_REG_LIST_RI(id) … /* AFMT */ #define AFMT_DCN3_REG_LIST_RI(id) … /* APG */ #define APG_DCN31_REG_LIST_RI(id) … /* Stream encoder */ #define SE_DCN32_REG_LIST_RI(id) … /* Aux regs */ #define AUX_REG_LIST_RI(id) … #define DCN2_AUX_REG_LIST_RI(id) … /* HDP */ #define HPD_REG_LIST_RI(id) … /* Link encoder */ #define LE_DCN3_REG_LIST_RI(id) … #define LE_DCN31_REG_LIST_RI(id) … #define UNIPHY_DCN2_REG_LIST_RI(id, phyid) … /* HPO DP stream encoder */ #define DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) … /* HPO DP link encoder regs */ #define DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) … /* DPP */ #define DPP_REG_LIST_DCN30_COMMON_RI(id) … /* OPP */ #define OPP_REG_LIST_DCN_RI(id) … \ #define OPP_REG_LIST_DCN10_RI(id) … #define OPP_DPG_REG_LIST_RI(id) … #define OPP_REG_LIST_DCN30_RI(id) … /* Aux engine regs */ #define AUX_COMMON_REG_LIST0_RI(id) … /* DWBC */ #define DWBC_COMMON_REG_LIST_DCN30_RI(id) … /* MCIF */ #define MCIF_WB_COMMON_REG_LIST_DCN32_RI(inst) … /* DSC */ #define DSC_REG_LIST_DCN20_RI(id) … /* MPC */ #define MPC_DWB_MUX_REG_LIST_DCN3_0_RI(inst) … #define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0_RI(inst) … #define MPC_OUT_MUX_REG_LIST_DCN3_0_RI(inst) … #define MPC_COMMON_REG_LIST_DCN1_0_RI(inst) … #define MPC_REG_LIST_DCN3_0_RI(inst) … #define MPC_REG_LIST_DCN3_2_RI(inst) … /* OPTC */ #define OPTC_COMMON_REG_LIST_DCN3_2_RI(inst) … /* HUBP */ #define HUBP_REG_LIST_DCN_VM_RI(id) … #define HUBP_REG_LIST_DCN_RI(id) … #define HUBP_REG_LIST_DCN2_COMMON_RI(id) … #define HUBP_REG_LIST_DCN21_RI(id) … #define HUBP_REG_LIST_DCN30_RI(id) … #define HUBP_REG_LIST_DCN32_RI(id) … /* HUBBUB */ #define HUBBUB_REG_LIST_DCN32_RI(id) … /* DCCG */ #define DCCG_REG_LIST_DCN32_RI() … /* VMID */ #define DCN20_VMID_REG_LIST_RI(id) … /* I2C HW */ #define I2C_HW_ENGINE_COMMON_REG_LIST_RI(id) … #define I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) … #endif /* _DCN32_RESOURCE_H_ */
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