/* SPDX-License-Identifier: MIT */ /* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef _DCN35_RESOURCE_H_ #define _DCN35_RESOURCE_H_ #include "core_types.h" #define DCN3_5_VMIN_DISPCLK_HZ … #define TO_DCN35_RES_POOL(pool) … extern struct _vcs_dpi_ip_params_st dcn3_5_ip; extern struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc; struct dcn35_resource_pool { … }; struct resource_pool *dcn35_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc); /* Defs for runtime init of registers */ #define OPP_REG_LIST_DCN20_RI(id) … #define OPP_REG_LIST_DCN35_RI(id) … #define VPG_DCN31_REG_LIST_RI(id) … #define AFMT_DCN31_REG_LIST_RI(id) … /* Stream encoder */ #define SE_DCN35_REG_LIST_RI(id) … #define LE_DCN35_REG_LIST_RI(id) … #define MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(inst) … #define HWSEQ_DCN35_REG_LIST() … /* OPTC */ #define OPTC_COMMON_REG_LIST_DCN3_5_RI(inst) … /* DPP */ #define DPP_REG_LIST_DCN35_RI(id) … #endif /* _DCN35_RESOURCE_H_ */
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