// SPDX-License-Identifier: MIT /* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "clk_mgr.h" #include "resource.h" #include "dcn321_fpu.h" #include "dcn32/dcn32_resource.h" #include "dcn321/dcn321_resource.h" #include "dml/dcn32/display_mode_vba_util_32.h" #define DCN3_2_DEFAULT_DET_SIZE … struct _vcs_dpi_ip_params_st dcn3_21_ip = …; struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = …; static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry) { … } static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry) { … } static void dcn321_insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, struct _vcs_dpi_voltage_scaling_st *entry) { … } static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries, unsigned int index) { … } static void swap_table_entries(struct _vcs_dpi_voltage_scaling_st *first_entry, struct _vcs_dpi_voltage_scaling_st *second_entry) { … } /* * sort_entries_with_same_bw - Sort entries sharing the same bandwidth by DCFCLK */ static void sort_entries_with_same_bw(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) { … } /* * remove_inconsistent_entries - Ensure entries with the same bandwidth have MEMCLK and FCLK monotonically increasing * and remove entries that do not follow this order */ static void remove_inconsistent_entries(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) { … } /* * override_max_clk_values - Overwrite the max clock frequencies with the max DC mode timings * Input: * max_clk_limit - struct containing the desired clock timings * Output: * curr_clk_limit - struct containing the timings that need to be overwritten * Return: 0 upon success, non-zero for failure */ static int override_max_clk_values(struct clk_limit_table_entry *max_clk_limit, struct clk_limit_table_entry *curr_clk_limit) { … } static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk_bw_params *bw_params, struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries) { … } static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, unsigned int *optimal_dcfclk, unsigned int *optimal_fclk) { … } /** dcn321_update_bw_bounding_box * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet * with actual values as per dGPU SKU: * -with passed few options from dc->config * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW) * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC) * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different * clocks (which might differ for certain dGPU SKU of the same ASIC) */ void dcn321_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) { … }