linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

// SPDX-License-Identifier: MIT
/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */
#include "resource.h"
#include "dcn35_fpu.h"
#include "dcn31/dcn31_resource.h"
#include "dcn32/dcn32_resource.h"
#include "dcn35/dcn35_resource.h"
#include "dml/dcn31/dcn31_fpu.h"
#include "dml/dml_inline_defs.h"

#include "link.h"

#define DC_LOGGER_INIT(logger) …

struct _vcs_dpi_ip_params_st dcn3_5_ip = …;

struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = …;

void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)
{ … }


/*
 * dcn35_update_bw_bounding_box
 *
 * This would override some dcn3_5 ip_or_soc initial parameters hardcoded from
 * spreadsheet with actual values as per dGPU SKU:
 * - with passed few options from dc->config
 * - with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might
 *   need to get it from PM FW)
 * - with passed latency values (passed in ns units) in dc-> bb override for
 *   debugging purposes
 * - with passed latencies from VBIOS (in 100_ns units) if available for
 *   certain dGPU SKU
 * - with number of DRAM channels from VBIOS (which differ for certain dGPU SKU
 *   of the same ASIC)
 * - clocks levels with passed clk_table entries from Clk Mgr as reported by PM
 *   FW for different clocks (which might differ for certain dGPU SKU of the
 *   same ASIC)
 */
void dcn35_update_bw_bounding_box_fpu(struct dc *dc,
				      struct clk_bw_params *bw_params)
{ … }

static bool is_dual_plane(enum surface_pixel_format format)
{ … }

/*
 * micro_sec_to_vert_lines () - converts time to number of vertical lines for a given timing
 *
 * @param: num_us: number of microseconds
 * @return: number of vertical lines. If exact number of vertical lines is not found then
 *          it will round up to next number of lines to guarantee num_us
 */
static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_timing *timing)
{ … }

static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing)
{ … }

int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc,
					      struct dc_state *context,
					      display_e2e_pipe_params_st *pipes,
					      bool fast_validate)
{ … }

void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)
{ … }