/* * Copyright 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef __DCN30_CLK_MGR_H__ #define __DCN30_CLK_MGR_H__ //CLK1_CLK_PLL_REQ #ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT #define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT … #define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT … #define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT … #define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK … #define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK … #define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK … //CLK1_CLK0_DFS_CNTL #define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT … #define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK … /*DPREF clock related*/ #define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT … #define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK … #define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT … #define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK … #define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT … #define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK … #define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT … #define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK … //CLK3_0_CLK3_CLK_PLL_REQ #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT … #define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT … #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT … #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK … #define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK … #define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK … #define mmCLK0_CLK2_DFS_CNTL … #define mmCLK00_CLK0_CLK2_DFS_CNTL … #define mmCLK01_CLK0_CLK2_DFS_CNTL … #define mmCLK02_CLK0_CLK2_DFS_CNTL … #define mmCLK0_CLK3_DFS_CNTL … #define mmCLK00_CLK0_CLK3_DFS_CNTL … #define mmCLK01_CLK0_CLK3_DFS_CNTL … #define mmCLK02_CLK0_CLK3_DFS_CNTL … #define mmCLK03_CLK0_CLK3_DFS_CNTL … #define mmCLK0_CLK_PLL_REQ … #define mmCLK00_CLK0_CLK_PLL_REQ … #define mmCLK01_CLK0_CLK_PLL_REQ … #define mmCLK02_CLK0_CLK_PLL_REQ … #define mmCLK03_CLK0_CLK_PLL_REQ … #define mmCLK1_CLK_PLL_REQ … #define mmCLK10_CLK1_CLK_PLL_REQ … #define mmCLK11_CLK1_CLK_PLL_REQ … #define mmCLK12_CLK1_CLK_PLL_REQ … #define mmCLK13_CLK1_CLK_PLL_REQ … #define mmCLK2_CLK_PLL_REQ … /*AMCLK*/ #define mmCLK11_CLK1_CLK0_DFS_CNTL … #define mmCLK11_CLK1_CLK_PLL_REQ … #endif void dcn3_init_clocks(struct clk_mgr *clk_mgr_base); void dcn3_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu, struct dccg *dccg); void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr); #endif //__DCN30_CLK_MGR_H__
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