/* * Copyright (C) 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _dcn_2_0_3_OFFSET_HEADER #define _dcn_2_0_3_OFFSET_HEADER // addressBlock: dce_dc_dccg_dccg_dispdec // base address: 0x0 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL … #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmPHYPLLB_PIXCLK_RESYNC_CNTL … #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX … #define mmDP_DTO_DBUF_EN … #define mmDP_DTO_DBUF_EN_BASE_IDX … #define mmDPREFCLK_CGTT_BLK_CTRL_REG … #define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmREFCLK_CNTL … #define mmREFCLK_CNTL_BASE_IDX … #define mmREFCLK_CGTT_BLK_CTRL_REG … #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmDCCG_PERFMON_CNTL2 … #define mmDCCG_PERFMON_CNTL2_BASE_IDX … #define mmDCCG_DS_DTO_INCR … #define mmDCCG_DS_DTO_INCR_BASE_IDX … #define mmDCCG_DS_DTO_MODULO … #define mmDCCG_DS_DTO_MODULO_BASE_IDX … #define mmDCCG_DS_CNTL … #define mmDCCG_DS_CNTL_BASE_IDX … #define mmDCCG_DS_HW_CAL_INTERVAL … #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX … #define mmDPREFCLK_CNTL … #define mmDPREFCLK_CNTL_BASE_IDX … #define mmDCE_VERSION … #define mmDCE_VERSION_BASE_IDX … #define mmDCCG_GTC_CNTL … #define mmDCCG_GTC_CNTL_BASE_IDX … #define mmDCCG_GTC_DTO_INCR … #define mmDCCG_GTC_DTO_INCR_BASE_IDX … #define mmDCCG_GTC_DTO_MODULO … #define mmDCCG_GTC_DTO_MODULO_BASE_IDX … #define mmDCCG_GTC_CURRENT … #define mmDCCG_GTC_CURRENT_BASE_IDX … #define mmDSCCLK0_DTO_PARAM … #define mmDSCCLK0_DTO_PARAM_BASE_IDX … #define mmMILLISECOND_TIME_BASE_DIV … #define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX … #define mmDISPCLK_FREQ_CHANGE_CNTL … #define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX … #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL … #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX … #define mmDCCG_PERFMON_CNTL … #define mmDCCG_PERFMON_CNTL_BASE_IDX … #define mmDCCG_GATE_DISABLE_CNTL … #define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX … #define mmDISPCLK_CGTT_BLK_CTRL_REG … #define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmSOCCLK_CGTT_BLK_CTRL_REG … #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmDCCG_CAC_STATUS … #define mmDCCG_CAC_STATUS_BASE_IDX … #define mmMICROSECOND_TIME_BASE_DIV … #define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX … #define mmDCCG_GATE_DISABLE_CNTL2 … #define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX … #define mmSYMCLK_CGTT_BLK_CTRL_REG … #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmDCCG_DISP_CNTL_REG … #define mmDCCG_DISP_CNTL_REG_BASE_IDX … #define mmOTG0_PIXEL_RATE_CNTL … #define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO0_PHASE … #define mmDP_DTO0_PHASE_BASE_IDX … #define mmDP_DTO0_MODULO … #define mmDP_DTO0_MODULO_BASE_IDX … #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL … #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmOTG1_PIXEL_RATE_CNTL … #define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX … #define mmDP_DTO1_PHASE … #define mmDP_DTO1_PHASE_BASE_IDX … #define mmDP_DTO1_MODULO … #define mmDP_DTO1_MODULO_BASE_IDX … #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL … #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX … #define mmDPPCLK_CGTT_BLK_CTRL_REG … #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX … #define mmDPPCLK0_DTO_PARAM … #define mmDPPCLK0_DTO_PARAM_BASE_IDX … #define mmDPPCLK1_DTO_PARAM … #define mmDPPCLK1_DTO_PARAM_BASE_IDX … #define mmDPPCLK2_DTO_PARAM … #define mmDPPCLK2_DTO_PARAM_BASE_IDX … #define mmDPPCLK3_DTO_PARAM … #define mmDPPCLK3_DTO_PARAM_BASE_IDX … #define mmDCCG_CAC_STATUS2 … #define mmDCCG_CAC_STATUS2_BASE_IDX … #define mmSYMCLKA_CLOCK_ENABLE … #define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX … #define mmSYMCLKB_CLOCK_ENABLE … #define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX … #define mmDCCG_SOFT_RESET … #define mmDCCG_SOFT_RESET_BASE_IDX … #define mmDSCCLK_DTO_CTRL … #define mmDSCCLK_DTO_CTRL_BASE_IDX … #define mmDCCG_AUDIO_DTO_SOURCE … #define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX … #define mmDCCG_AUDIO_DTO0_PHASE … #define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX … #define mmDCCG_AUDIO_DTO0_MODULE … #define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX … #define mmDCCG_AUDIO_DTO1_PHASE … #define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX … #define mmDCCG_AUDIO_DTO1_MODULE … #define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX … #define mmDCCG_VSYNC_OTG0_LATCH_VALUE … #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX … #define mmDCCG_VSYNC_OTG1_LATCH_VALUE … #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX … #define mmDCCG_VSYNC_OTG2_LATCH_VALUE … #define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX … #define mmDCCG_VSYNC_OTG3_LATCH_VALUE … #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX … #define mmDCCG_VSYNC_OTG4_LATCH_VALUE … #define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX … #define mmDCCG_VSYNC_OTG5_LATCH_VALUE … #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX … #define mmDPPCLK_DTO_CTRL … #define mmDPPCLK_DTO_CTRL_BASE_IDX … #define mmDCCG_VSYNC_CNT_CTRL … #define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX … #define mmDCCG_VSYNC_CNT_INT_CTRL … #define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX … // addressBlock: dce_dc_dccg_dccg_dfs_dispdec // base address: 0x0 #define mmDENTIST_DISPCLK_CNTL … #define mmDENTIST_DISPCLK_CNTL_BASE_IDX … // addressBlock: dce_dc_dmu_rbbmif_dispdec // base address: 0x0 #define mmRBBMIF_TIMEOUT … #define mmRBBMIF_TIMEOUT_BASE_IDX … #define mmRBBMIF_STATUS … #define mmRBBMIF_STATUS_BASE_IDX … #define mmRBBMIF_STATUS_2 … #define mmRBBMIF_STATUS_2_BASE_IDX … #define mmRBBMIF_INT_STATUS … #define mmRBBMIF_INT_STATUS_BASE_IDX … #define mmRBBMIF_TIMEOUT_DIS … #define mmRBBMIF_TIMEOUT_DIS_BASE_IDX … #define mmRBBMIF_TIMEOUT_DIS_2 … #define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX … #define mmRBBMIF_STATUS_FLAG … #define mmRBBMIF_STATUS_FLAG_BASE_IDX … // addressBlock: dce_dc_hda_az_misc_dispdec // base address: 0x0 #define mmAZ_CLOCK_CNTL … #define mmAZ_CLOCK_CNTL_BASE_IDX … // addressBlock: dce_dc_hda_azf0endpoint0_dispdec // base address: 0x0 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0endpoint1_dispdec // base address: 0x18 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX … #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA … #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0controller_dispdec // base address: 0x0 #define mmAZALIA_CONTROLLER_CLOCK_GATING … #define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX … #define mmAZALIA_AUDIO_DTO … #define mmAZALIA_AUDIO_DTO_BASE_IDX … #define mmAZALIA_AUDIO_DTO_CONTROL … #define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX … #define mmAZALIA_SOCCLK_CONTROL … #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX … #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE … #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX … #define mmAZALIA_DATA_DMA_CONTROL … #define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX … #define mmAZALIA_BDL_DMA_CONTROL … #define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX … #define mmAZALIA_RIRB_AND_DP_CONTROL … #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX … #define mmAZALIA_CORB_DMA_CONTROL … #define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX … #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER … #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX … #define mmAZALIA_CYCLIC_BUFFER_SYNC … #define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX … #define mmAZALIA_GLOBAL_CAPABILITIES … #define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX … #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY … #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX … #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL … #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX … #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY … #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL0 … #define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL1 … #define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL2 … #define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX … #define mmAZALIA_INPUT_CRC0_CONTROL3 … #define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX … #define mmAZALIA_INPUT_CRC0_RESULT … #define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL0 … #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL1 … #define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL2 … #define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX … #define mmAZALIA_INPUT_CRC1_CONTROL3 … #define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX … #define mmAZALIA_INPUT_CRC1_RESULT … #define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX … #define mmAZALIA_MEM_PWR_CTRL … #define mmAZALIA_MEM_PWR_CTRL_BASE_IDX … #define mmAZALIA_MEM_PWR_STATUS … #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_hda_azf0root_dispdec // base address: 0x0 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID … #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX … #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL … #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL … #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES … #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION … #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX … #define mmREG_DC_AUDIO_PORT_CONNECTIVITY … #define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX … #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY … #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX … // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec // base address: 0x0 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec // base address: 0x10 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX … #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX … #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA … #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX … // addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec // base address: 0x0 #define mmDCHUBBUB_RET_PATH_DCC_CFG … #define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 … #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX … #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 … #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX … #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL … #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX … #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS … #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX … #define mmDCHUBBUB_CRC_CTRL … #define mmDCHUBBUB_CRC_CTRL_BASE_IDX … #define mmDCHUBBUB_CRC0_VAL_R_G … #define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX … #define mmDCHUBBUB_CRC0_VAL_B_A … #define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX … #define mmDCHUBBUB_CRC1_VAL_R_G … #define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX … #define mmDCHUBBUB_CRC1_VAL_B_A … #define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX … // addressBlock: dce_dc_dchubbub_hubbub_dispdec // base address: 0x0 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND … #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX … #define mmDCHUBBUB_ARB_SAT_LEVEL … #define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX … #define mmDCHUBBUB_ARB_QOS_FORCE … #define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX … #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL … #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D … #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D … #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D … #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX … #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL … #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX … #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE … #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX … #define mmDCHUBBUB_GLOBAL_TIMER_CNTL … #define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX … #define mmVTG0_CONTROL … #define mmVTG0_CONTROL_BASE_IDX … #define mmVTG1_CONTROL … #define mmVTG1_CONTROL_BASE_IDX … #define mmDCHUBBUB_SOFT_RESET … #define mmDCHUBBUB_SOFT_RESET_BASE_IDX … #define mmDCHUBBUB_CLOCK_CNTL … #define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX … #define mmDCFCLK_CNTL … #define mmDCFCLK_CNTL_BASE_IDX … #define mmDCHUBBUB_VLINE_SNAPSHOT … #define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX … #define mmDCHUBBUB_CTRL_STATUS … #define mmDCHUBBUB_CTRL_STATUS_BASE_IDX … #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 … #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX … #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 … #define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX … #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS … #define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX … #define mmDCHUBBUB_TEST_DEBUG_INDEX … #define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX … #define mmDCHUBBUB_TEST_DEBUG_DATA … #define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX … #define mmFMON_CTRL … #define mmFMON_CTRL_BASE_IDX … // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec // base address: 0x0 #define mmHUBP0_DCSURF_SURFACE_CONFIG … #define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX … #define mmHUBP0_DCSURF_ADDR_CONFIG … #define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX … #define mmHUBP0_DCSURF_TILING_CONFIG … #define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX … #define mmHUBP0_DCSURF_PRI_VIEWPORT_START … #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION … #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C … #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP0_DCSURF_SEC_VIEWPORT_START … #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION … #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C … #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG … #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C … #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define mmHUBP0_DCHUBP_CNTL … #define mmHUBP0_DCHUBP_CNTL_BASE_IDX … #define mmHUBP0_HUBP_CLK_CNTL … #define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX … #define mmHUBP0_HUBPREQ_DEBUG_DB … #define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX … #define mmHUBP0_HUBPREQ_DEBUG … #define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX … #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec // base address: 0x0 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH … #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C … #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL … #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX … #define mmHUBPREQ0_DCSURF_FLIP_CONTROL … #define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX … #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 … #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT … #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C … #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ0_DCN_EXPANSION_MODE … #define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX … #define mmHUBPREQ0_DCN_TTU_QOS_WM … #define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX … #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL … #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 … #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 … #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 … #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 … #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 … #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 … #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ0_BLANK_OFFSET_0 … #define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX … #define mmHUBPREQ0_BLANK_OFFSET_1 … #define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX … #define mmHUBPREQ0_DST_DIMENSIONS … #define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX … #define mmHUBPREQ0_DST_AFTER_SCALER … #define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX … #define mmHUBPREQ0_PREFETCH_SETTINGS … #define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX … #define mmHUBPREQ0_PREFETCH_SETTINGS_C … #define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX … #define mmHUBPREQ0_VBLANK_PARAMETERS_0 … #define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ0_VBLANK_PARAMETERS_1 … #define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ0_VBLANK_PARAMETERS_2 … #define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ0_VBLANK_PARAMETERS_3 … #define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ0_VBLANK_PARAMETERS_4 … #define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ0_FLIP_PARAMETERS_0 … #define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ0_FLIP_PARAMETERS_2 … #define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_4 … #define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_5 … #define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_6 … #define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX … #define mmHUBPREQ0_NOM_PARAMETERS_7 … #define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX … #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE … #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX … #define mmHUBPREQ0_PER_LINE_DELIVERY … #define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX … #define mmHUBPREQ0_CURSOR_SETTINGS … #define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX … #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ … #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT … #define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX … #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL … #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS … #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec // base address: 0x0 #define mmHUBPRET0_HUBPRET_CONTROL … #define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX … #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL … #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS … #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 … #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 … #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE0 … #define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE1 … #define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX … #define mmHUBPRET0_HUBPRET_INTERRUPT … #define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE … #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS … #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec // base address: 0x0 #define mmCURSOR0_0_CURSOR_CONTROL … #define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX … #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS … #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH … #define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR0_0_CURSOR_SIZE … #define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX … #define mmCURSOR0_0_CURSOR_POSITION … #define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX … #define mmCURSOR0_0_CURSOR_HOT_SPOT … #define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX … #define mmCURSOR0_0_CURSOR_STEREO_CONTROL … #define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX … #define mmCURSOR0_0_CURSOR_DST_OFFSET … #define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX … #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL … #define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS … #define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX … #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH … #define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR0_0_DMDATA_ADDRESS_LOW … #define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX … #define mmCURSOR0_0_DMDATA_CNTL … #define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX … #define mmCURSOR0_0_DMDATA_QOS_CNTL … #define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX … #define mmCURSOR0_0_DMDATA_STATUS … #define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX … #define mmCURSOR0_0_DMDATA_SW_CNTL … #define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX … #define mmCURSOR0_0_DMDATA_SW_DATA … #define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX … // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec // base address: 0x370 #define mmHUBP1_DCSURF_SURFACE_CONFIG … #define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX … #define mmHUBP1_DCSURF_ADDR_CONFIG … #define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX … #define mmHUBP1_DCSURF_TILING_CONFIG … #define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX … #define mmHUBP1_DCSURF_PRI_VIEWPORT_START … #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION … #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C … #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP1_DCSURF_SEC_VIEWPORT_START … #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION … #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C … #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG … #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C … #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define mmHUBP1_DCHUBP_CNTL … #define mmHUBP1_DCHUBP_CNTL_BASE_IDX … #define mmHUBP1_HUBP_CLK_CNTL … #define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX … #define mmHUBP1_HUBPREQ_DEBUG_DB … #define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX … #define mmHUBP1_HUBPREQ_DEBUG … #define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX … #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec // base address: 0x370 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH … #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C … #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL … #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX … #define mmHUBPREQ1_DCSURF_FLIP_CONTROL … #define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX … #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 … #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT … #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C … #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ1_DCN_EXPANSION_MODE … #define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX … #define mmHUBPREQ1_DCN_TTU_QOS_WM … #define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX … #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL … #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 … #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 … #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 … #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 … #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 … #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 … #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 … #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 … #define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ1_BLANK_OFFSET_0 … #define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX … #define mmHUBPREQ1_BLANK_OFFSET_1 … #define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX … #define mmHUBPREQ1_DST_DIMENSIONS … #define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX … #define mmHUBPREQ1_DST_AFTER_SCALER … #define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX … #define mmHUBPREQ1_PREFETCH_SETTINGS … #define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX … #define mmHUBPREQ1_PREFETCH_SETTINGS_C … #define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX … #define mmHUBPREQ1_VBLANK_PARAMETERS_0 … #define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ1_VBLANK_PARAMETERS_1 … #define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ1_VBLANK_PARAMETERS_2 … #define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ1_VBLANK_PARAMETERS_3 … #define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ1_VBLANK_PARAMETERS_4 … #define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ1_FLIP_PARAMETERS_0 … #define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ1_FLIP_PARAMETERS_2 … #define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_4 … #define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_5 … #define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_6 … #define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX … #define mmHUBPREQ1_NOM_PARAMETERS_7 … #define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX … #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE … #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX … #define mmHUBPREQ1_PER_LINE_DELIVERY … #define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX … #define mmHUBPREQ1_CURSOR_SETTINGS … #define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX … #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ … #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT … #define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX … #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL … #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS … #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec // base address: 0x370 #define mmHUBPRET1_HUBPRET_CONTROL … #define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX … #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL … #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS … #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 … #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 … #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE0 … #define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE1 … #define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX … #define mmHUBPRET1_HUBPRET_INTERRUPT … #define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE … #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS … #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec // base address: 0x370 #define mmCURSOR0_1_CURSOR_CONTROL … #define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX … #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS … #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH … #define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR0_1_CURSOR_SIZE … #define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX … #define mmCURSOR0_1_CURSOR_POSITION … #define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX … #define mmCURSOR0_1_CURSOR_HOT_SPOT … #define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX … #define mmCURSOR0_1_CURSOR_STEREO_CONTROL … #define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX … #define mmCURSOR0_1_CURSOR_DST_OFFSET … #define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX … #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL … #define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS … #define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX … #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH … #define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR0_1_DMDATA_ADDRESS_LOW … #define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX … #define mmCURSOR0_1_DMDATA_CNTL … #define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX … #define mmCURSOR0_1_DMDATA_QOS_CNTL … #define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX … #define mmCURSOR0_1_DMDATA_STATUS … #define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX … #define mmCURSOR0_1_DMDATA_SW_CNTL … #define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX … #define mmCURSOR0_1_DMDATA_SW_DATA … #define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX … // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec // base address: 0x6e0 #define mmHUBP2_DCSURF_SURFACE_CONFIG … #define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX … #define mmHUBP2_DCSURF_ADDR_CONFIG … #define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX … #define mmHUBP2_DCSURF_TILING_CONFIG … #define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX … #define mmHUBP2_DCSURF_PRI_VIEWPORT_START … #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION … #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C … #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP2_DCSURF_SEC_VIEWPORT_START … #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION … #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C … #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG … #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C … #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define mmHUBP2_DCHUBP_CNTL … #define mmHUBP2_DCHUBP_CNTL_BASE_IDX … #define mmHUBP2_HUBP_CLK_CNTL … #define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX … #define mmHUBP2_HUBPREQ_DEBUG_DB … #define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX … #define mmHUBP2_HUBPREQ_DEBUG … #define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX … #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec // base address: 0x6e0 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH … #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C … #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL … #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX … #define mmHUBPREQ2_DCSURF_FLIP_CONTROL … #define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX … #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 … #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT … #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C … #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ2_DCN_EXPANSION_MODE … #define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX … #define mmHUBPREQ2_DCN_TTU_QOS_WM … #define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX … #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL … #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 … #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 … #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 … #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 … #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 … #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 … #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 … #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 … #define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ2_BLANK_OFFSET_0 … #define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX … #define mmHUBPREQ2_BLANK_OFFSET_1 … #define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX … #define mmHUBPREQ2_DST_DIMENSIONS … #define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX … #define mmHUBPREQ2_DST_AFTER_SCALER … #define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX … #define mmHUBPREQ2_PREFETCH_SETTINGS … #define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX … #define mmHUBPREQ2_PREFETCH_SETTINGS_C … #define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX … #define mmHUBPREQ2_VBLANK_PARAMETERS_0 … #define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ2_VBLANK_PARAMETERS_1 … #define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ2_VBLANK_PARAMETERS_2 … #define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ2_VBLANK_PARAMETERS_3 … #define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ2_VBLANK_PARAMETERS_4 … #define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ2_FLIP_PARAMETERS_0 … #define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ2_FLIP_PARAMETERS_2 … #define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_4 … #define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_5 … #define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_6 … #define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX … #define mmHUBPREQ2_NOM_PARAMETERS_7 … #define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX … #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE … #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX … #define mmHUBPREQ2_PER_LINE_DELIVERY … #define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX … #define mmHUBPREQ2_CURSOR_SETTINGS … #define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX … #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ … #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT … #define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX … #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL … #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS … #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec // base address: 0x6e0 #define mmHUBPRET2_HUBPRET_CONTROL … #define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX … #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL … #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS … #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 … #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 … #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE0 … #define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE1 … #define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX … #define mmHUBPRET2_HUBPRET_INTERRUPT … #define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE … #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS … #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec // base address: 0x6e0 #define mmCURSOR0_2_CURSOR_CONTROL … #define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX … #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS … #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH … #define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR0_2_CURSOR_SIZE … #define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX … #define mmCURSOR0_2_CURSOR_POSITION … #define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX … #define mmCURSOR0_2_CURSOR_HOT_SPOT … #define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX … #define mmCURSOR0_2_CURSOR_STEREO_CONTROL … #define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX … #define mmCURSOR0_2_CURSOR_DST_OFFSET … #define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX … #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL … #define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS … #define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX … #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH … #define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR0_2_DMDATA_ADDRESS_LOW … #define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX … #define mmCURSOR0_2_DMDATA_CNTL … #define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX … #define mmCURSOR0_2_DMDATA_QOS_CNTL … #define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX … #define mmCURSOR0_2_DMDATA_STATUS … #define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX … #define mmCURSOR0_2_DMDATA_SW_CNTL … #define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX … #define mmCURSOR0_2_DMDATA_SW_DATA … #define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX … // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec // base address: 0xa50 #define mmHUBP3_DCSURF_SURFACE_CONFIG … #define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX … #define mmHUBP3_DCSURF_ADDR_CONFIG … #define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX … #define mmHUBP3_DCSURF_TILING_CONFIG … #define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX … #define mmHUBP3_DCSURF_PRI_VIEWPORT_START … #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX … #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION … #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C … #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX … #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C … #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP3_DCSURF_SEC_VIEWPORT_START … #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX … #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION … #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX … #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C … #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX … #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C … #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX … #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG … #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX … #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C … #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX … #define mmHUBP3_DCHUBP_CNTL … #define mmHUBP3_DCHUBP_CNTL_BASE_IDX … #define mmHUBP3_HUBP_CLK_CNTL … #define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX … #define mmHUBP3_HUBPREQ_DEBUG_DB … #define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX … #define mmHUBP3_HUBPREQ_DEBUG … #define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX … #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK … #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX … #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK … #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX … // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec // base address: 0xa50 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH … #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C … #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C … #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL … #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX … #define mmHUBPREQ3_DCSURF_FLIP_CONTROL … #define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX … #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 … #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT … #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C … #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C … #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX … #define mmHUBPREQ3_DCN_EXPANSION_MODE … #define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX … #define mmHUBPREQ3_DCN_TTU_QOS_WM … #define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX … #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL … #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX … #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 … #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 … #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 … #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 … #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 … #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX … #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 … #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX … #define mmHUBPREQ3_BLANK_OFFSET_0 … #define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX … #define mmHUBPREQ3_BLANK_OFFSET_1 … #define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX … #define mmHUBPREQ3_DST_DIMENSIONS … #define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX … #define mmHUBPREQ3_DST_AFTER_SCALER … #define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX … #define mmHUBPREQ3_PREFETCH_SETTINGS … #define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX … #define mmHUBPREQ3_PREFETCH_SETTINGS_C … #define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX … #define mmHUBPREQ3_VBLANK_PARAMETERS_0 … #define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ3_VBLANK_PARAMETERS_1 … #define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX … #define mmHUBPREQ3_VBLANK_PARAMETERS_2 … #define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ3_VBLANK_PARAMETERS_3 … #define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX … #define mmHUBPREQ3_VBLANK_PARAMETERS_4 … #define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ3_FLIP_PARAMETERS_0 … #define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX … #define mmHUBPREQ3_FLIP_PARAMETERS_2 … #define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_4 … #define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_5 … #define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_6 … #define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX … #define mmHUBPREQ3_NOM_PARAMETERS_7 … #define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX … #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE … #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX … #define mmHUBPREQ3_PER_LINE_DELIVERY … #define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX … #define mmHUBPREQ3_CURSOR_SETTINGS … #define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX … #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ … #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX … #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT … #define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX … #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL … #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS … #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec // base address: 0xa50 #define mmHUBPRET3_HUBPRET_CONTROL … #define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX … #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL … #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX … #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS … #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 … #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 … #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE0 … #define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE1 … #define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX … #define mmHUBPRET3_HUBPRET_INTERRUPT … #define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE … #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX … #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS … #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX … // addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec // base address: 0xa50 #define mmCURSOR0_3_CURSOR_CONTROL … #define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX … #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS … #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX … #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH … #define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR0_3_CURSOR_SIZE … #define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX … #define mmCURSOR0_3_CURSOR_POSITION … #define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX … #define mmCURSOR0_3_CURSOR_HOT_SPOT … #define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX … #define mmCURSOR0_3_CURSOR_STEREO_CONTROL … #define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX … #define mmCURSOR0_3_CURSOR_DST_OFFSET … #define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX … #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL … #define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX … #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS … #define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX … #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH … #define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX … #define mmCURSOR0_3_DMDATA_ADDRESS_LOW … #define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX … #define mmCURSOR0_3_DMDATA_CNTL … #define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX … #define mmCURSOR0_3_DMDATA_QOS_CNTL … #define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX … #define mmCURSOR0_3_DMDATA_STATUS … #define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX … #define mmCURSOR0_3_DMDATA_SW_CNTL … #define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX … #define mmCURSOR0_3_DMDATA_SW_DATA … #define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX … // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec // base address: 0x0 #define mmDPP_TOP0_DPP_CONTROL … #define mmDPP_TOP0_DPP_CONTROL_BASE_IDX … #define mmDPP_TOP0_DPP_SOFT_RESET … #define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX … #define mmDPP_TOP0_DPP_CRC_VAL_R_G … #define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX … #define mmDPP_TOP0_DPP_CRC_VAL_B_A … #define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX … #define mmDPP_TOP0_DPP_CRC_CTRL … #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX … #define mmDPP_TOP0_HOST_READ_CONTROL … #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX … // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec // base address: 0x0 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT … #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define mmCNVC_CFG0_FORMAT_CONTROL … #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX … #define mmCNVC_CFG0_FCNV_FP_BIAS_R … #define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX … #define mmCNVC_CFG0_FCNV_FP_BIAS_G … #define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX … #define mmCNVC_CFG0_FCNV_FP_BIAS_B … #define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX … #define mmCNVC_CFG0_FCNV_FP_SCALE_R … #define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX … #define mmCNVC_CFG0_FCNV_FP_SCALE_G … #define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX … #define mmCNVC_CFG0_FCNV_FP_SCALE_B … #define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX … #define mmCNVC_CFG0_COLOR_KEYER_CONTROL … #define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX … #define mmCNVC_CFG0_COLOR_KEYER_ALPHA … #define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX … #define mmCNVC_CFG0_COLOR_KEYER_RED … #define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX … #define mmCNVC_CFG0_COLOR_KEYER_GREEN … #define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX … #define mmCNVC_CFG0_COLOR_KEYER_BLUE … #define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX … #define mmCNVC_CFG0_ALPHA_2BIT_LUT … #define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX … // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec // base address: 0x0 #define mmCNVC_CUR0_CURSOR0_CONTROL … #define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX … #define mmCNVC_CUR0_CURSOR0_COLOR0 … #define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX … #define mmCNVC_CUR0_CURSOR0_COLOR1 … #define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX … #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS … #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX … // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec // base address: 0x0 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT … #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define mmDSCL0_SCL_COEF_RAM_TAP_DATA … #define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmDSCL0_SCL_MODE … #define mmDSCL0_SCL_MODE_BASE_IDX … #define mmDSCL0_SCL_TAP_CONTROL … #define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX … #define mmDSCL0_DSCL_CONTROL … #define mmDSCL0_DSCL_CONTROL_BASE_IDX … #define mmDSCL0_DSCL_2TAP_CONTROL … #define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX … #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL … #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO … #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL0_SCL_HORZ_FILTER_INIT … #define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C … #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL0_SCL_HORZ_FILTER_INIT_C … #define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO … #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_INIT … #define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT … #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C … #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_INIT_C … #define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C … #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define mmDSCL0_SCL_BLACK_OFFSET … #define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX … #define mmDSCL0_DSCL_UPDATE … #define mmDSCL0_DSCL_UPDATE_BASE_IDX … #define mmDSCL0_DSCL_AUTOCAL … #define mmDSCL0_DSCL_AUTOCAL_BASE_IDX … #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmDSCL0_OTG_H_BLANK … #define mmDSCL0_OTG_H_BLANK_BASE_IDX … #define mmDSCL0_OTG_V_BLANK … #define mmDSCL0_OTG_V_BLANK_BASE_IDX … #define mmDSCL0_RECOUT_START … #define mmDSCL0_RECOUT_START_BASE_IDX … #define mmDSCL0_RECOUT_SIZE … #define mmDSCL0_RECOUT_SIZE_BASE_IDX … #define mmDSCL0_MPC_SIZE … #define mmDSCL0_MPC_SIZE_BASE_IDX … #define mmDSCL0_LB_DATA_FORMAT … #define mmDSCL0_LB_DATA_FORMAT_BASE_IDX … #define mmDSCL0_LB_MEMORY_CTRL … #define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX … #define mmDSCL0_LB_V_COUNTER … #define mmDSCL0_LB_V_COUNTER_BASE_IDX … #define mmDSCL0_DSCL_MEM_PWR_CTRL … #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX … #define mmDSCL0_DSCL_MEM_PWR_STATUS … #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX … #define mmDSCL0_OBUF_CONTROL … #define mmDSCL0_OBUF_CONTROL_BASE_IDX … #define mmDSCL0_OBUF_MEM_PWR_CTRL … #define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec // base address: 0x0 #define mmCM0_CM_CONTROL … #define mmCM0_CM_CONTROL_BASE_IDX … #define mmCM0_CM_ICSC_CONTROL … #define mmCM0_CM_ICSC_CONTROL_BASE_IDX … #define mmCM0_CM_ICSC_C11_C12 … #define mmCM0_CM_ICSC_C11_C12_BASE_IDX … #define mmCM0_CM_ICSC_C13_C14 … #define mmCM0_CM_ICSC_C13_C14_BASE_IDX … #define mmCM0_CM_ICSC_C21_C22 … #define mmCM0_CM_ICSC_C21_C22_BASE_IDX … #define mmCM0_CM_ICSC_C23_C24 … #define mmCM0_CM_ICSC_C23_C24_BASE_IDX … #define mmCM0_CM_ICSC_C31_C32 … #define mmCM0_CM_ICSC_C31_C32_BASE_IDX … #define mmCM0_CM_ICSC_C33_C34 … #define mmCM0_CM_ICSC_C33_C34_BASE_IDX … #define mmCM0_CM_ICSC_B_C11_C12 … #define mmCM0_CM_ICSC_B_C11_C12_BASE_IDX … #define mmCM0_CM_ICSC_B_C13_C14 … #define mmCM0_CM_ICSC_B_C13_C14_BASE_IDX … #define mmCM0_CM_ICSC_B_C21_C22 … #define mmCM0_CM_ICSC_B_C21_C22_BASE_IDX … #define mmCM0_CM_ICSC_B_C23_C24 … #define mmCM0_CM_ICSC_B_C23_C24_BASE_IDX … #define mmCM0_CM_ICSC_B_C31_C32 … #define mmCM0_CM_ICSC_B_C31_C32_BASE_IDX … #define mmCM0_CM_ICSC_B_C33_C34 … #define mmCM0_CM_ICSC_B_C33_C34_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_CONTROL … #define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C11_C12 … #define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C13_C14 … #define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C21_C22 … #define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C23_C24 … #define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C31_C32 … #define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_C33_C34 … #define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_B_C11_C12 … #define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_B_C13_C14 … #define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_B_C21_C22 … #define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_B_C23_C24 … #define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_B_C31_C32 … #define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX … #define mmCM0_CM_GAMUT_REMAP_B_C33_C34 … #define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX … #define mmCM0_CM_BIAS_CR_R … #define mmCM0_CM_BIAS_CR_R_BASE_IDX … #define mmCM0_CM_BIAS_Y_G_CB_B … #define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX … #define mmCM0_CM_DGAM_CONTROL … #define mmCM0_CM_DGAM_CONTROL_BASE_IDX … #define mmCM0_CM_DGAM_LUT_INDEX … #define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX … #define mmCM0_CM_DGAM_LUT_DATA … #define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX … #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK … #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_START_CNTL_B … #define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_START_CNTL_G … #define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_START_CNTL_R … #define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R … #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R … #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R … #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_0_1 … #define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_2_3 … #define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_4_5 … #define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_6_7 … #define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_8_9 … #define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_10_11 … #define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_12_13 … #define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM0_CM_DGAM_RAMA_REGION_14_15 … #define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_START_CNTL_B … #define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_START_CNTL_G … #define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_START_CNTL_R … #define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R … #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R … #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R … #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_0_1 … #define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_2_3 … #define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_4_5 … #define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_6_7 … #define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_8_9 … #define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_10_11 … #define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_12_13 … #define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM0_CM_DGAM_RAMB_REGION_14_15 … #define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM0_CM_BLNDGAM_CONTROL … #define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX … #define mmCM0_CM_BLNDGAM_LUT_INDEX … #define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX … #define mmCM0_CM_BLNDGAM_LUT_DATA … #define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX … #define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK … #define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B … #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G … #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R … #define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B … #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G … #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R … #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R … #define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 … #define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B … #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G … #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R … #define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B … #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G … #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R … #define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R … #define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX … #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 … #define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX … #define mmCM0_CM_HDR_MULT_COEF … #define mmCM0_CM_HDR_MULT_COEF_BASE_IDX … #define mmCM0_CM_MEM_PWR_CTRL … #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX … #define mmCM0_CM_MEM_PWR_STATUS … #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX … #define mmCM0_CM_DEALPHA … #define mmCM0_CM_DEALPHA_BASE_IDX … #define mmCM0_CM_COEF_FORMAT … #define mmCM0_CM_COEF_FORMAT_BASE_IDX … #define mmCM0_CM_SHAPER_CONTROL … #define mmCM0_CM_SHAPER_CONTROL_BASE_IDX … #define mmCM0_CM_SHAPER_OFFSET_R … #define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX … #define mmCM0_CM_SHAPER_OFFSET_G … #define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX … #define mmCM0_CM_SHAPER_OFFSET_B … #define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX … #define mmCM0_CM_SHAPER_SCALE_R … #define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX … #define mmCM0_CM_SHAPER_SCALE_G_B … #define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX … #define mmCM0_CM_SHAPER_LUT_INDEX … #define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX … #define mmCM0_CM_SHAPER_LUT_DATA … #define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX … #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK … #define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B … #define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G … #define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R … #define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B … #define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G … #define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R … #define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_0_1 … #define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_2_3 … #define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_4_5 … #define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_6_7 … #define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_8_9 … #define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_10_11 … #define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_12_13 … #define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_14_15 … #define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_16_17 … #define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_18_19 … #define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_20_21 … #define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_22_23 … #define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_24_25 … #define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_26_27 … #define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_28_29 … #define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_30_31 … #define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX … #define mmCM0_CM_SHAPER_RAMA_REGION_32_33 … #define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B … #define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G … #define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R … #define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B … #define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G … #define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R … #define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_0_1 … #define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_2_3 … #define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_4_5 … #define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_6_7 … #define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_8_9 … #define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_10_11 … #define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_12_13 … #define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_14_15 … #define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_16_17 … #define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_18_19 … #define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_20_21 … #define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_22_23 … #define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_24_25 … #define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_26_27 … #define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_28_29 … #define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_30_31 … #define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX … #define mmCM0_CM_SHAPER_RAMB_REGION_32_33 … #define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX … #define mmCM0_CM_MEM_PWR_CTRL2 … #define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX … #define mmCM0_CM_MEM_PWR_STATUS2 … #define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX … #define mmCM0_CM_3DLUT_MODE … #define mmCM0_CM_3DLUT_MODE_BASE_IDX … #define mmCM0_CM_3DLUT_INDEX … #define mmCM0_CM_3DLUT_INDEX_BASE_IDX … #define mmCM0_CM_3DLUT_DATA … #define mmCM0_CM_3DLUT_DATA_BASE_IDX … #define mmCM0_CM_3DLUT_DATA_30BIT … #define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX … #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL … #define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX … #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR … #define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX … #define mmCM0_CM_3DLUT_OUT_OFFSET_R … #define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX … #define mmCM0_CM_3DLUT_OUT_OFFSET_G … #define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX … #define mmCM0_CM_3DLUT_OUT_OFFSET_B … #define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX … #define mmCM0_CM_TEST_DEBUG_INDEX … #define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX … #define mmCM0_CM_TEST_DEBUG_DATA … #define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec // base address: 0x5ac #define mmDPP_TOP1_DPP_CONTROL … #define mmDPP_TOP1_DPP_CONTROL_BASE_IDX … #define mmDPP_TOP1_DPP_SOFT_RESET … #define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX … #define mmDPP_TOP1_DPP_CRC_VAL_R_G … #define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX … #define mmDPP_TOP1_DPP_CRC_VAL_B_A … #define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX … #define mmDPP_TOP1_DPP_CRC_CTRL … #define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX … #define mmDPP_TOP1_HOST_READ_CONTROL … #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX … // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec // base address: 0x5ac #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT … #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define mmCNVC_CFG1_FORMAT_CONTROL … #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX … #define mmCNVC_CFG1_FCNV_FP_BIAS_R … #define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX … #define mmCNVC_CFG1_FCNV_FP_BIAS_G … #define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX … #define mmCNVC_CFG1_FCNV_FP_BIAS_B … #define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX … #define mmCNVC_CFG1_FCNV_FP_SCALE_R … #define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX … #define mmCNVC_CFG1_FCNV_FP_SCALE_G … #define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX … #define mmCNVC_CFG1_FCNV_FP_SCALE_B … #define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX … #define mmCNVC_CFG1_COLOR_KEYER_CONTROL … #define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX … #define mmCNVC_CFG1_COLOR_KEYER_ALPHA … #define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX … #define mmCNVC_CFG1_COLOR_KEYER_RED … #define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX … #define mmCNVC_CFG1_COLOR_KEYER_GREEN … #define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX … #define mmCNVC_CFG1_COLOR_KEYER_BLUE … #define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX … #define mmCNVC_CFG1_ALPHA_2BIT_LUT … #define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX … // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec // base address: 0x5ac #define mmCNVC_CUR1_CURSOR0_CONTROL … #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX … #define mmCNVC_CUR1_CURSOR0_COLOR0 … #define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX … #define mmCNVC_CUR1_CURSOR0_COLOR1 … #define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX … #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS … #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX … // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec // base address: 0x5ac #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT … #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define mmDSCL1_SCL_COEF_RAM_TAP_DATA … #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmDSCL1_SCL_MODE … #define mmDSCL1_SCL_MODE_BASE_IDX … #define mmDSCL1_SCL_TAP_CONTROL … #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX … #define mmDSCL1_DSCL_CONTROL … #define mmDSCL1_DSCL_CONTROL_BASE_IDX … #define mmDSCL1_DSCL_2TAP_CONTROL … #define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX … #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL … #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO … #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL1_SCL_HORZ_FILTER_INIT … #define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C … #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL1_SCL_HORZ_FILTER_INIT_C … #define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO … #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_INIT … #define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT … #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C … #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_INIT_C … #define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C … #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define mmDSCL1_SCL_BLACK_OFFSET … #define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX … #define mmDSCL1_DSCL_UPDATE … #define mmDSCL1_DSCL_UPDATE_BASE_IDX … #define mmDSCL1_DSCL_AUTOCAL … #define mmDSCL1_DSCL_AUTOCAL_BASE_IDX … #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmDSCL1_OTG_H_BLANK … #define mmDSCL1_OTG_H_BLANK_BASE_IDX … #define mmDSCL1_OTG_V_BLANK … #define mmDSCL1_OTG_V_BLANK_BASE_IDX … #define mmDSCL1_RECOUT_START … #define mmDSCL1_RECOUT_START_BASE_IDX … #define mmDSCL1_RECOUT_SIZE … #define mmDSCL1_RECOUT_SIZE_BASE_IDX … #define mmDSCL1_MPC_SIZE … #define mmDSCL1_MPC_SIZE_BASE_IDX … #define mmDSCL1_LB_DATA_FORMAT … #define mmDSCL1_LB_DATA_FORMAT_BASE_IDX … #define mmDSCL1_LB_MEMORY_CTRL … #define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX … #define mmDSCL1_LB_V_COUNTER … #define mmDSCL1_LB_V_COUNTER_BASE_IDX … #define mmDSCL1_DSCL_MEM_PWR_CTRL … #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX … #define mmDSCL1_DSCL_MEM_PWR_STATUS … #define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX … #define mmDSCL1_OBUF_CONTROL … #define mmDSCL1_OBUF_CONTROL_BASE_IDX … #define mmDSCL1_OBUF_MEM_PWR_CTRL … #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec // base address: 0x5ac #define mmCM1_CM_CONTROL … #define mmCM1_CM_CONTROL_BASE_IDX … #define mmCM1_CM_ICSC_CONTROL … #define mmCM1_CM_ICSC_CONTROL_BASE_IDX … #define mmCM1_CM_ICSC_C11_C12 … #define mmCM1_CM_ICSC_C11_C12_BASE_IDX … #define mmCM1_CM_ICSC_C13_C14 … #define mmCM1_CM_ICSC_C13_C14_BASE_IDX … #define mmCM1_CM_ICSC_C21_C22 … #define mmCM1_CM_ICSC_C21_C22_BASE_IDX … #define mmCM1_CM_ICSC_C23_C24 … #define mmCM1_CM_ICSC_C23_C24_BASE_IDX … #define mmCM1_CM_ICSC_C31_C32 … #define mmCM1_CM_ICSC_C31_C32_BASE_IDX … #define mmCM1_CM_ICSC_C33_C34 … #define mmCM1_CM_ICSC_C33_C34_BASE_IDX … #define mmCM1_CM_ICSC_B_C11_C12 … #define mmCM1_CM_ICSC_B_C11_C12_BASE_IDX … #define mmCM1_CM_ICSC_B_C13_C14 … #define mmCM1_CM_ICSC_B_C13_C14_BASE_IDX … #define mmCM1_CM_ICSC_B_C21_C22 … #define mmCM1_CM_ICSC_B_C21_C22_BASE_IDX … #define mmCM1_CM_ICSC_B_C23_C24 … #define mmCM1_CM_ICSC_B_C23_C24_BASE_IDX … #define mmCM1_CM_ICSC_B_C31_C32 … #define mmCM1_CM_ICSC_B_C31_C32_BASE_IDX … #define mmCM1_CM_ICSC_B_C33_C34 … #define mmCM1_CM_ICSC_B_C33_C34_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_CONTROL … #define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C11_C12 … #define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C13_C14 … #define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C21_C22 … #define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C23_C24 … #define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C31_C32 … #define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_C33_C34 … #define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_B_C11_C12 … #define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_B_C13_C14 … #define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_B_C21_C22 … #define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_B_C23_C24 … #define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_B_C31_C32 … #define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX … #define mmCM1_CM_GAMUT_REMAP_B_C33_C34 … #define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX … #define mmCM1_CM_BIAS_CR_R … #define mmCM1_CM_BIAS_CR_R_BASE_IDX … #define mmCM1_CM_BIAS_Y_G_CB_B … #define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX … #define mmCM1_CM_DGAM_CONTROL … #define mmCM1_CM_DGAM_CONTROL_BASE_IDX … #define mmCM1_CM_DGAM_LUT_INDEX … #define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX … #define mmCM1_CM_DGAM_LUT_DATA … #define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX … #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK … #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_START_CNTL_B … #define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_START_CNTL_G … #define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_START_CNTL_R … #define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R … #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R … #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R … #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_0_1 … #define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_2_3 … #define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_4_5 … #define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_6_7 … #define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_8_9 … #define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_10_11 … #define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_12_13 … #define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM1_CM_DGAM_RAMA_REGION_14_15 … #define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_START_CNTL_B … #define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_START_CNTL_G … #define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_START_CNTL_R … #define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R … #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R … #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R … #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_0_1 … #define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_2_3 … #define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_4_5 … #define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_6_7 … #define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_8_9 … #define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_10_11 … #define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_12_13 … #define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM1_CM_DGAM_RAMB_REGION_14_15 … #define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM1_CM_BLNDGAM_CONTROL … #define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX … #define mmCM1_CM_BLNDGAM_LUT_INDEX … #define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX … #define mmCM1_CM_BLNDGAM_LUT_DATA … #define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX … #define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK … #define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B … #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G … #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R … #define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B … #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G … #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R … #define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R … #define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 … #define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B … #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G … #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R … #define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B … #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G … #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R … #define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R … #define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX … #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 … #define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX … #define mmCM1_CM_HDR_MULT_COEF … #define mmCM1_CM_HDR_MULT_COEF_BASE_IDX … #define mmCM1_CM_MEM_PWR_CTRL … #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX … #define mmCM1_CM_MEM_PWR_STATUS … #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX … #define mmCM1_CM_DEALPHA … #define mmCM1_CM_DEALPHA_BASE_IDX … #define mmCM1_CM_COEF_FORMAT … #define mmCM1_CM_COEF_FORMAT_BASE_IDX … #define mmCM1_CM_SHAPER_CONTROL … #define mmCM1_CM_SHAPER_CONTROL_BASE_IDX … #define mmCM1_CM_SHAPER_OFFSET_R … #define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX … #define mmCM1_CM_SHAPER_OFFSET_G … #define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX … #define mmCM1_CM_SHAPER_OFFSET_B … #define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX … #define mmCM1_CM_SHAPER_SCALE_R … #define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX … #define mmCM1_CM_SHAPER_SCALE_G_B … #define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX … #define mmCM1_CM_SHAPER_LUT_INDEX … #define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX … #define mmCM1_CM_SHAPER_LUT_DATA … #define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX … #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK … #define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B … #define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G … #define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R … #define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B … #define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G … #define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R … #define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_0_1 … #define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_2_3 … #define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_4_5 … #define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_6_7 … #define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_8_9 … #define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_10_11 … #define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_12_13 … #define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_14_15 … #define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_16_17 … #define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_18_19 … #define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_20_21 … #define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_22_23 … #define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_24_25 … #define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_26_27 … #define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_28_29 … #define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_30_31 … #define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX … #define mmCM1_CM_SHAPER_RAMA_REGION_32_33 … #define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B … #define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G … #define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R … #define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B … #define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G … #define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R … #define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_0_1 … #define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_2_3 … #define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_4_5 … #define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_6_7 … #define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_8_9 … #define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_10_11 … #define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_12_13 … #define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_14_15 … #define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_16_17 … #define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_18_19 … #define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_20_21 … #define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_22_23 … #define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_24_25 … #define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_26_27 … #define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_28_29 … #define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_30_31 … #define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX … #define mmCM1_CM_SHAPER_RAMB_REGION_32_33 … #define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX … #define mmCM1_CM_MEM_PWR_CTRL2 … #define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX … #define mmCM1_CM_MEM_PWR_STATUS2 … #define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX … #define mmCM1_CM_3DLUT_MODE … #define mmCM1_CM_3DLUT_MODE_BASE_IDX … #define mmCM1_CM_3DLUT_INDEX … #define mmCM1_CM_3DLUT_INDEX_BASE_IDX … #define mmCM1_CM_3DLUT_DATA … #define mmCM1_CM_3DLUT_DATA_BASE_IDX … #define mmCM1_CM_3DLUT_DATA_30BIT … #define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX … #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL … #define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX … #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR … #define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX … #define mmCM1_CM_3DLUT_OUT_OFFSET_R … #define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX … #define mmCM1_CM_3DLUT_OUT_OFFSET_G … #define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX … #define mmCM1_CM_3DLUT_OUT_OFFSET_B … #define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX … #define mmCM1_CM_TEST_DEBUG_INDEX … #define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX … #define mmCM1_CM_TEST_DEBUG_DATA … #define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec // base address: 0xb58 #define mmDPP_TOP2_DPP_CONTROL … #define mmDPP_TOP2_DPP_CONTROL_BASE_IDX … #define mmDPP_TOP2_DPP_SOFT_RESET … #define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX … #define mmDPP_TOP2_DPP_CRC_VAL_R_G … #define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX … #define mmDPP_TOP2_DPP_CRC_VAL_B_A … #define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX … #define mmDPP_TOP2_DPP_CRC_CTRL … #define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX … // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec // base address: 0xb58 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT … #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define mmCNVC_CFG2_FORMAT_CONTROL … #define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX … #define mmCNVC_CFG2_FCNV_FP_BIAS_R … #define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX … #define mmCNVC_CFG2_FCNV_FP_BIAS_G … #define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX … #define mmCNVC_CFG2_FCNV_FP_BIAS_B … #define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX … #define mmCNVC_CFG2_FCNV_FP_SCALE_R … #define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX … #define mmCNVC_CFG2_FCNV_FP_SCALE_G … #define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX … #define mmCNVC_CFG2_FCNV_FP_SCALE_B … #define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX … #define mmCNVC_CFG2_COLOR_KEYER_CONTROL … #define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX … #define mmCNVC_CFG2_COLOR_KEYER_ALPHA … #define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX … #define mmCNVC_CFG2_COLOR_KEYER_RED … #define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX … #define mmCNVC_CFG2_COLOR_KEYER_GREEN … #define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX … #define mmCNVC_CFG2_COLOR_KEYER_BLUE … #define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX … #define mmCNVC_CFG2_ALPHA_2BIT_LUT … #define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX … // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec // base address: 0xb58 #define mmCNVC_CUR2_CURSOR0_CONTROL … #define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX … #define mmCNVC_CUR2_CURSOR0_COLOR0 … #define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX … #define mmCNVC_CUR2_CURSOR0_COLOR1 … #define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX … #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS … #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX … // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec // base address: 0xb58 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT … #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define mmDSCL2_SCL_COEF_RAM_TAP_DATA … #define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmDSCL2_SCL_MODE … #define mmDSCL2_SCL_MODE_BASE_IDX … #define mmDSCL2_SCL_TAP_CONTROL … #define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX … #define mmDSCL2_DSCL_CONTROL … #define mmDSCL2_DSCL_CONTROL_BASE_IDX … #define mmDSCL2_DSCL_2TAP_CONTROL … #define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX … #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL … #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO … #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL2_SCL_HORZ_FILTER_INIT … #define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C … #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL2_SCL_HORZ_FILTER_INIT_C … #define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO … #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_INIT … #define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT … #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C … #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_INIT_C … #define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C … #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define mmDSCL2_SCL_BLACK_OFFSET … #define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX … #define mmDSCL2_DSCL_UPDATE … #define mmDSCL2_DSCL_UPDATE_BASE_IDX … #define mmDSCL2_DSCL_AUTOCAL … #define mmDSCL2_DSCL_AUTOCAL_BASE_IDX … #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmDSCL2_OTG_H_BLANK … #define mmDSCL2_OTG_H_BLANK_BASE_IDX … #define mmDSCL2_OTG_V_BLANK … #define mmDSCL2_OTG_V_BLANK_BASE_IDX … #define mmDSCL2_RECOUT_START … #define mmDSCL2_RECOUT_START_BASE_IDX … #define mmDSCL2_RECOUT_SIZE … #define mmDSCL2_RECOUT_SIZE_BASE_IDX … #define mmDSCL2_MPC_SIZE … #define mmDSCL2_MPC_SIZE_BASE_IDX … #define mmDSCL2_LB_DATA_FORMAT … #define mmDSCL2_LB_DATA_FORMAT_BASE_IDX … #define mmDSCL2_LB_MEMORY_CTRL … #define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX … #define mmDSCL2_LB_V_COUNTER … #define mmDSCL2_LB_V_COUNTER_BASE_IDX … #define mmDSCL2_DSCL_MEM_PWR_CTRL … #define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX … #define mmDSCL2_DSCL_MEM_PWR_STATUS … #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX … #define mmDSCL2_OBUF_CONTROL … #define mmDSCL2_OBUF_CONTROL_BASE_IDX … #define mmDSCL2_OBUF_MEM_PWR_CTRL … #define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec // base address: 0xb58 #define mmCM2_CM_CONTROL … #define mmCM2_CM_CONTROL_BASE_IDX … #define mmCM2_CM_ICSC_CONTROL … #define mmCM2_CM_ICSC_CONTROL_BASE_IDX … #define mmCM2_CM_ICSC_C11_C12 … #define mmCM2_CM_ICSC_C11_C12_BASE_IDX … #define mmCM2_CM_ICSC_C13_C14 … #define mmCM2_CM_ICSC_C13_C14_BASE_IDX … #define mmCM2_CM_ICSC_C21_C22 … #define mmCM2_CM_ICSC_C21_C22_BASE_IDX … #define mmCM2_CM_ICSC_C23_C24 … #define mmCM2_CM_ICSC_C23_C24_BASE_IDX … #define mmCM2_CM_ICSC_C31_C32 … #define mmCM2_CM_ICSC_C31_C32_BASE_IDX … #define mmCM2_CM_ICSC_C33_C34 … #define mmCM2_CM_ICSC_C33_C34_BASE_IDX … #define mmCM2_CM_ICSC_B_C11_C12 … #define mmCM2_CM_ICSC_B_C11_C12_BASE_IDX … #define mmCM2_CM_ICSC_B_C13_C14 … #define mmCM2_CM_ICSC_B_C13_C14_BASE_IDX … #define mmCM2_CM_ICSC_B_C21_C22 … #define mmCM2_CM_ICSC_B_C21_C22_BASE_IDX … #define mmCM2_CM_ICSC_B_C23_C24 … #define mmCM2_CM_ICSC_B_C23_C24_BASE_IDX … #define mmCM2_CM_ICSC_B_C31_C32 … #define mmCM2_CM_ICSC_B_C31_C32_BASE_IDX … #define mmCM2_CM_ICSC_B_C33_C34 … #define mmCM2_CM_ICSC_B_C33_C34_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_CONTROL … #define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C11_C12 … #define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C13_C14 … #define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C21_C22 … #define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C23_C24 … #define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C31_C32 … #define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_C33_C34 … #define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_B_C11_C12 … #define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_B_C13_C14 … #define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_B_C21_C22 … #define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_B_C23_C24 … #define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_B_C31_C32 … #define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX … #define mmCM2_CM_GAMUT_REMAP_B_C33_C34 … #define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX … #define mmCM2_CM_BIAS_CR_R … #define mmCM2_CM_BIAS_CR_R_BASE_IDX … #define mmCM2_CM_BIAS_Y_G_CB_B … #define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX … #define mmCM2_CM_DGAM_CONTROL … #define mmCM2_CM_DGAM_CONTROL_BASE_IDX … #define mmCM2_CM_DGAM_LUT_INDEX … #define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX … #define mmCM2_CM_DGAM_LUT_DATA … #define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX … #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK … #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_START_CNTL_B … #define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_START_CNTL_G … #define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_START_CNTL_R … #define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R … #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R … #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R … #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_0_1 … #define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_2_3 … #define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_4_5 … #define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_6_7 … #define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_8_9 … #define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_10_11 … #define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_12_13 … #define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM2_CM_DGAM_RAMA_REGION_14_15 … #define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_START_CNTL_B … #define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_START_CNTL_G … #define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_START_CNTL_R … #define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R … #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R … #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R … #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_0_1 … #define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_2_3 … #define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_4_5 … #define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_6_7 … #define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_8_9 … #define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_10_11 … #define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_12_13 … #define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM2_CM_DGAM_RAMB_REGION_14_15 … #define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM2_CM_BLNDGAM_CONTROL … #define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX … #define mmCM2_CM_BLNDGAM_LUT_INDEX … #define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX … #define mmCM2_CM_BLNDGAM_LUT_DATA … #define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX … #define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK … #define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B … #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G … #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R … #define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B … #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G … #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R … #define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R … #define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 … #define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B … #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G … #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R … #define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B … #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G … #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R … #define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R … #define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX … #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 … #define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX … #define mmCM2_CM_HDR_MULT_COEF … #define mmCM2_CM_HDR_MULT_COEF_BASE_IDX … #define mmCM2_CM_MEM_PWR_CTRL … #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX … #define mmCM2_CM_MEM_PWR_STATUS … #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX … #define mmCM2_CM_DEALPHA … #define mmCM2_CM_DEALPHA_BASE_IDX … #define mmCM2_CM_COEF_FORMAT … #define mmCM2_CM_COEF_FORMAT_BASE_IDX … #define mmCM2_CM_SHAPER_CONTROL … #define mmCM2_CM_SHAPER_CONTROL_BASE_IDX … #define mmCM2_CM_SHAPER_OFFSET_R … #define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX … #define mmCM2_CM_SHAPER_OFFSET_G … #define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX … #define mmCM2_CM_SHAPER_OFFSET_B … #define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX … #define mmCM2_CM_SHAPER_SCALE_R … #define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX … #define mmCM2_CM_SHAPER_SCALE_G_B … #define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX … #define mmCM2_CM_SHAPER_LUT_INDEX … #define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX … #define mmCM2_CM_SHAPER_LUT_DATA … #define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX … #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK … #define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B … #define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G … #define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R … #define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B … #define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G … #define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R … #define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_0_1 … #define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_2_3 … #define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_4_5 … #define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_6_7 … #define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_8_9 … #define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_10_11 … #define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_12_13 … #define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_14_15 … #define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_16_17 … #define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_18_19 … #define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_20_21 … #define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_22_23 … #define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_24_25 … #define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_26_27 … #define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_28_29 … #define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_30_31 … #define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX … #define mmCM2_CM_SHAPER_RAMA_REGION_32_33 … #define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B … #define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G … #define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R … #define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B … #define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G … #define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R … #define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_0_1 … #define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_2_3 … #define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_4_5 … #define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_6_7 … #define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_8_9 … #define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_10_11 … #define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_12_13 … #define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_14_15 … #define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_16_17 … #define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_18_19 … #define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_20_21 … #define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_22_23 … #define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_24_25 … #define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_26_27 … #define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_28_29 … #define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_30_31 … #define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX … #define mmCM2_CM_SHAPER_RAMB_REGION_32_33 … #define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX … #define mmCM2_CM_MEM_PWR_CTRL2 … #define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX … #define mmCM2_CM_MEM_PWR_STATUS2 … #define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX … #define mmCM2_CM_3DLUT_MODE … #define mmCM2_CM_3DLUT_MODE_BASE_IDX … #define mmCM2_CM_3DLUT_INDEX … #define mmCM2_CM_3DLUT_INDEX_BASE_IDX … #define mmCM2_CM_3DLUT_DATA … #define mmCM2_CM_3DLUT_DATA_BASE_IDX … #define mmCM2_CM_3DLUT_DATA_30BIT … #define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX … #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL … #define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX … #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR … #define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX … #define mmCM2_CM_3DLUT_OUT_OFFSET_R … #define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX … #define mmCM2_CM_3DLUT_OUT_OFFSET_G … #define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX … #define mmCM2_CM_3DLUT_OUT_OFFSET_B … #define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX … #define mmCM2_CM_TEST_DEBUG_INDEX … #define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX … #define mmCM2_CM_TEST_DEBUG_DATA … #define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec // base address: 0x1104 #define mmDPP_TOP3_DPP_CONTROL … #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX … #define mmDPP_TOP3_DPP_SOFT_RESET … #define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX … #define mmDPP_TOP3_DPP_CRC_VAL_R_G … #define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX … #define mmDPP_TOP3_DPP_CRC_VAL_B_A … #define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX … #define mmDPP_TOP3_DPP_CRC_CTRL … #define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX … // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec // base address: 0x1104 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT … #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX … #define mmCNVC_CFG3_FORMAT_CONTROL … #define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX … #define mmCNVC_CFG3_FCNV_FP_BIAS_R … #define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX … #define mmCNVC_CFG3_FCNV_FP_BIAS_G … #define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX … #define mmCNVC_CFG3_FCNV_FP_BIAS_B … #define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX … #define mmCNVC_CFG3_FCNV_FP_SCALE_R … #define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX … #define mmCNVC_CFG3_FCNV_FP_SCALE_G … #define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX … #define mmCNVC_CFG3_FCNV_FP_SCALE_B … #define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX … #define mmCNVC_CFG3_COLOR_KEYER_CONTROL … #define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX … #define mmCNVC_CFG3_COLOR_KEYER_ALPHA … #define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX … #define mmCNVC_CFG3_COLOR_KEYER_RED … #define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX … #define mmCNVC_CFG3_COLOR_KEYER_GREEN … #define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX … #define mmCNVC_CFG3_COLOR_KEYER_BLUE … #define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX … #define mmCNVC_CFG3_ALPHA_2BIT_LUT … #define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX … // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec // base address: 0x1104 #define mmCNVC_CUR3_CURSOR0_CONTROL … #define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX … #define mmCNVC_CUR3_CURSOR0_COLOR0 … #define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX … #define mmCNVC_CUR3_CURSOR0_COLOR1 … #define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX … #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS … #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX … // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec // base address: 0x1104 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT … #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX … #define mmDSCL3_SCL_COEF_RAM_TAP_DATA … #define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX … #define mmDSCL3_SCL_MODE … #define mmDSCL3_SCL_MODE_BASE_IDX … #define mmDSCL3_SCL_TAP_CONTROL … #define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX … #define mmDSCL3_DSCL_CONTROL … #define mmDSCL3_DSCL_CONTROL_BASE_IDX … #define mmDSCL3_DSCL_2TAP_CONTROL … #define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX … #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL … #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX … #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO … #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL3_SCL_HORZ_FILTER_INIT … #define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX … #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C … #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL3_SCL_HORZ_FILTER_INIT_C … #define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO … #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_INIT … #define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT … #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C … #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_INIT_C … #define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX … #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C … #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX … #define mmDSCL3_SCL_BLACK_OFFSET … #define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX … #define mmDSCL3_DSCL_UPDATE … #define mmDSCL3_DSCL_UPDATE_BASE_IDX … #define mmDSCL3_DSCL_AUTOCAL … #define mmDSCL3_DSCL_AUTOCAL_BASE_IDX … #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT … #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX … #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM … #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX … #define mmDSCL3_OTG_H_BLANK … #define mmDSCL3_OTG_H_BLANK_BASE_IDX … #define mmDSCL3_OTG_V_BLANK … #define mmDSCL3_OTG_V_BLANK_BASE_IDX … #define mmDSCL3_RECOUT_START … #define mmDSCL3_RECOUT_START_BASE_IDX … #define mmDSCL3_RECOUT_SIZE … #define mmDSCL3_RECOUT_SIZE_BASE_IDX … #define mmDSCL3_MPC_SIZE … #define mmDSCL3_MPC_SIZE_BASE_IDX … #define mmDSCL3_LB_DATA_FORMAT … #define mmDSCL3_LB_DATA_FORMAT_BASE_IDX … #define mmDSCL3_LB_MEMORY_CTRL … #define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX … #define mmDSCL3_LB_V_COUNTER … #define mmDSCL3_LB_V_COUNTER_BASE_IDX … #define mmDSCL3_DSCL_MEM_PWR_CTRL … #define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX … #define mmDSCL3_DSCL_MEM_PWR_STATUS … #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX … #define mmDSCL3_OBUF_CONTROL … #define mmDSCL3_OBUF_CONTROL_BASE_IDX … #define mmDSCL3_OBUF_MEM_PWR_CTRL … #define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX … // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec // base address: 0x1104 #define mmCM3_CM_CONTROL … #define mmCM3_CM_CONTROL_BASE_IDX … #define mmCM3_CM_ICSC_CONTROL … #define mmCM3_CM_ICSC_CONTROL_BASE_IDX … #define mmCM3_CM_ICSC_C11_C12 … #define mmCM3_CM_ICSC_C11_C12_BASE_IDX … #define mmCM3_CM_ICSC_C13_C14 … #define mmCM3_CM_ICSC_C13_C14_BASE_IDX … #define mmCM3_CM_ICSC_C21_C22 … #define mmCM3_CM_ICSC_C21_C22_BASE_IDX … #define mmCM3_CM_ICSC_C23_C24 … #define mmCM3_CM_ICSC_C23_C24_BASE_IDX … #define mmCM3_CM_ICSC_C31_C32 … #define mmCM3_CM_ICSC_C31_C32_BASE_IDX … #define mmCM3_CM_ICSC_C33_C34 … #define mmCM3_CM_ICSC_C33_C34_BASE_IDX … #define mmCM3_CM_ICSC_B_C11_C12 … #define mmCM3_CM_ICSC_B_C11_C12_BASE_IDX … #define mmCM3_CM_ICSC_B_C13_C14 … #define mmCM3_CM_ICSC_B_C13_C14_BASE_IDX … #define mmCM3_CM_ICSC_B_C21_C22 … #define mmCM3_CM_ICSC_B_C21_C22_BASE_IDX … #define mmCM3_CM_ICSC_B_C23_C24 … #define mmCM3_CM_ICSC_B_C23_C24_BASE_IDX … #define mmCM3_CM_ICSC_B_C31_C32 … #define mmCM3_CM_ICSC_B_C31_C32_BASE_IDX … #define mmCM3_CM_ICSC_B_C33_C34 … #define mmCM3_CM_ICSC_B_C33_C34_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_CONTROL … #define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C11_C12 … #define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C13_C14 … #define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C21_C22 … #define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C23_C24 … #define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C31_C32 … #define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_C33_C34 … #define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_B_C11_C12 … #define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_B_C13_C14 … #define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_B_C21_C22 … #define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_B_C23_C24 … #define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_B_C31_C32 … #define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX … #define mmCM3_CM_GAMUT_REMAP_B_C33_C34 … #define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX … #define mmCM3_CM_BIAS_CR_R … #define mmCM3_CM_BIAS_CR_R_BASE_IDX … #define mmCM3_CM_BIAS_Y_G_CB_B … #define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX … #define mmCM3_CM_DGAM_CONTROL … #define mmCM3_CM_DGAM_CONTROL_BASE_IDX … #define mmCM3_CM_DGAM_LUT_INDEX … #define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX … #define mmCM3_CM_DGAM_LUT_DATA … #define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX … #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK … #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_START_CNTL_B … #define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_START_CNTL_G … #define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_START_CNTL_R … #define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R … #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R … #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R … #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_0_1 … #define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_2_3 … #define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_4_5 … #define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_6_7 … #define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_8_9 … #define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_10_11 … #define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_12_13 … #define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM3_CM_DGAM_RAMA_REGION_14_15 … #define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_START_CNTL_B … #define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_START_CNTL_G … #define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_START_CNTL_R … #define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R … #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R … #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R … #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_0_1 … #define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_2_3 … #define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_4_5 … #define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_6_7 … #define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_8_9 … #define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_10_11 … #define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_12_13 … #define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM3_CM_DGAM_RAMB_REGION_14_15 … #define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM3_CM_BLNDGAM_CONTROL … #define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX … #define mmCM3_CM_BLNDGAM_LUT_INDEX … #define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX … #define mmCM3_CM_BLNDGAM_LUT_DATA … #define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX … #define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK … #define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B … #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G … #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R … #define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B … #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G … #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R … #define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R … #define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 … #define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B … #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G … #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R … #define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B … #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G … #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R … #define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R … #define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX … #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 … #define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX … #define mmCM3_CM_HDR_MULT_COEF … #define mmCM3_CM_HDR_MULT_COEF_BASE_IDX … #define mmCM3_CM_MEM_PWR_CTRL … #define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX … #define mmCM3_CM_MEM_PWR_STATUS … #define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX … #define mmCM3_CM_DEALPHA … #define mmCM3_CM_DEALPHA_BASE_IDX … #define mmCM3_CM_COEF_FORMAT … #define mmCM3_CM_COEF_FORMAT_BASE_IDX … #define mmCM3_CM_SHAPER_CONTROL … #define mmCM3_CM_SHAPER_CONTROL_BASE_IDX … #define mmCM3_CM_SHAPER_OFFSET_R … #define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX … #define mmCM3_CM_SHAPER_OFFSET_G … #define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX … #define mmCM3_CM_SHAPER_OFFSET_B … #define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX … #define mmCM3_CM_SHAPER_SCALE_R … #define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX … #define mmCM3_CM_SHAPER_SCALE_G_B … #define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX … #define mmCM3_CM_SHAPER_LUT_INDEX … #define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX … #define mmCM3_CM_SHAPER_LUT_DATA … #define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX … #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK … #define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B … #define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G … #define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R … #define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B … #define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G … #define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R … #define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_0_1 … #define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_2_3 … #define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_4_5 … #define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_6_7 … #define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_8_9 … #define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_10_11 … #define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_12_13 … #define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_14_15 … #define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_16_17 … #define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_18_19 … #define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_20_21 … #define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_22_23 … #define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_24_25 … #define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_26_27 … #define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_28_29 … #define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_30_31 … #define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX … #define mmCM3_CM_SHAPER_RAMA_REGION_32_33 … #define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B … #define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G … #define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R … #define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B … #define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G … #define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R … #define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_0_1 … #define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_2_3 … #define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_4_5 … #define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_6_7 … #define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_8_9 … #define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_10_11 … #define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_12_13 … #define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_14_15 … #define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_16_17 … #define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_18_19 … #define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_20_21 … #define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_22_23 … #define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_24_25 … #define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_26_27 … #define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_28_29 … #define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_30_31 … #define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX … #define mmCM3_CM_SHAPER_RAMB_REGION_32_33 … #define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX … #define mmCM3_CM_MEM_PWR_CTRL2 … #define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX … #define mmCM3_CM_MEM_PWR_STATUS2 … #define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX … #define mmCM3_CM_3DLUT_MODE … #define mmCM3_CM_3DLUT_MODE_BASE_IDX … #define mmCM3_CM_3DLUT_INDEX … #define mmCM3_CM_3DLUT_INDEX_BASE_IDX … #define mmCM3_CM_3DLUT_DATA … #define mmCM3_CM_3DLUT_DATA_BASE_IDX … #define mmCM3_CM_3DLUT_DATA_30BIT … #define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX … #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL … #define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX … #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR … #define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX … #define mmCM3_CM_3DLUT_OUT_OFFSET_R … #define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX … #define mmCM3_CM_3DLUT_OUT_OFFSET_G … #define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX … #define mmCM3_CM_3DLUT_OUT_OFFSET_B … #define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX … #define mmCM3_CM_TEST_DEBUG_INDEX … #define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX … #define mmCM3_CM_TEST_DEBUG_DATA … #define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc0_dispdec // base address: 0x0 #define mmMPCC0_MPCC_TOP_SEL … #define mmMPCC0_MPCC_TOP_SEL_BASE_IDX … #define mmMPCC0_MPCC_BOT_SEL … #define mmMPCC0_MPCC_BOT_SEL_BASE_IDX … #define mmMPCC0_MPCC_OPP_ID … #define mmMPCC0_MPCC_OPP_ID_BASE_IDX … #define mmMPCC0_MPCC_CONTROL … #define mmMPCC0_MPCC_CONTROL_BASE_IDX … #define mmMPCC0_MPCC_SM_CONTROL … #define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX … #define mmMPCC0_MPCC_UPDATE_LOCK_SEL … #define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define mmMPCC0_MPCC_TOP_GAIN … #define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX … #define mmMPCC0_MPCC_BOT_GAIN_INSIDE … #define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX … #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE … #define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX … #define mmMPCC0_MPCC_BG_R_CR … #define mmMPCC0_MPCC_BG_R_CR_BASE_IDX … #define mmMPCC0_MPCC_BG_G_Y … #define mmMPCC0_MPCC_BG_G_Y_BASE_IDX … #define mmMPCC0_MPCC_BG_B_CB … #define mmMPCC0_MPCC_BG_B_CB_BASE_IDX … #define mmMPCC0_MPCC_MEM_PWR_CTRL … #define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX … #define mmMPCC0_MPCC_STALL_STATUS … #define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX … #define mmMPCC0_MPCC_STATUS … #define mmMPCC0_MPCC_STATUS_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc1_dispdec // base address: 0x6c #define mmMPCC1_MPCC_TOP_SEL … #define mmMPCC1_MPCC_TOP_SEL_BASE_IDX … #define mmMPCC1_MPCC_BOT_SEL … #define mmMPCC1_MPCC_BOT_SEL_BASE_IDX … #define mmMPCC1_MPCC_OPP_ID … #define mmMPCC1_MPCC_OPP_ID_BASE_IDX … #define mmMPCC1_MPCC_CONTROL … #define mmMPCC1_MPCC_CONTROL_BASE_IDX … #define mmMPCC1_MPCC_SM_CONTROL … #define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX … #define mmMPCC1_MPCC_UPDATE_LOCK_SEL … #define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define mmMPCC1_MPCC_TOP_GAIN … #define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX … #define mmMPCC1_MPCC_BOT_GAIN_INSIDE … #define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX … #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE … #define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX … #define mmMPCC1_MPCC_BG_R_CR … #define mmMPCC1_MPCC_BG_R_CR_BASE_IDX … #define mmMPCC1_MPCC_BG_G_Y … #define mmMPCC1_MPCC_BG_G_Y_BASE_IDX … #define mmMPCC1_MPCC_BG_B_CB … #define mmMPCC1_MPCC_BG_B_CB_BASE_IDX … #define mmMPCC1_MPCC_MEM_PWR_CTRL … #define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX … #define mmMPCC1_MPCC_STALL_STATUS … #define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX … #define mmMPCC1_MPCC_STATUS … #define mmMPCC1_MPCC_STATUS_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc2_dispdec // base address: 0xd8 #define mmMPCC2_MPCC_TOP_SEL … #define mmMPCC2_MPCC_TOP_SEL_BASE_IDX … #define mmMPCC2_MPCC_BOT_SEL … #define mmMPCC2_MPCC_BOT_SEL_BASE_IDX … #define mmMPCC2_MPCC_OPP_ID … #define mmMPCC2_MPCC_OPP_ID_BASE_IDX … #define mmMPCC2_MPCC_CONTROL … #define mmMPCC2_MPCC_CONTROL_BASE_IDX … #define mmMPCC2_MPCC_SM_CONTROL … #define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX … #define mmMPCC2_MPCC_UPDATE_LOCK_SEL … #define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define mmMPCC2_MPCC_TOP_GAIN … #define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX … #define mmMPCC2_MPCC_BOT_GAIN_INSIDE … #define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX … #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE … #define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX … #define mmMPCC2_MPCC_BG_R_CR … #define mmMPCC2_MPCC_BG_R_CR_BASE_IDX … #define mmMPCC2_MPCC_BG_G_Y … #define mmMPCC2_MPCC_BG_G_Y_BASE_IDX … #define mmMPCC2_MPCC_BG_B_CB … #define mmMPCC2_MPCC_BG_B_CB_BASE_IDX … #define mmMPCC2_MPCC_MEM_PWR_CTRL … #define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX … #define mmMPCC2_MPCC_STALL_STATUS … #define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX … #define mmMPCC2_MPCC_STATUS … #define mmMPCC2_MPCC_STATUS_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc3_dispdec // base address: 0x144 #define mmMPCC3_MPCC_TOP_SEL … #define mmMPCC3_MPCC_TOP_SEL_BASE_IDX … #define mmMPCC3_MPCC_BOT_SEL … #define mmMPCC3_MPCC_BOT_SEL_BASE_IDX … #define mmMPCC3_MPCC_OPP_ID … #define mmMPCC3_MPCC_OPP_ID_BASE_IDX … #define mmMPCC3_MPCC_CONTROL … #define mmMPCC3_MPCC_CONTROL_BASE_IDX … #define mmMPCC3_MPCC_SM_CONTROL … #define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX … #define mmMPCC3_MPCC_UPDATE_LOCK_SEL … #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define mmMPCC3_MPCC_TOP_GAIN … #define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX … #define mmMPCC3_MPCC_BOT_GAIN_INSIDE … #define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX … #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE … #define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX … #define mmMPCC3_MPCC_BG_R_CR … #define mmMPCC3_MPCC_BG_R_CR_BASE_IDX … #define mmMPCC3_MPCC_BG_G_Y … #define mmMPCC3_MPCC_BG_G_Y_BASE_IDX … #define mmMPCC3_MPCC_BG_B_CB … #define mmMPCC3_MPCC_BG_B_CB_BASE_IDX … #define mmMPCC3_MPCC_MEM_PWR_CTRL … #define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX … #define mmMPCC3_MPCC_STALL_STATUS … #define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX … #define mmMPCC3_MPCC_STATUS … #define mmMPCC3_MPCC_STATUS_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc4_dispdec // base address: 0x1b0 #define mmMPCC4_MPCC_TOP_SEL … #define mmMPCC4_MPCC_TOP_SEL_BASE_IDX … #define mmMPCC4_MPCC_BOT_SEL … #define mmMPCC4_MPCC_BOT_SEL_BASE_IDX … #define mmMPCC4_MPCC_OPP_ID … #define mmMPCC4_MPCC_OPP_ID_BASE_IDX … #define mmMPCC4_MPCC_CONTROL … #define mmMPCC4_MPCC_CONTROL_BASE_IDX … #define mmMPCC4_MPCC_SM_CONTROL … #define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX … #define mmMPCC4_MPCC_UPDATE_LOCK_SEL … #define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX … #define mmMPCC4_MPCC_TOP_GAIN … #define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX … #define mmMPCC4_MPCC_BOT_GAIN_INSIDE … #define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX … #define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE … #define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX … #define mmMPCC4_MPCC_BG_R_CR … #define mmMPCC4_MPCC_BG_R_CR_BASE_IDX … #define mmMPCC4_MPCC_BG_G_Y … #define mmMPCC4_MPCC_BG_G_Y_BASE_IDX … #define mmMPCC4_MPCC_BG_B_CB … #define mmMPCC4_MPCC_BG_B_CB_BASE_IDX … #define mmMPCC4_MPCC_MEM_PWR_CTRL … #define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX … #define mmMPCC4_MPCC_STALL_STATUS … #define mmMPCC4_MPCC_STALL_STATUS_BASE_IDX … #define mmMPCC4_MPCC_STATUS … #define mmMPCC4_MPCC_STATUS_BASE_IDX … // addressBlock: dce_dc_mpc_mpc_cfg_dispdec // base address: 0x0 #define mmMPC_CLOCK_CONTROL … #define mmMPC_CLOCK_CONTROL_BASE_IDX … #define mmMPC_SOFT_RESET … #define mmMPC_SOFT_RESET_BASE_IDX … #define mmMPC_CRC_CTRL … #define mmMPC_CRC_CTRL_BASE_IDX … #define mmMPC_CRC_SEL_CONTROL … #define mmMPC_CRC_SEL_CONTROL_BASE_IDX … #define mmMPC_CRC_RESULT_AR … #define mmMPC_CRC_RESULT_AR_BASE_IDX … #define mmMPC_CRC_RESULT_GB … #define mmMPC_CRC_RESULT_GB_BASE_IDX … #define mmMPC_CRC_RESULT_C … #define mmMPC_CRC_RESULT_C_BASE_IDX … #define mmMPC_PERFMON_EVENT_CTRL … #define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX … #define mmMPC_BYPASS_BG_AR … #define mmMPC_BYPASS_BG_AR_BASE_IDX … #define mmMPC_BYPASS_BG_GB … #define mmMPC_BYPASS_BG_GB_BASE_IDX … #define mmMPC_STALL_GRACE_WINDOW … #define mmMPC_STALL_GRACE_WINDOW_BASE_IDX … #define mmMPC_HOST_READ_CONTROL … #define mmMPC_HOST_READ_CONTROL_BASE_IDX … #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 … #define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX … #define mmADR_CFG_VUPDATE_LOCK_SET0 … #define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX … #define mmADR_VUPDATE_LOCK_SET0 … #define mmADR_VUPDATE_LOCK_SET0_BASE_IDX … #define mmCFG_VUPDATE_LOCK_SET0 … #define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX … #define mmCUR_VUPDATE_LOCK_SET0 … #define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX … #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 … #define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX … #define mmADR_CFG_VUPDATE_LOCK_SET1 … #define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX … #define mmADR_VUPDATE_LOCK_SET1 … #define mmADR_VUPDATE_LOCK_SET1_BASE_IDX … #define mmCFG_VUPDATE_LOCK_SET1 … #define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX … #define mmCUR_VUPDATE_LOCK_SET1 … #define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX … #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 … #define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX … #define mmADR_CFG_VUPDATE_LOCK_SET2 … #define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX … #define mmADR_VUPDATE_LOCK_SET2 … #define mmADR_VUPDATE_LOCK_SET2_BASE_IDX … #define mmCFG_VUPDATE_LOCK_SET2 … #define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX … #define mmCUR_VUPDATE_LOCK_SET2 … #define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX … #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 … #define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX … #define mmADR_CFG_VUPDATE_LOCK_SET3 … #define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX … #define mmADR_VUPDATE_LOCK_SET3 … #define mmADR_VUPDATE_LOCK_SET3_BASE_IDX … #define mmCFG_VUPDATE_LOCK_SET3 … #define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX … #define mmCUR_VUPDATE_LOCK_SET3 … #define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX … #define mmMPC_OUT0_MUX … #define mmMPC_OUT0_MUX_BASE_IDX … #define mmMPC_OUT0_DENORM_CONTROL … #define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX … #define mmMPC_OUT0_DENORM_CLAMP_G_Y … #define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX … #define mmMPC_OUT0_DENORM_CLAMP_B_CB … #define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX … #define mmMPC_OUT1_MUX … #define mmMPC_OUT1_MUX_BASE_IDX … #define mmMPC_OUT1_DENORM_CONTROL … #define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX … #define mmMPC_OUT1_DENORM_CLAMP_G_Y … #define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX … #define mmMPC_OUT1_DENORM_CLAMP_B_CB … #define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec // base address: 0x0 #define mmMPCC_OGAM0_MPCC_OGAM_MODE … #define mmMPCC_OGAM0_MPCC_OGAM_MODE_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX … #define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA … #define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL … #define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 … #define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec // base address: 0x104 #define mmMPCC_OGAM1_MPCC_OGAM_MODE … #define mmMPCC_OGAM1_MPCC_OGAM_MODE_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX … #define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA … #define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL … #define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 … #define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec // base address: 0x208 #define mmMPCC_OGAM2_MPCC_OGAM_MODE … #define mmMPCC_OGAM2_MPCC_OGAM_MODE_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX … #define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA … #define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL … #define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 … #define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec // base address: 0x30c #define mmMPCC_OGAM3_MPCC_OGAM_MODE … #define mmMPCC_OGAM3_MPCC_OGAM_MODE_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX … #define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA … #define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL … #define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 … #define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX … // addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec // base address: 0x410 #define mmMPCC_OGAM4_MPCC_OGAM_MODE … #define mmMPCC_OGAM4_MPCC_OGAM_MODE_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX … #define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA … #define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL … #define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 … #define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX … // addressBlock: dce_dc_mpc_mpc_ocsc_dispdec // base address: 0x0 #define mmMPC_OUT_CSC_COEF_FORMAT … #define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX … #define mmMPC_OUT0_CSC_MODE … #define mmMPC_OUT0_CSC_MODE_BASE_IDX … #define mmMPC_OUT0_CSC_C11_C12_A … #define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX … #define mmMPC_OUT0_CSC_C13_C14_A … #define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX … #define mmMPC_OUT0_CSC_C21_C22_A … #define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX … #define mmMPC_OUT0_CSC_C23_C24_A … #define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX … #define mmMPC_OUT0_CSC_C31_C32_A … #define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX … #define mmMPC_OUT0_CSC_C33_C34_A … #define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX … #define mmMPC_OUT0_CSC_C11_C12_B … #define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX … #define mmMPC_OUT0_CSC_C13_C14_B … #define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX … #define mmMPC_OUT0_CSC_C21_C22_B … #define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX … #define mmMPC_OUT0_CSC_C23_C24_B … #define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX … #define mmMPC_OUT0_CSC_C31_C32_B … #define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX … #define mmMPC_OUT0_CSC_C33_C34_B … #define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX … #define mmMPC_OUT1_CSC_MODE … #define mmMPC_OUT1_CSC_MODE_BASE_IDX … #define mmMPC_OUT1_CSC_C11_C12_A … #define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX … #define mmMPC_OUT1_CSC_C13_C14_A … #define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX … #define mmMPC_OUT1_CSC_C21_C22_A … #define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX … #define mmMPC_OUT1_CSC_C23_C24_A … #define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX … #define mmMPC_OUT1_CSC_C31_C32_A … #define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX … #define mmMPC_OUT1_CSC_C33_C34_A … #define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX … #define mmMPC_OUT1_CSC_C11_C12_B … #define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX … #define mmMPC_OUT1_CSC_C13_C14_B … #define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX … #define mmMPC_OUT1_CSC_C21_C22_B … #define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX … #define mmMPC_OUT1_CSC_C23_C24_B … #define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX … #define mmMPC_OUT1_CSC_C31_C32_B … #define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX … #define mmMPC_OUT1_CSC_C33_C34_B … #define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX … // addressBlock: dce_dc_opp_fmt0_dispdec // base address: 0x0 #define mmFMT0_FMT_CLAMP_COMPONENT_R … #define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT0_FMT_CLAMP_COMPONENT_G … #define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT0_FMT_CLAMP_COMPONENT_B … #define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT0_FMT_DYNAMIC_EXP_CNTL … #define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT0_FMT_CONTROL … #define mmFMT0_FMT_CONTROL_BASE_IDX … #define mmFMT0_FMT_BIT_DEPTH_CONTROL … #define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT0_FMT_DITHER_RAND_R_SEED … #define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT0_FMT_DITHER_RAND_G_SEED … #define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT0_FMT_DITHER_RAND_B_SEED … #define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT0_FMT_CLAMP_CNTL … #define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT0_FMT_MAP420_MEMORY_CONTROL … #define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … #define mmFMT0_FMT_422_CONTROL … #define mmFMT0_FMT_422_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_dpg0_dispdec // base address: 0x0 #define mmDPG0_DPG_CONTROL … #define mmDPG0_DPG_CONTROL_BASE_IDX … #define mmDPG0_DPG_RAMP_CONTROL … #define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX … #define mmDPG0_DPG_DIMENSIONS … #define mmDPG0_DPG_DIMENSIONS_BASE_IDX … #define mmDPG0_DPG_COLOUR_R_CR … #define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX … #define mmDPG0_DPG_COLOUR_G_Y … #define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX … #define mmDPG0_DPG_COLOUR_B_CB … #define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX … #define mmDPG0_DPG_OFFSET_SEGMENT … #define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX … #define mmDPG0_DPG_STATUS … #define mmDPG0_DPG_STATUS_BASE_IDX … // addressBlock: dce_dc_opp_oppbuf0_dispdec // base address: 0x0 #define mmOPPBUF0_OPPBUF_CONTROL … #define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX … #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 … #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 … #define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe0_dispdec // base address: 0x0 #define mmOPP_PIPE0_OPP_PIPE_CONTROL … #define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec // base address: 0x0 #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 … #define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dce_dc_opp_fmt1_dispdec // base address: 0x168 #define mmFMT1_FMT_CLAMP_COMPONENT_R … #define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX … #define mmFMT1_FMT_CLAMP_COMPONENT_G … #define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX … #define mmFMT1_FMT_CLAMP_COMPONENT_B … #define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX … #define mmFMT1_FMT_DYNAMIC_EXP_CNTL … #define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX … #define mmFMT1_FMT_CONTROL … #define mmFMT1_FMT_CONTROL_BASE_IDX … #define mmFMT1_FMT_BIT_DEPTH_CONTROL … #define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX … #define mmFMT1_FMT_DITHER_RAND_R_SEED … #define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX … #define mmFMT1_FMT_DITHER_RAND_G_SEED … #define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX … #define mmFMT1_FMT_DITHER_RAND_B_SEED … #define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX … #define mmFMT1_FMT_CLAMP_CNTL … #define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX … #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL … #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX … #define mmFMT1_FMT_MAP420_MEMORY_CONTROL … #define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX … #define mmFMT1_FMT_422_CONTROL … #define mmFMT1_FMT_422_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_dpg1_dispdec // base address: 0x168 #define mmDPG1_DPG_CONTROL … #define mmDPG1_DPG_CONTROL_BASE_IDX … #define mmDPG1_DPG_RAMP_CONTROL … #define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX … #define mmDPG1_DPG_DIMENSIONS … #define mmDPG1_DPG_DIMENSIONS_BASE_IDX … #define mmDPG1_DPG_COLOUR_R_CR … #define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX … #define mmDPG1_DPG_COLOUR_G_Y … #define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX … #define mmDPG1_DPG_COLOUR_B_CB … #define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX … #define mmDPG1_DPG_OFFSET_SEGMENT … #define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX … #define mmDPG1_DPG_STATUS … #define mmDPG1_DPG_STATUS_BASE_IDX … // addressBlock: dce_dc_opp_oppbuf1_dispdec // base address: 0x168 #define mmOPPBUF1_OPPBUF_CONTROL … #define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX … #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 … #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX … #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 … #define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe1_dispdec // base address: 0x168 #define mmOPP_PIPE1_OPP_PIPE_CONTROL … #define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX … // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec // base address: 0x168 #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 … #define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX … // addressBlock: dce_dc_opp_opp_top_dispdec // base address: 0x0 #define mmOPP_TOP_CLK_CONTROL … #define mmOPP_TOP_CLK_CONTROL_BASE_IDX … // addressBlock: dce_dc_optc_odm0_dispdec // base address: 0x0 #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL … #define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define mmODM0_OPTC_DATA_SOURCE_SELECT … #define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define mmODM0_OPTC_DATA_FORMAT_CONTROL … #define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX … #define mmODM0_OPTC_BYTES_PER_PIXEL … #define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX … #define mmODM0_OPTC_WIDTH_CONTROL … #define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX … #define mmODM0_OPTC_INPUT_CLOCK_CONTROL … #define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … // addressBlock: dce_dc_optc_odm1_dispdec // base address: 0x40 #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL … #define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX … #define mmODM1_OPTC_DATA_SOURCE_SELECT … #define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX … #define mmODM1_OPTC_DATA_FORMAT_CONTROL … #define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX … #define mmODM1_OPTC_BYTES_PER_PIXEL … #define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX … #define mmODM1_OPTC_WIDTH_CONTROL … #define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX … #define mmODM1_OPTC_INPUT_CLOCK_CONTROL … #define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX … // addressBlock: dce_dc_optc_otg0_dispdec // base address: 0x0 #define mmOTG0_OTG_H_TOTAL … #define mmOTG0_OTG_H_TOTAL_BASE_IDX … #define mmOTG0_OTG_H_BLANK_START_END … #define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX … #define mmOTG0_OTG_H_SYNC_A … #define mmOTG0_OTG_H_SYNC_A_BASE_IDX … #define mmOTG0_OTG_H_SYNC_A_CNTL … #define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX … #define mmOTG0_OTG_H_TIMING_CNTL … #define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX … #define mmOTG0_OTG_V_TOTAL … #define mmOTG0_OTG_V_TOTAL_BASE_IDX … #define mmOTG0_OTG_V_TOTAL_MIN … #define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX … #define mmOTG0_OTG_V_TOTAL_MAX … #define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX … #define mmOTG0_OTG_V_TOTAL_MID … #define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX … #define mmOTG0_OTG_V_TOTAL_CONTROL … #define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX … #define mmOTG0_OTG_V_TOTAL_INT_STATUS … #define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS … #define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmOTG0_OTG_V_BLANK_START_END … #define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX … #define mmOTG0_OTG_V_SYNC_A … #define mmOTG0_OTG_V_SYNC_A_BASE_IDX … #define mmOTG0_OTG_V_SYNC_A_CNTL … #define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX … #define mmOTG0_OTG_TRIGA_CNTL … #define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX … #define mmOTG0_OTG_TRIGA_MANUAL_TRIG … #define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmOTG0_OTG_TRIGB_CNTL … #define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX … #define mmOTG0_OTG_TRIGB_MANUAL_TRIG … #define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL … #define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE … #define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmOTG0_OTG_CONTROL … #define mmOTG0_OTG_CONTROL_BASE_IDX … #define mmOTG0_OTG_BLANK_CONTROL … #define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX … #define mmOTG0_OTG_INTERLACE_CONTROL … #define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX … #define mmOTG0_OTG_INTERLACE_STATUS … #define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX … #define mmOTG0_OTG_PIXEL_DATA_READBACK0 … #define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define mmOTG0_OTG_PIXEL_DATA_READBACK1 … #define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define mmOTG0_OTG_STATUS … #define mmOTG0_OTG_STATUS_BASE_IDX … #define mmOTG0_OTG_STATUS_POSITION … #define mmOTG0_OTG_STATUS_POSITION_BASE_IDX … #define mmOTG0_OTG_NOM_VERT_POSITION … #define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX … #define mmOTG0_OTG_STATUS_FRAME_COUNT … #define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define mmOTG0_OTG_STATUS_VF_COUNT … #define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX … #define mmOTG0_OTG_STATUS_HV_COUNT … #define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX … #define mmOTG0_OTG_COUNT_CONTROL … #define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX … #define mmOTG0_OTG_COUNT_RESET … #define mmOTG0_OTG_COUNT_RESET_BASE_IDX … #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmOTG0_OTG_VERT_SYNC_CONTROL … #define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define mmOTG0_OTG_STEREO_STATUS … #define mmOTG0_OTG_STEREO_STATUS_BASE_IDX … #define mmOTG0_OTG_STEREO_CONTROL … #define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX … #define mmOTG0_OTG_SNAPSHOT_STATUS … #define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX … #define mmOTG0_OTG_SNAPSHOT_CONTROL … #define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define mmOTG0_OTG_SNAPSHOT_POSITION … #define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX … #define mmOTG0_OTG_SNAPSHOT_FRAME … #define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX … #define mmOTG0_OTG_INTERRUPT_CONTROL … #define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX … #define mmOTG0_OTG_UPDATE_LOCK … #define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX … #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL … #define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmOTG0_OTG_MASTER_EN … #define mmOTG0_OTG_MASTER_EN_BASE_IDX … #define mmOTG0_OTG_BLANK_DATA_COLOR … #define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX … #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT … #define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmOTG0_OTG_BLACK_COLOR … #define mmOTG0_OTG_BLACK_COLOR_BASE_IDX … #define mmOTG0_OTG_BLACK_COLOR_EXT … #define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION … #define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL … #define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION … #define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL … #define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION … #define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL … #define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC_CNTL … #define mmOTG0_OTG_CRC_CNTL_BASE_IDX … #define mmOTG0_OTG_CRC_CNTL2 … #define mmOTG0_OTG_CRC_CNTL2_BASE_IDX … #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL … #define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL … #define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL … #define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL … #define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC0_DATA_RG … #define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX … #define mmOTG0_OTG_CRC0_DATA_B … #define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX … #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL … #define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL … #define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL … #define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL … #define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG0_OTG_CRC1_DATA_RG … #define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX … #define mmOTG0_OTG_CRC1_DATA_B … #define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX … #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK … #define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmOTG0_OTG_STATIC_SCREEN_CONTROL … #define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmOTG0_OTG_3D_STRUCTURE_CONTROL … #define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmOTG0_OTG_GSL_VSYNC_GAP … #define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX … #define mmOTG0_OTG_MASTER_UPDATE_MODE … #define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define mmOTG0_OTG_CLOCK_CONTROL … #define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX … #define mmOTG0_OTG_VSTARTUP_PARAM … #define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX … #define mmOTG0_OTG_VUPDATE_PARAM … #define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX … #define mmOTG0_OTG_VREADY_PARAM … #define mmOTG0_OTG_VREADY_PARAM_BASE_IDX … #define mmOTG0_OTG_GLOBAL_SYNC_STATUS … #define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define mmOTG0_OTG_MASTER_UPDATE_LOCK … #define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define mmOTG0_OTG_GSL_CONTROL … #define mmOTG0_OTG_GSL_CONTROL_BASE_IDX … #define mmOTG0_OTG_GSL_WINDOW_X … #define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX … #define mmOTG0_OTG_GSL_WINDOW_Y … #define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX … #define mmOTG0_OTG_VUPDATE_KEEPOUT … #define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define mmOTG0_OTG_GLOBAL_CONTROL0 … #define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX … #define mmOTG0_OTG_GLOBAL_CONTROL1 … #define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX … #define mmOTG0_OTG_GLOBAL_CONTROL2 … #define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX … #define mmOTG0_OTG_GLOBAL_CONTROL3 … #define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX … #define mmOTG0_OTG_TRIG_MANUAL_CONTROL … #define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define mmOTG0_OTG_DRR_CONTROL … #define mmOTG0_OTG_DRR_CONTROL_BASE_IDX … #define mmOTG0_OTG_DSC_START_POSITION … #define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX … // addressBlock: dce_dc_optc_otg1_dispdec // base address: 0x200 #define mmOTG1_OTG_H_TOTAL … #define mmOTG1_OTG_H_TOTAL_BASE_IDX … #define mmOTG1_OTG_H_BLANK_START_END … #define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX … #define mmOTG1_OTG_H_SYNC_A … #define mmOTG1_OTG_H_SYNC_A_BASE_IDX … #define mmOTG1_OTG_H_SYNC_A_CNTL … #define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX … #define mmOTG1_OTG_H_TIMING_CNTL … #define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX … #define mmOTG1_OTG_V_TOTAL … #define mmOTG1_OTG_V_TOTAL_BASE_IDX … #define mmOTG1_OTG_V_TOTAL_MIN … #define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX … #define mmOTG1_OTG_V_TOTAL_MAX … #define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX … #define mmOTG1_OTG_V_TOTAL_MID … #define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX … #define mmOTG1_OTG_V_TOTAL_CONTROL … #define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX … #define mmOTG1_OTG_V_TOTAL_INT_STATUS … #define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX … #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS … #define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX … #define mmOTG1_OTG_V_BLANK_START_END … #define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX … #define mmOTG1_OTG_V_SYNC_A … #define mmOTG1_OTG_V_SYNC_A_BASE_IDX … #define mmOTG1_OTG_V_SYNC_A_CNTL … #define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX … #define mmOTG1_OTG_TRIGA_CNTL … #define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX … #define mmOTG1_OTG_TRIGA_MANUAL_TRIG … #define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX … #define mmOTG1_OTG_TRIGB_CNTL … #define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX … #define mmOTG1_OTG_TRIGB_MANUAL_TRIG … #define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX … #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL … #define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX … #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE … #define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX … #define mmOTG1_OTG_CONTROL … #define mmOTG1_OTG_CONTROL_BASE_IDX … #define mmOTG1_OTG_BLANK_CONTROL … #define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX … #define mmOTG1_OTG_INTERLACE_CONTROL … #define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX … #define mmOTG1_OTG_INTERLACE_STATUS … #define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX … #define mmOTG1_OTG_PIXEL_DATA_READBACK0 … #define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX … #define mmOTG1_OTG_PIXEL_DATA_READBACK1 … #define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX … #define mmOTG1_OTG_STATUS … #define mmOTG1_OTG_STATUS_BASE_IDX … #define mmOTG1_OTG_STATUS_POSITION … #define mmOTG1_OTG_STATUS_POSITION_BASE_IDX … #define mmOTG1_OTG_NOM_VERT_POSITION … #define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX … #define mmOTG1_OTG_STATUS_FRAME_COUNT … #define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX … #define mmOTG1_OTG_STATUS_VF_COUNT … #define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX … #define mmOTG1_OTG_STATUS_HV_COUNT … #define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX … #define mmOTG1_OTG_COUNT_CONTROL … #define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX … #define mmOTG1_OTG_COUNT_RESET … #define mmOTG1_OTG_COUNT_RESET_BASE_IDX … #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE … #define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX … #define mmOTG1_OTG_VERT_SYNC_CONTROL … #define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX … #define mmOTG1_OTG_STEREO_STATUS … #define mmOTG1_OTG_STEREO_STATUS_BASE_IDX … #define mmOTG1_OTG_STEREO_CONTROL … #define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX … #define mmOTG1_OTG_SNAPSHOT_STATUS … #define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX … #define mmOTG1_OTG_SNAPSHOT_CONTROL … #define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX … #define mmOTG1_OTG_SNAPSHOT_POSITION … #define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX … #define mmOTG1_OTG_SNAPSHOT_FRAME … #define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX … #define mmOTG1_OTG_INTERRUPT_CONTROL … #define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX … #define mmOTG1_OTG_UPDATE_LOCK … #define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX … #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL … #define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX … #define mmOTG1_OTG_MASTER_EN … #define mmOTG1_OTG_MASTER_EN_BASE_IDX … #define mmOTG1_OTG_BLANK_DATA_COLOR … #define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX … #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT … #define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX … #define mmOTG1_OTG_BLACK_COLOR … #define mmOTG1_OTG_BLACK_COLOR_BASE_IDX … #define mmOTG1_OTG_BLACK_COLOR_EXT … #define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION … #define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL … #define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION … #define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL … #define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION … #define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX … #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL … #define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC_CNTL … #define mmOTG1_OTG_CRC_CNTL_BASE_IDX … #define mmOTG1_OTG_CRC_CNTL2 … #define mmOTG1_OTG_CRC_CNTL2_BASE_IDX … #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL … #define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL … #define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL … #define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL … #define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC0_DATA_RG … #define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX … #define mmOTG1_OTG_CRC0_DATA_B … #define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX … #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL … #define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL … #define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL … #define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL … #define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX … #define mmOTG1_OTG_CRC1_DATA_RG … #define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX … #define mmOTG1_OTG_CRC1_DATA_B … #define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX … #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK … #define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX … #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK … #define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX … #define mmOTG1_OTG_STATIC_SCREEN_CONTROL … #define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX … #define mmOTG1_OTG_3D_STRUCTURE_CONTROL … #define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX … #define mmOTG1_OTG_GSL_VSYNC_GAP … #define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX … #define mmOTG1_OTG_MASTER_UPDATE_MODE … #define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX … #define mmOTG1_OTG_CLOCK_CONTROL … #define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX … #define mmOTG1_OTG_VSTARTUP_PARAM … #define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX … #define mmOTG1_OTG_VUPDATE_PARAM … #define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX … #define mmOTG1_OTG_VREADY_PARAM … #define mmOTG1_OTG_VREADY_PARAM_BASE_IDX … #define mmOTG1_OTG_GLOBAL_SYNC_STATUS … #define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX … #define mmOTG1_OTG_MASTER_UPDATE_LOCK … #define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX … #define mmOTG1_OTG_GSL_CONTROL … #define mmOTG1_OTG_GSL_CONTROL_BASE_IDX … #define mmOTG1_OTG_GSL_WINDOW_X … #define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX … #define mmOTG1_OTG_GSL_WINDOW_Y … #define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX … #define mmOTG1_OTG_VUPDATE_KEEPOUT … #define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX … #define mmOTG1_OTG_GLOBAL_CONTROL0 … #define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX … #define mmOTG1_OTG_GLOBAL_CONTROL1 … #define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX … #define mmOTG1_OTG_GLOBAL_CONTROL2 … #define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX … #define mmOTG1_OTG_GLOBAL_CONTROL3 … #define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX … #define mmOTG1_OTG_TRIG_MANUAL_CONTROL … #define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX … #define mmOTG1_OTG_DRR_CONTROL … #define mmOTG1_OTG_DRR_CONTROL_BASE_IDX … #define mmOTG1_OTG_DSC_START_POSITION … #define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX … // addressBlock: dce_dc_optc_optc_misc_dispdec // base address: 0x0 #define mmDWB_SOURCE_SELECT … #define mmDWB_SOURCE_SELECT_BASE_IDX … #define mmGSL_SOURCE_SELECT … #define mmGSL_SOURCE_SELECT_BASE_IDX … #define mmOPTC_CLOCK_CONTROL … #define mmOPTC_CLOCK_CONTROL_BASE_IDX … // addressBlock: dce_dc_dio_dout_i2c_dispdec // base address: 0x0 #define mmDC_I2C_CONTROL … #define mmDC_I2C_CONTROL_BASE_IDX … #define mmDC_I2C_ARBITRATION … #define mmDC_I2C_ARBITRATION_BASE_IDX … #define mmDC_I2C_INTERRUPT_CONTROL … #define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX … #define mmDC_I2C_SW_STATUS … #define mmDC_I2C_SW_STATUS_BASE_IDX … #define mmDC_I2C_DDC1_HW_STATUS … #define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC2_HW_STATUS … #define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX … #define mmDC_I2C_DDC1_SPEED … #define mmDC_I2C_DDC1_SPEED_BASE_IDX … #define mmDC_I2C_DDC1_SETUP … #define mmDC_I2C_DDC1_SETUP_BASE_IDX … #define mmDC_I2C_DDC2_SPEED … #define mmDC_I2C_DDC2_SPEED_BASE_IDX … #define mmDC_I2C_DDC2_SETUP … #define mmDC_I2C_DDC2_SETUP_BASE_IDX … #define mmDC_I2C_TRANSACTION0 … #define mmDC_I2C_TRANSACTION0_BASE_IDX … #define mmDC_I2C_TRANSACTION1 … #define mmDC_I2C_TRANSACTION1_BASE_IDX … #define mmDC_I2C_TRANSACTION2 … #define mmDC_I2C_TRANSACTION2_BASE_IDX … #define mmDC_I2C_TRANSACTION3 … #define mmDC_I2C_TRANSACTION3_BASE_IDX … #define mmDC_I2C_DATA … #define mmDC_I2C_DATA_BASE_IDX … #define mmDC_I2C_EDID_DETECT_CTRL … #define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX … #define mmDC_I2C_READ_REQUEST_INTERRUPT … #define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX … // addressBlock: dce_dc_dio_dio_misc_dispdec // base address: 0x0 #define mmDIO_SCRATCH0 … #define mmDIO_SCRATCH0_BASE_IDX … #define mmDIO_SCRATCH1 … #define mmDIO_SCRATCH1_BASE_IDX … #define mmDIO_SCRATCH2 … #define mmDIO_SCRATCH2_BASE_IDX … #define mmDIO_SCRATCH3 … #define mmDIO_SCRATCH3_BASE_IDX … #define mmDIO_SCRATCH4 … #define mmDIO_SCRATCH4_BASE_IDX … #define mmDIO_SCRATCH5 … #define mmDIO_SCRATCH5_BASE_IDX … #define mmDIO_SCRATCH6 … #define mmDIO_SCRATCH6_BASE_IDX … #define mmDIO_SCRATCH7 … #define mmDIO_SCRATCH7_BASE_IDX … #define mmDIO_MEM_PWR_STATUS … #define mmDIO_MEM_PWR_STATUS_BASE_IDX … #define mmDIO_MEM_PWR_CTRL … #define mmDIO_MEM_PWR_CTRL_BASE_IDX … #define mmDIO_MEM_PWR_CTRL2 … #define mmDIO_MEM_PWR_CTRL2_BASE_IDX … #define mmDIO_CLK_CNTL … #define mmDIO_CLK_CNTL_BASE_IDX … #define mmDIO_MEM_PWR_CTRL3 … #define mmDIO_MEM_PWR_CTRL3_BASE_IDX … #define mmDIO_POWER_MANAGEMENT_CNTL … #define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX … #define mmDIG_SOFT_RESET … #define mmDIG_SOFT_RESET_BASE_IDX … #define mmDIO_MEM_PWR_STATUS1 … #define mmDIO_MEM_PWR_STATUS1_BASE_IDX … #define mmDIO_CLK_CNTL2 … #define mmDIO_CLK_CNTL2_BASE_IDX … #define mmDIO_CLK_CNTL3 … #define mmDIO_CLK_CNTL3_BASE_IDX … #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL … #define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX … #define mmDIO_GENERIC_INTERRUPT_MESSAGE … #define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX … #define mmDIO_GENERIC_INTERRUPT_CLEAR … #define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX … // addressBlock: dce_dc_dio_hpd0_dispdec // base address: 0x0 #define mmHPD0_DC_HPD_INT_STATUS … #define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD0_DC_HPD_INT_CONTROL … #define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD0_DC_HPD_CONTROL … #define mmHPD0_DC_HPD_CONTROL_BASE_IDX … #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_dio_hpd1_dispdec // base address: 0x20 #define mmHPD1_DC_HPD_INT_STATUS … #define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX … #define mmHPD1_DC_HPD_INT_CONTROL … #define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX … #define mmHPD1_DC_HPD_CONTROL … #define mmHPD1_DC_HPD_CONTROL_BASE_IDX … #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL … #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX … #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL … #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX … // addressBlock: dce_dc_dio_dp_aux0_dispdec // base address: 0x0 #define mmDP_AUX0_AUX_CONTROL … #define mmDP_AUX0_AUX_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_SW_CONTROL … #define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_ARB_CONTROL … #define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_INTERRUPT_CONTROL … #define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_SW_STATUS … #define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_LS_STATUS … #define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_SW_DATA … #define mmDP_AUX0_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX0_AUX_LS_DATA … #define mmDP_AUX0_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_TX_CONTROL … #define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_TX_STATUS … #define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX0_AUX_DPHY_RX_STATUS … #define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX … // addressBlock: dce_dc_dio_dp_aux1_dispdec // base address: 0x70 #define mmDP_AUX1_AUX_CONTROL … #define mmDP_AUX1_AUX_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_SW_CONTROL … #define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_ARB_CONTROL … #define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_INTERRUPT_CONTROL … #define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_SW_STATUS … #define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_LS_STATUS … #define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_SW_DATA … #define mmDP_AUX1_AUX_SW_DATA_BASE_IDX … #define mmDP_AUX1_AUX_LS_DATA … #define mmDP_AUX1_AUX_LS_DATA_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL … #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_TX_CONTROL … #define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 … #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_TX_STATUS … #define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX … #define mmDP_AUX1_AUX_DPHY_RX_STATUS … #define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX … // addressBlock: dce_dc_dio_dig0_dispdec // base address: 0x0 #define mmDIG0_DIG_FE_CNTL … #define mmDIG0_DIG_FE_CNTL_BASE_IDX … #define mmDIG0_DIG_OUTPUT_CRC_CNTL … #define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG0_DIG_OUTPUT_CRC_RESULT … #define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG0_DIG_CLOCK_PATTERN … #define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG0_DIG_TEST_PATTERN … #define mmDIG0_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG0_DIG_RANDOM_PATTERN_SEED … #define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG0_DIG_FIFO_STATUS … #define mmDIG0_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG0_HDMI_METADATA_PACKET_CONTROL … #define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX … #define mmDIG0_HDMI_CONTROL … #define mmDIG0_HDMI_CONTROL_BASE_IDX … #define mmDIG0_HDMI_STATUS … #define mmDIG0_HDMI_STATUS_BASE_IDX … #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG0_HDMI_ACR_PACKET_CONTROL … #define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG0_HDMI_VBI_PACKET_CONTROL … #define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG0_HDMI_INFOFRAME_CONTROL0 … #define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG0_HDMI_INFOFRAME_CONTROL1 … #define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG0_AFMT_INTERRUPT_STATUS … #define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG0_HDMI_GC … #define mmDIG0_HDMI_GC_BASE_IDX … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG0_AFMT_ISRC1_0 … #define mmDIG0_AFMT_ISRC1_0_BASE_IDX … #define mmDIG0_AFMT_ISRC1_1 … #define mmDIG0_AFMT_ISRC1_1_BASE_IDX … #define mmDIG0_AFMT_ISRC1_2 … #define mmDIG0_AFMT_ISRC1_2_BASE_IDX … #define mmDIG0_AFMT_ISRC1_3 … #define mmDIG0_AFMT_ISRC1_3_BASE_IDX … #define mmDIG0_AFMT_ISRC1_4 … #define mmDIG0_AFMT_ISRC1_4_BASE_IDX … #define mmDIG0_AFMT_ISRC2_0 … #define mmDIG0_AFMT_ISRC2_0_BASE_IDX … #define mmDIG0_AFMT_ISRC2_1 … #define mmDIG0_AFMT_ISRC2_1_BASE_IDX … #define mmDIG0_AFMT_ISRC2_2 … #define mmDIG0_AFMT_ISRC2_2_BASE_IDX … #define mmDIG0_AFMT_ISRC2_3 … #define mmDIG0_AFMT_ISRC2_3_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define mmDIG0_HDMI_DB_CONTROL … #define mmDIG0_HDMI_DB_CONTROL_BASE_IDX … #define mmDIG0_DME_CONTROL … #define mmDIG0_DME_CONTROL_BASE_IDX … #define mmDIG0_AFMT_MPEG_INFO0 … #define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG0_AFMT_MPEG_INFO1 … #define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG0_AFMT_GENERIC_HDR … #define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG0_AFMT_GENERIC_0 … #define mmDIG0_AFMT_GENERIC_0_BASE_IDX … #define mmDIG0_AFMT_GENERIC_1 … #define mmDIG0_AFMT_GENERIC_1_BASE_IDX … #define mmDIG0_AFMT_GENERIC_2 … #define mmDIG0_AFMT_GENERIC_2_BASE_IDX … #define mmDIG0_AFMT_GENERIC_3 … #define mmDIG0_AFMT_GENERIC_3_BASE_IDX … #define mmDIG0_AFMT_GENERIC_4 … #define mmDIG0_AFMT_GENERIC_4_BASE_IDX … #define mmDIG0_AFMT_GENERIC_5 … #define mmDIG0_AFMT_GENERIC_5_BASE_IDX … #define mmDIG0_AFMT_GENERIC_6 … #define mmDIG0_AFMT_GENERIC_6_BASE_IDX … #define mmDIG0_AFMT_GENERIC_7 … #define mmDIG0_AFMT_GENERIC_7_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG0_HDMI_ACR_32_0 … #define mmDIG0_HDMI_ACR_32_0_BASE_IDX … #define mmDIG0_HDMI_ACR_32_1 … #define mmDIG0_HDMI_ACR_32_1_BASE_IDX … #define mmDIG0_HDMI_ACR_44_0 … #define mmDIG0_HDMI_ACR_44_0_BASE_IDX … #define mmDIG0_HDMI_ACR_44_1 … #define mmDIG0_HDMI_ACR_44_1_BASE_IDX … #define mmDIG0_HDMI_ACR_48_0 … #define mmDIG0_HDMI_ACR_48_0_BASE_IDX … #define mmDIG0_HDMI_ACR_48_1 … #define mmDIG0_HDMI_ACR_48_1_BASE_IDX … #define mmDIG0_HDMI_ACR_STATUS_0 … #define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG0_HDMI_ACR_STATUS_1 … #define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG0_AFMT_AUDIO_INFO0 … #define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG0_AFMT_AUDIO_INFO1 … #define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG0_AFMT_60958_0 … #define mmDIG0_AFMT_60958_0_BASE_IDX … #define mmDIG0_AFMT_60958_1 … #define mmDIG0_AFMT_60958_1_BASE_IDX … #define mmDIG0_AFMT_AUDIO_CRC_CONTROL … #define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL0 … #define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL1 … #define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL2 … #define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG0_AFMT_RAMP_CONTROL3 … #define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG0_AFMT_60958_2 … #define mmDIG0_AFMT_60958_2_BASE_IDX … #define mmDIG0_AFMT_AUDIO_CRC_RESULT … #define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG0_AFMT_STATUS … #define mmDIG0_AFMT_STATUS_BASE_IDX … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG0_AFMT_VBI_PACKET_CONTROL … #define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG0_AFMT_INFOFRAME_CONTROL0 … #define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG0_AFMT_AUDIO_SRC_CONTROL … #define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG0_DIG_BE_CNTL … #define mmDIG0_DIG_BE_CNTL_BASE_IDX … #define mmDIG0_DIG_BE_EN_CNTL … #define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG0_TMDS_CNTL … #define mmDIG0_TMDS_CNTL_BASE_IDX … #define mmDIG0_TMDS_CONTROL_CHAR … #define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG0_TMDS_CONTROL0_FEEDBACK … #define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG0_TMDS_CTL_BITS … #define mmDIG0_TMDS_CTL_BITS_BASE_IDX … #define mmDIG0_TMDS_DCBALANCER_CONTROL … #define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR … #define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX … #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … #define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG0_TMDS_CTL2_3_GEN_CNTL … #define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG0_DIG_VERSION … #define mmDIG0_DIG_VERSION_BASE_IDX … #define mmDIG0_DIG_LANE_ENABLE … #define mmDIG0_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG0_AFMT_CNTL … #define mmDIG0_AFMT_CNTL_BASE_IDX … #define mmDIG0_AFMT_VBI_PACKET_CONTROL1 … #define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 … #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX … // addressBlock: dce_dc_dio_dp0_dispdec // base address: 0x0 #define mmDP0_DP_LINK_CNTL … #define mmDP0_DP_LINK_CNTL_BASE_IDX … #define mmDP0_DP_PIXEL_FORMAT … #define mmDP0_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP0_DP_MSA_COLORIMETRY … #define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP0_DP_CONFIG … #define mmDP0_DP_CONFIG_BASE_IDX … #define mmDP0_DP_VID_STREAM_CNTL … #define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP0_DP_STEER_FIFO … #define mmDP0_DP_STEER_FIFO_BASE_IDX … #define mmDP0_DP_MSA_MISC … #define mmDP0_DP_MSA_MISC_BASE_IDX … #define mmDP0_DP_VID_TIMING … #define mmDP0_DP_VID_TIMING_BASE_IDX … #define mmDP0_DP_VID_N … #define mmDP0_DP_VID_N_BASE_IDX … #define mmDP0_DP_VID_M … #define mmDP0_DP_VID_M_BASE_IDX … #define mmDP0_DP_LINK_FRAMING_CNTL … #define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP0_DP_HBR2_EYE_PATTERN … #define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP0_DP_VID_MSA_VBID … #define mmDP0_DP_VID_MSA_VBID_BASE_IDX … #define mmDP0_DP_VID_INTERRUPT_CNTL … #define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CNTL … #define mmDP0_DP_DPHY_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP0_DP_DPHY_SYM0 … #define mmDP0_DP_DPHY_SYM0_BASE_IDX … #define mmDP0_DP_DPHY_SYM1 … #define mmDP0_DP_DPHY_SYM1_BASE_IDX … #define mmDP0_DP_DPHY_SYM2 … #define mmDP0_DP_DPHY_SYM2_BASE_IDX … #define mmDP0_DP_DPHY_8B10B_CNTL … #define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_PRBS_CNTL … #define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_SCRAM_CNTL … #define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CRC_EN … #define mmDP0_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP0_DP_DPHY_CRC_CNTL … #define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CRC_RESULT … #define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP0_DP_DPHY_CRC_MST_CNTL … #define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_CRC_MST_STATUS … #define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP0_DP_DPHY_FAST_TRAINING … #define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP0_DP_SEC_CNTL … #define mmDP0_DP_SEC_CNTL_BASE_IDX … #define mmDP0_DP_SEC_CNTL1 … #define mmDP0_DP_SEC_CNTL1_BASE_IDX … #define mmDP0_DP_SEC_FRAMING1 … #define mmDP0_DP_SEC_FRAMING1_BASE_IDX … #define mmDP0_DP_SEC_FRAMING2 … #define mmDP0_DP_SEC_FRAMING2_BASE_IDX … #define mmDP0_DP_SEC_FRAMING3 … #define mmDP0_DP_SEC_FRAMING3_BASE_IDX … #define mmDP0_DP_SEC_FRAMING4 … #define mmDP0_DP_SEC_FRAMING4_BASE_IDX … #define mmDP0_DP_SEC_AUD_N … #define mmDP0_DP_SEC_AUD_N_BASE_IDX … #define mmDP0_DP_SEC_AUD_N_READBACK … #define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP0_DP_SEC_AUD_M … #define mmDP0_DP_SEC_AUD_M_BASE_IDX … #define mmDP0_DP_SEC_AUD_M_READBACK … #define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP0_DP_SEC_TIMESTAMP … #define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP0_DP_SEC_PACKET_CNTL … #define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP0_DP_MSE_RATE_CNTL … #define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP0_DP_MSE_RATE_UPDATE … #define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP0_DP_MSE_SAT0 … #define mmDP0_DP_MSE_SAT0_BASE_IDX … #define mmDP0_DP_MSE_SAT1 … #define mmDP0_DP_MSE_SAT1_BASE_IDX … #define mmDP0_DP_MSE_SAT2 … #define mmDP0_DP_MSE_SAT2_BASE_IDX … #define mmDP0_DP_MSE_SAT_UPDATE … #define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP0_DP_MSE_LINK_TIMING … #define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP0_DP_MSE_MISC_CNTL … #define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP0_DP_MSE_SAT0_STATUS … #define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP0_DP_MSE_SAT1_STATUS … #define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP0_DP_MSE_SAT2_STATUS … #define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX … #define mmDP0_DP_MSA_TIMING_PARAM1 … #define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX … #define mmDP0_DP_MSA_TIMING_PARAM2 … #define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX … #define mmDP0_DP_MSA_TIMING_PARAM3 … #define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX … #define mmDP0_DP_MSA_TIMING_PARAM4 … #define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX … #define mmDP0_DP_DSC_CNTL … #define mmDP0_DP_DSC_CNTL_BASE_IDX … #define mmDP0_DP_SEC_CNTL2 … #define mmDP0_DP_SEC_CNTL2_BASE_IDX … #define mmDP0_DP_SEC_CNTL3 … #define mmDP0_DP_SEC_CNTL3_BASE_IDX … #define mmDP0_DP_SEC_CNTL4 … #define mmDP0_DP_SEC_CNTL4_BASE_IDX … #define mmDP0_DP_SEC_CNTL5 … #define mmDP0_DP_SEC_CNTL5_BASE_IDX … #define mmDP0_DP_SEC_CNTL6 … #define mmDP0_DP_SEC_CNTL6_BASE_IDX … #define mmDP0_DP_SEC_CNTL7 … #define mmDP0_DP_SEC_CNTL7_BASE_IDX … #define mmDP0_DP_DB_CNTL … #define mmDP0_DP_DB_CNTL_BASE_IDX … #define mmDP0_DP_MSA_VBID_MISC … #define mmDP0_DP_MSA_VBID_MISC_BASE_IDX … #define mmDP0_DP_SEC_METADATA_TRANSMISSION … #define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX … #define mmDP0_DP_DSC_BYTES_PER_PIXEL … #define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX … // addressBlock: dce_dc_dio_dig1_dispdec // base address: 0x400 #define mmDIG1_DIG_FE_CNTL … #define mmDIG1_DIG_FE_CNTL_BASE_IDX … #define mmDIG1_DIG_OUTPUT_CRC_CNTL … #define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX … #define mmDIG1_DIG_OUTPUT_CRC_RESULT … #define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX … #define mmDIG1_DIG_CLOCK_PATTERN … #define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX … #define mmDIG1_DIG_TEST_PATTERN … #define mmDIG1_DIG_TEST_PATTERN_BASE_IDX … #define mmDIG1_DIG_RANDOM_PATTERN_SEED … #define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX … #define mmDIG1_DIG_FIFO_STATUS … #define mmDIG1_DIG_FIFO_STATUS_BASE_IDX … #define mmDIG1_HDMI_METADATA_PACKET_CONTROL … #define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX … #define mmDIG1_HDMI_CONTROL … #define mmDIG1_HDMI_CONTROL_BASE_IDX … #define mmDIG1_HDMI_STATUS … #define mmDIG1_HDMI_STATUS_BASE_IDX … #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL … #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG1_HDMI_ACR_PACKET_CONTROL … #define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX … #define mmDIG1_HDMI_VBI_PACKET_CONTROL … #define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG1_HDMI_INFOFRAME_CONTROL0 … #define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG1_HDMI_INFOFRAME_CONTROL1 … #define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX … #define mmDIG1_AFMT_INTERRUPT_STATUS … #define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX … #define mmDIG1_HDMI_GC … #define mmDIG1_HDMI_GC_BASE_IDX … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX … #define mmDIG1_AFMT_ISRC1_0 … #define mmDIG1_AFMT_ISRC1_0_BASE_IDX … #define mmDIG1_AFMT_ISRC1_1 … #define mmDIG1_AFMT_ISRC1_1_BASE_IDX … #define mmDIG1_AFMT_ISRC1_2 … #define mmDIG1_AFMT_ISRC1_2_BASE_IDX … #define mmDIG1_AFMT_ISRC1_3 … #define mmDIG1_AFMT_ISRC1_3_BASE_IDX … #define mmDIG1_AFMT_ISRC1_4 … #define mmDIG1_AFMT_ISRC1_4_BASE_IDX … #define mmDIG1_AFMT_ISRC2_0 … #define mmDIG1_AFMT_ISRC2_0_BASE_IDX … #define mmDIG1_AFMT_ISRC2_1 … #define mmDIG1_AFMT_ISRC2_1_BASE_IDX … #define mmDIG1_AFMT_ISRC2_2 … #define mmDIG1_AFMT_ISRC2_2_BASE_IDX … #define mmDIG1_AFMT_ISRC2_3 … #define mmDIG1_AFMT_ISRC2_3_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX … #define mmDIG1_HDMI_DB_CONTROL … #define mmDIG1_HDMI_DB_CONTROL_BASE_IDX … #define mmDIG1_DME_CONTROL … #define mmDIG1_DME_CONTROL_BASE_IDX … #define mmDIG1_AFMT_MPEG_INFO0 … #define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX … #define mmDIG1_AFMT_MPEG_INFO1 … #define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX … #define mmDIG1_AFMT_GENERIC_HDR … #define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX … #define mmDIG1_AFMT_GENERIC_0 … #define mmDIG1_AFMT_GENERIC_0_BASE_IDX … #define mmDIG1_AFMT_GENERIC_1 … #define mmDIG1_AFMT_GENERIC_1_BASE_IDX … #define mmDIG1_AFMT_GENERIC_2 … #define mmDIG1_AFMT_GENERIC_2_BASE_IDX … #define mmDIG1_AFMT_GENERIC_3 … #define mmDIG1_AFMT_GENERIC_3_BASE_IDX … #define mmDIG1_AFMT_GENERIC_4 … #define mmDIG1_AFMT_GENERIC_4_BASE_IDX … #define mmDIG1_AFMT_GENERIC_5 … #define mmDIG1_AFMT_GENERIC_5_BASE_IDX … #define mmDIG1_AFMT_GENERIC_6 … #define mmDIG1_AFMT_GENERIC_6_BASE_IDX … #define mmDIG1_AFMT_GENERIC_7 … #define mmDIG1_AFMT_GENERIC_7_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX … #define mmDIG1_HDMI_ACR_32_0 … #define mmDIG1_HDMI_ACR_32_0_BASE_IDX … #define mmDIG1_HDMI_ACR_32_1 … #define mmDIG1_HDMI_ACR_32_1_BASE_IDX … #define mmDIG1_HDMI_ACR_44_0 … #define mmDIG1_HDMI_ACR_44_0_BASE_IDX … #define mmDIG1_HDMI_ACR_44_1 … #define mmDIG1_HDMI_ACR_44_1_BASE_IDX … #define mmDIG1_HDMI_ACR_48_0 … #define mmDIG1_HDMI_ACR_48_0_BASE_IDX … #define mmDIG1_HDMI_ACR_48_1 … #define mmDIG1_HDMI_ACR_48_1_BASE_IDX … #define mmDIG1_HDMI_ACR_STATUS_0 … #define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX … #define mmDIG1_HDMI_ACR_STATUS_1 … #define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX … #define mmDIG1_AFMT_AUDIO_INFO0 … #define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX … #define mmDIG1_AFMT_AUDIO_INFO1 … #define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX … #define mmDIG1_AFMT_60958_0 … #define mmDIG1_AFMT_60958_0_BASE_IDX … #define mmDIG1_AFMT_60958_1 … #define mmDIG1_AFMT_60958_1_BASE_IDX … #define mmDIG1_AFMT_AUDIO_CRC_CONTROL … #define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL0 … #define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL1 … #define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL2 … #define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX … #define mmDIG1_AFMT_RAMP_CONTROL3 … #define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX … #define mmDIG1_AFMT_60958_2 … #define mmDIG1_AFMT_60958_2_BASE_IDX … #define mmDIG1_AFMT_AUDIO_CRC_RESULT … #define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX … #define mmDIG1_AFMT_STATUS … #define mmDIG1_AFMT_STATUS_BASE_IDX … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL … #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX … #define mmDIG1_AFMT_VBI_PACKET_CONTROL … #define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX … #define mmDIG1_AFMT_INFOFRAME_CONTROL0 … #define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX … #define mmDIG1_AFMT_AUDIO_SRC_CONTROL … #define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX … #define mmDIG1_DIG_BE_CNTL … #define mmDIG1_DIG_BE_CNTL_BASE_IDX … #define mmDIG1_DIG_BE_EN_CNTL … #define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX … #define mmDIG1_TMDS_CNTL … #define mmDIG1_TMDS_CNTL_BASE_IDX … #define mmDIG1_TMDS_CONTROL_CHAR … #define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX … #define mmDIG1_TMDS_CONTROL0_FEEDBACK … #define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX … #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL … #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 … #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX … #define mmDIG1_TMDS_CTL_BITS … #define mmDIG1_TMDS_CTL_BITS_BASE_IDX … #define mmDIG1_TMDS_DCBALANCER_CONTROL … #define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX … #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR … #define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX … #define mmDIG1_TMDS_CTL0_1_GEN_CNTL … #define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX … #define mmDIG1_TMDS_CTL2_3_GEN_CNTL … #define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … #define mmDIG1_DIG_VERSION … #define mmDIG1_DIG_VERSION_BASE_IDX … #define mmDIG1_DIG_LANE_ENABLE … #define mmDIG1_DIG_LANE_ENABLE_BASE_IDX … #define mmDIG1_AFMT_CNTL … #define mmDIG1_AFMT_CNTL_BASE_IDX … #define mmDIG1_AFMT_VBI_PACKET_CONTROL1 … #define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 … #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX … // addressBlock: dce_dc_dio_dp1_dispdec // base address: 0x400 #define mmDP1_DP_LINK_CNTL … #define mmDP1_DP_LINK_CNTL_BASE_IDX … #define mmDP1_DP_PIXEL_FORMAT … #define mmDP1_DP_PIXEL_FORMAT_BASE_IDX … #define mmDP1_DP_MSA_COLORIMETRY … #define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX … #define mmDP1_DP_CONFIG … #define mmDP1_DP_CONFIG_BASE_IDX … #define mmDP1_DP_VID_STREAM_CNTL … #define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX … #define mmDP1_DP_STEER_FIFO … #define mmDP1_DP_STEER_FIFO_BASE_IDX … #define mmDP1_DP_MSA_MISC … #define mmDP1_DP_MSA_MISC_BASE_IDX … #define mmDP1_DP_VID_TIMING … #define mmDP1_DP_VID_TIMING_BASE_IDX … #define mmDP1_DP_VID_N … #define mmDP1_DP_VID_N_BASE_IDX … #define mmDP1_DP_VID_M … #define mmDP1_DP_VID_M_BASE_IDX … #define mmDP1_DP_LINK_FRAMING_CNTL … #define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX … #define mmDP1_DP_HBR2_EYE_PATTERN … #define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX … #define mmDP1_DP_VID_MSA_VBID … #define mmDP1_DP_VID_MSA_VBID_BASE_IDX … #define mmDP1_DP_VID_INTERRUPT_CNTL … #define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CNTL … #define mmDP1_DP_DPHY_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL … #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX … #define mmDP1_DP_DPHY_SYM0 … #define mmDP1_DP_DPHY_SYM0_BASE_IDX … #define mmDP1_DP_DPHY_SYM1 … #define mmDP1_DP_DPHY_SYM1_BASE_IDX … #define mmDP1_DP_DPHY_SYM2 … #define mmDP1_DP_DPHY_SYM2_BASE_IDX … #define mmDP1_DP_DPHY_8B10B_CNTL … #define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_PRBS_CNTL … #define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_SCRAM_CNTL … #define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CRC_EN … #define mmDP1_DP_DPHY_CRC_EN_BASE_IDX … #define mmDP1_DP_DPHY_CRC_CNTL … #define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CRC_RESULT … #define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX … #define mmDP1_DP_DPHY_CRC_MST_CNTL … #define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_CRC_MST_STATUS … #define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX … #define mmDP1_DP_DPHY_FAST_TRAINING … #define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX … #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS … #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX … #define mmDP1_DP_SEC_CNTL … #define mmDP1_DP_SEC_CNTL_BASE_IDX … #define mmDP1_DP_SEC_CNTL1 … #define mmDP1_DP_SEC_CNTL1_BASE_IDX … #define mmDP1_DP_SEC_FRAMING1 … #define mmDP1_DP_SEC_FRAMING1_BASE_IDX … #define mmDP1_DP_SEC_FRAMING2 … #define mmDP1_DP_SEC_FRAMING2_BASE_IDX … #define mmDP1_DP_SEC_FRAMING3 … #define mmDP1_DP_SEC_FRAMING3_BASE_IDX … #define mmDP1_DP_SEC_FRAMING4 … #define mmDP1_DP_SEC_FRAMING4_BASE_IDX … #define mmDP1_DP_SEC_AUD_N … #define mmDP1_DP_SEC_AUD_N_BASE_IDX … #define mmDP1_DP_SEC_AUD_N_READBACK … #define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX … #define mmDP1_DP_SEC_AUD_M … #define mmDP1_DP_SEC_AUD_M_BASE_IDX … #define mmDP1_DP_SEC_AUD_M_READBACK … #define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX … #define mmDP1_DP_SEC_TIMESTAMP … #define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX … #define mmDP1_DP_SEC_PACKET_CNTL … #define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX … #define mmDP1_DP_MSE_RATE_CNTL … #define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX … #define mmDP1_DP_MSE_RATE_UPDATE … #define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX … #define mmDP1_DP_MSE_SAT0 … #define mmDP1_DP_MSE_SAT0_BASE_IDX … #define mmDP1_DP_MSE_SAT1 … #define mmDP1_DP_MSE_SAT1_BASE_IDX … #define mmDP1_DP_MSE_SAT2 … #define mmDP1_DP_MSE_SAT2_BASE_IDX … #define mmDP1_DP_MSE_SAT_UPDATE … #define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX … #define mmDP1_DP_MSE_LINK_TIMING … #define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX … #define mmDP1_DP_MSE_MISC_CNTL … #define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL … #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX … #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL … #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX … #define mmDP1_DP_MSE_SAT0_STATUS … #define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX … #define mmDP1_DP_MSE_SAT1_STATUS … #define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX … #define mmDP1_DP_MSE_SAT2_STATUS … #define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX … #define mmDP1_DP_MSA_TIMING_PARAM1 … #define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX … #define mmDP1_DP_MSA_TIMING_PARAM2 … #define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX … #define mmDP1_DP_MSA_TIMING_PARAM3 … #define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX … #define mmDP1_DP_MSA_TIMING_PARAM4 … #define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX … #define mmDP1_DP_DSC_CNTL … #define mmDP1_DP_DSC_CNTL_BASE_IDX … #define mmDP1_DP_SEC_CNTL2 … #define mmDP1_DP_SEC_CNTL2_BASE_IDX … #define mmDP1_DP_SEC_CNTL3 … #define mmDP1_DP_SEC_CNTL3_BASE_IDX … #define mmDP1_DP_SEC_CNTL4 … #define mmDP1_DP_SEC_CNTL4_BASE_IDX … #define mmDP1_DP_SEC_CNTL5 … #define mmDP1_DP_SEC_CNTL5_BASE_IDX … #define mmDP1_DP_SEC_CNTL6 … #define mmDP1_DP_SEC_CNTL6_BASE_IDX … #define mmDP1_DP_SEC_CNTL7 … #define mmDP1_DP_SEC_CNTL7_BASE_IDX … #define mmDP1_DP_DB_CNTL … #define mmDP1_DP_DB_CNTL_BASE_IDX … #define mmDP1_DP_MSA_VBID_MISC … #define mmDP1_DP_MSA_VBID_MISC_BASE_IDX … #define mmDP1_DP_SEC_METADATA_TRANSMISSION … #define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX … #define mmDP1_DP_DSC_BYTES_PER_PIXEL … #define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX … // addressBlock: dce_dc_dcio_dcio_dispdec // base address: 0x0 #define mmDC_GENERICA … #define mmDC_GENERICA_BASE_IDX … #define mmUNIPHYA_LINK_CNTL … #define mmUNIPHYA_LINK_CNTL_BASE_IDX … #define mmUNIPHYA_CHANNEL_XBAR_CNTL … #define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmUNIPHYB_LINK_CNTL … #define mmUNIPHYB_LINK_CNTL_BASE_IDX … #define mmUNIPHYB_CHANNEL_XBAR_CNTL … #define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX … #define mmDCIO_WRCMD_DELAY … #define mmDCIO_WRCMD_DELAY_BASE_IDX … #define mmDC_PINSTRAPS … #define mmDC_PINSTRAPS_BASE_IDX … #define mmDCIO_CLOCK_CNTL … #define mmDCIO_CLOCK_CNTL_BASE_IDX … #define mmDCIO_SOFT_RESET … #define mmDCIO_SOFT_RESET_BASE_IDX … // addressBlock: dce_dc_dcio_dcio_chip_dispdec // base address: 0x0 #define mmDC_GPIO_DDC1_MASK … #define mmDC_GPIO_DDC1_MASK_BASE_IDX … #define mmDC_GPIO_DDC1_A … #define mmDC_GPIO_DDC1_A_BASE_IDX … #define mmDC_GPIO_DDC1_EN … #define mmDC_GPIO_DDC1_EN_BASE_IDX … #define mmDC_GPIO_DDC1_Y … #define mmDC_GPIO_DDC1_Y_BASE_IDX … #define mmDC_GPIO_DDC2_MASK … #define mmDC_GPIO_DDC2_MASK_BASE_IDX … #define mmDC_GPIO_DDC2_A … #define mmDC_GPIO_DDC2_A_BASE_IDX … #define mmDC_GPIO_DDC2_EN … #define mmDC_GPIO_DDC2_EN_BASE_IDX … #define mmDC_GPIO_DDC2_Y … #define mmDC_GPIO_DDC2_Y_BASE_IDX … #define mmDC_GPIO_HPD_MASK … #define mmDC_GPIO_HPD_MASK_BASE_IDX … #define mmDC_GPIO_HPD_A … #define mmDC_GPIO_HPD_A_BASE_IDX … #define mmDC_GPIO_HPD_EN … #define mmDC_GPIO_HPD_EN_BASE_IDX … #define mmDC_GPIO_HPD_Y … #define mmDC_GPIO_HPD_Y_BASE_IDX … #define mmDC_GPIO_PAD_STRENGTH_1 … #define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX … #define mmPHY_AUX_CNTL … #define mmPHY_AUX_CNTL_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_1 … #define mmDC_GPIO_AUX_CTRL_1_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_2 … #define mmDC_GPIO_AUX_CTRL_2_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_3 … #define mmDC_GPIO_AUX_CTRL_3_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_4 … #define mmDC_GPIO_AUX_CTRL_4_BASE_IDX … #define mmDC_GPIO_AUX_CTRL_5 … #define mmDC_GPIO_AUX_CTRL_5_BASE_IDX … #define mmAUXI2C_PAD_ALL_PWR_OK … #define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX … // addressBlock: azf0endpoint0_endpointind // base address: 0x0 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0endpoint1_endpointind // base address: 0x0 #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 … #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION … #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS … #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS … // addressBlock: azf0inputendpoint0_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … // addressBlock: azf0inputendpoint1_inputendpointind // base address: 0x0 #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL … #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME … #endif
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