/* * Copyright 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "dcn30_clk_mgr_smu_msg.h" #include "clk_mgr_internal.h" #include "reg_helper.h" #include "dm_helpers.h" #include "dalsmc.h" #include "dcn30_smu11_driver_if.h" #define mmDAL_MSG_REG … #define mmDAL_ARG_REG … #define mmDAL_RESP_REG … #define REG(reg_name) … #include "logger_types.h" #undef DC_LOGGER #define DC_LOGGER … #define smu_print(str, ...) … /* * Function to be used instead of REG_WAIT macro because the wait ends when * the register is NOT EQUAL to zero, and because the translation in msg_if.h * won't work with REG_WAIT. */ static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries) { … } static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out) { … } /* Test message should return input + 1 */ bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input) { … } bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version) { … } /* Message output should match SMU11_DRIVER_IF_VERSION in smu11_driver_if.h */ bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr) { … } /* Message output should match DALSMC_VERSION in dalsmc.h */ bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr) { … } void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) { … } void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) { … } void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) { … } void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) { … } /* Returns the actual frequency that was set in MHz, 0 on failure */ unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz) { … } /* Returns the actual frequency that was set in MHz, 0 on failure */ unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz) { … } /* * Frequency in MHz returned in lower 16 bits for valid DPM level * * Call with dpm_level = 0xFF to query features, return value will be: * Bits 7:0 - number of DPM levels * Bit 28 - 1 = auto DPM on * Bit 29 - 1 = sweep DPM on * Bit 30 - 1 = forced DPM on * Bit 31 - 0 = discrete, 1 = fine-grained * * With fine-grained DPM, only min and max frequencies will be reported * * Returns 0 on failure */ unsigned int dcn30_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level) { … } /* Returns the max DPM frequency in DC mode in MHz, 0 on failure */ unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk) { … } void dcn30_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz) { … } void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays) { … } void dcn30_smu_set_display_refresh_from_mall(struct clk_mgr_internal *clk_mgr, bool enable, uint8_t cache_timer_delay, uint8_t cache_timer_scale) { … } void dcn30_smu_set_external_client_df_cstate_allow(struct clk_mgr_internal *clk_mgr, bool enable) { … } void dcn30_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr) { … }
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