#include "core_types.h"
#include "clk_mgr_internal.h"
#include "reg_helper.h"
#include "dm_helpers.h"
#include "dcn314_smu.h"
#include "mp/mp_13_0_5_offset.h"
#define MP1_BASE__INST0_SEG0 …
#define MP1_BASE__INST0_SEG1 …
#define MP1_BASE__INST0_SEG2 …
#define MP1_BASE__INST0_SEG3 …
#define MP1_BASE__INST0_SEG4 …
#define MP1_BASE__INST0_SEG5 …
#ifdef BASE_INNER
#undef BASE_INNER
#endif
#define BASE_INNER(seg) …
#define BASE(seg) …
#define REG(reg_name) …
#define FN(reg_name, field) …
#include "logger_types.h"
#undef DC_LOGGER
#define DC_LOGGER …
#define smu_print(str, ...) …
#define VBIOSSMC_MSG_TestMessage …
#define VBIOSSMC_MSG_GetSmuVersion …
#define VBIOSSMC_MSG_PowerUpGfx …
#define VBIOSSMC_MSG_SetDispclkFreq …
#define VBIOSSMC_MSG_SetDprefclkFreq …
#define VBIOSSMC_MSG_SetDppclkFreq …
#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq …
#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk …
#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq …
#define VBIOSSMC_MSG_GetFclkFrequency …
#define VBIOSSMC_MSG_SetDisplayCount …
#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown …
#define VBIOSSMC_MSG_UpdatePmeRestore …
#define VBIOSSMC_MSG_SetVbiosDramAddrHigh …
#define VBIOSSMC_MSG_SetVbiosDramAddrLow …
#define VBIOSSMC_MSG_TransferTableSmu2Dram …
#define VBIOSSMC_MSG_TransferTableDram2Smu …
#define VBIOSSMC_MSG_SetDisplayIdleOptimizations …
#define VBIOSSMC_MSG_GetDprefclkFreq …
#define VBIOSSMC_MSG_GetDtbclkFreq …
#define VBIOSSMC_MSG_AllowZstatesEntry …
#define VBIOSSMC_MSG_DisallowZstatesEntry …
#define VBIOSSMC_MSG_SetDtbClk …
#define VBIOSSMC_Message_Count …
#define VBIOSSMC_Status_BUSY …
#define VBIOSSMC_Result_OK …
#define VBIOSSMC_Result_Failed …
#define VBIOSSMC_Result_UnknownCmd …
#define VBIOSSMC_Result_CmdRejectedPrereq …
#define VBIOSSMC_Result_CmdRejectedBusy …
static uint32_t dcn314_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
{ … }
static int dcn314_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
unsigned int msg_id,
unsigned int param)
{ … }
int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
{ … }
int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
{ … }
int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
{ … }
int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
{ … }
int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
{ … }
int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
{ … }
void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
{ … }
void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
{ … }
void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
{ … }
void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
{ … }
void dcn314_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
{ … }
void dcn314_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
{ … }
void dcn314_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
{ … }
void dcn314_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)
{ … }
void dcn314_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
{ … }