/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef DAL_DC_35_SMU_H_ #define DAL_DC_35_SMU_H_ #include "os_types.h" #ifndef PMFW_DRIVER_IF_H #define PMFW_DRIVER_IF_H #define PMFW_DRIVER_IF_VERSION … DSPCLK_e; DisplayClockTable_t; WatermarkRowGeneric_t; #define NUM_WM_RANGES … #define WM_PSTATE_CHG … #define WM_RETRAINING … WM_CLOCK_e; Watermarks_t; #define NUM_DCFCLK_DPM_LEVELS … #define NUM_DISPCLK_DPM_LEVELS … #define NUM_DPPCLK_DPM_LEVELS … #define NUM_SOCCLK_DPM_LEVELS … #define NUM_VCN_DPM_LEVELS … #define NUM_SOC_VOLTAGE_LEVELS … #define NUM_VPE_DPM_LEVELS … #define NUM_FCLK_DPM_LEVELS … #define NUM_MEM_PSTATE_LEVELS … WCK_RATIO_e; MemPstateTable_t; //Freq in MHz //Voltage in milli volts with 2 fractional bits DpmClocks_t_dcn35; // Throttler Status Bitmask #define TABLE_BIOS_IF … #define TABLE_WATERMARKS … #define TABLE_CUSTOM_DPM … #define TABLE_SPARE1 … #define TABLE_DPMCLOCKS … #define TABLE_MOMENTARY_PM … #define TABLE_MODERN_STDBY … #define TABLE_SMU_METRICS … #define TABLE_COUNT … #endif struct dcn35_watermarks { … }; struct dcn35_smu_dpm_clks { … }; /* TODO: taken from vgh, may not be correct */ struct display_idle_optimization { … }; display_idle_optimization_u; int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr); int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz); int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info); void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support); void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable); void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr); int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr); int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr); int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr); void dcn35_smu_notify_host_router_bw(struct clk_mgr_internal *clk_mgr, uint32_t hr_id, uint32_t bw_kbps); #endif /* DAL_DC_35_SMU_H_ */
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