/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "core_types.h" #include "clk_mgr_internal.h" #include "reg_helper.h" #include "dm_helpers.h" #include "dcn35_smu.h" #include "mp/mp_14_0_0_offset.h" #include "mp/mp_14_0_0_sh_mask.h" /* TODO: Use the real headers when they're correct */ #define MP1_BASE__INST0_SEG0 … #define MP1_BASE__INST0_SEG1 … #define MP1_BASE__INST0_SEG2 … #define MP1_BASE__INST0_SEG3 … #define MP1_BASE__INST0_SEG4 … #define MP1_BASE__INST0_SEG5 … #ifdef BASE_INNER #undef BASE_INNER #endif #define BASE_INNER(seg) … #define BASE(seg) … #define REG(reg_name) … #define FN(reg_name, field) … #include "logger_types.h" #undef DC_LOGGER #define DC_LOGGER … #define smu_print(str, ...) … #define VBIOSSMC_MSG_TestMessage … #define VBIOSSMC_MSG_GetSmuVersion … #define VBIOSSMC_MSG_PowerUpGfx … #define VBIOSSMC_MSG_SetDispclkFreq … #define VBIOSSMC_MSG_SetDprefclkFreq … #define VBIOSSMC_MSG_SetDppclkFreq … #define VBIOSSMC_MSG_SetHardMinDcfclkByFreq … #define VBIOSSMC_MSG_SetMinDeepSleepDcfclk … #define VBIOSSMC_MSG_SetPhyclkVoltageByFreq … #define VBIOSSMC_MSG_GetFclkFrequency … #define VBIOSSMC_MSG_SetDisplayCount … #define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown … #define VBIOSSMC_MSG_UpdatePmeRestore … #define VBIOSSMC_MSG_SetVbiosDramAddrHigh … #define VBIOSSMC_MSG_SetVbiosDramAddrLow … #define VBIOSSMC_MSG_TransferTableSmu2Dram … #define VBIOSSMC_MSG_TransferTableDram2Smu … #define VBIOSSMC_MSG_SetDisplayIdleOptimizations … #define VBIOSSMC_MSG_GetDprefclkFreq … #define VBIOSSMC_MSG_GetDtbclkFreq … #define VBIOSSMC_MSG_AllowZstatesEntry … #define VBIOSSMC_MSG_DisallowZstatesEntry … #define VBIOSSMC_MSG_SetDtbClk … #define VBIOSSMC_MSG_DispPsrEntry … #define VBIOSSMC_MSG_DispPsrExit … #define VBIOSSMC_MSG_DisableLSdma … #define VBIOSSMC_MSG_DpControllerPhyStatus … #define VBIOSSMC_MSG_QueryIPS2Support … #define VBIOSSMC_MSG_NotifyHostRouterBW … #define VBIOSSMC_Message_Count … #define VBIOSSMC_Status_BUSY … #define VBIOSSMC_Result_OK … #define VBIOSSMC_Result_Failed … #define VBIOSSMC_Result_UnknownCmd … #define VBIOSSMC_Result_CmdRejectedPrereq … #define VBIOSSMC_Result_CmdRejectedBusy … dcn35_dpia_host_router_bw; /* * Function to be used instead of REG_WAIT macro because the wait ends when * the register is NOT EQUAL to zero, and because `the translation in msg_if.h * won't work with REG_WAIT. */ static uint32_t dcn35_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries) { … } static int dcn35_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param) { … } int dcn35_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) { … } int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) { … } int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) { … } int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) { … } int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) { … } int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) { … } void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) { … } void dcn35_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) { … } void dcn35_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) { … } void dcn35_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) { … } void dcn35_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) { … } void dcn35_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) { … } void dcn35_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) { … } void dcn35_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support) { … } int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr) { … } int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr) { … } /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */ void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) { … } void dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) { … } int dcn35_smu_exit_low_power_state(struct clk_mgr_internal *clk_mgr) { … } int dcn35_smu_get_ips_supported(struct clk_mgr_internal *clk_mgr) { … } void dcn35_smu_notify_host_router_bw(struct clk_mgr_internal *clk_mgr, uint32_t hr_id, uint32_t bw_kbps) { … }
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