/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "dcn35_clk_mgr.h" #include "dccg.h" #include "clk_mgr_internal.h" // For dce12_get_dp_ref_freq_khz #include "dce100/dce_clk_mgr.h" // For dcn20_update_clocks_update_dpp_dto #include "dcn20/dcn20_clk_mgr.h" #include "reg_helper.h" #include "core_types.h" #include "dcn35_smu.h" #include "dm_helpers.h" /* TODO: remove this include once we ported over remaining clk mgr functions*/ #include "dcn30/dcn30_clk_mgr.h" #include "dcn31/dcn31_clk_mgr.h" #include "dc_dmub_srv.h" #include "link.h" #include "logger_types.h" #undef DC_LOGGER #define DC_LOGGER … #define regCLK1_CLK_PLL_REQ … #define regCLK1_CLK_PLL_REQ_BASE_IDX … #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT … #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT … #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT … #define CLK1_CLK_PLL_REQ__FbMult_int_MASK … #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK … #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK … #define regCLK1_CLK2_BYPASS_CNTL … #define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX … #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT … #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT … #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK … #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK … #define regCLK5_0_CLK5_spll_field_8 … #define regCLK5_0_CLK5_spll_field_8_BASE_IDX … #define CLK5_0_CLK5_spll_field_8__spll_ssc_en__SHIFT … #define CLK5_0_CLK5_spll_field_8__spll_ssc_en_MASK … #define SMU_VER_THRESHOLD … #define REG(reg_name) … #define TO_CLK_MGR_DCN35(clk_mgr) … static int dcn35_get_active_display_cnt_wa( struct dc *dc, struct dc_state *context, int *all_active_disps) { … } static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower, bool disable) { … } static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dtbclk_khz) { … } static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower) { … } static uint8_t get_lowest_dpia_index(const struct dc_link *link) { … } static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower) { … } void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower) { … } static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) { … } static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base) { … } bool dcn35_are_clock_states_equal(struct dc_clocks *a, struct dc_clocks *b) { … } static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr_dcn35 *clk_mgr) { … } static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base) { … } static void init_clk_states(struct clk_mgr *clk_mgr) { … } void dcn35_init_clocks(struct clk_mgr *clk_mgr) { … } static struct clk_bw_params dcn35_bw_params = …; static struct wm_table ddr5_wm_table = …; static struct wm_table lpddr5_wm_table = …; static DpmClocks_t_dcn35 dummy_clocks; static struct dcn35_watermarks dummy_wms = …; static struct dcn35_ss_info_table ss_info_table = …; static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr) { … } static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table) { … } static void dcn35_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { … } static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, struct dcn35_smu_dpm_clks *smu_dpm_clks) { … } static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { … } static inline bool is_valid_clock_value(uint32_t clock_value) { … } static unsigned int convert_wck_ratio(uint8_t wck_ratio) { … } static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry) { … } static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr, struct integrated_info *bios_info, DpmClocks_t_dcn35 *clock_table) { … } static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base) { … } static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base) { … } static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base) { … } static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr) { … } static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr, struct dc_state *context, bool safe_to_lower) { … } static struct clk_mgr_funcs dcn35_funcs = …; struct clk_mgr_funcs dcn35_fpga_funcs = …; void dcn35_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_dcn35 *clk_mgr, struct pp_smu_funcs *pp_smu, struct dccg *dccg) { … } void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) { … }
Codebase Browser
linux