/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "dccg.h" #include "clk_mgr_internal.h" #include "dcn32/dcn32_clk_mgr_smu_msg.h" #include "dcn20/dcn20_clk_mgr.h" #include "dce100/dce_clk_mgr.h" #include "dcn31/dcn31_clk_mgr.h" #include "dcn32/dcn32_clk_mgr.h" #include "reg_helper.h" #include "core_types.h" #include "dm_helpers.h" #include "link.h" #include "dc_state_priv.h" #include "atomfirmware.h" #include "dcn32_smu13_driver_if.h" #include "dcn/dcn_3_2_0_offset.h" #include "dcn/dcn_3_2_0_sh_mask.h" #include "dml/dcn32/dcn32_fpu.h" #define DCN_BASE__INST0_SEG1 … #define mmCLK1_CLK_PLL_REQ … #define mmCLK1_CLK0_DFS_CNTL … #define mmCLK1_CLK1_DFS_CNTL … #define mmCLK1_CLK2_DFS_CNTL … #define mmCLK1_CLK3_DFS_CNTL … #define mmCLK1_CLK4_DFS_CNTL … #define mmCLK1_CLK0_CURRENT_CNT … #define mmCLK1_CLK1_CURRENT_CNT … #define mmCLK1_CLK2_CURRENT_CNT … #define mmCLK1_CLK3_CURRENT_CNT … #define mmCLK1_CLK4_CURRENT_CNT … #define mmCLK4_CLK0_CURRENT_CNT … #define CLK1_CLK_PLL_REQ__FbMult_int_MASK … #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK … #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK … #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT … #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT … #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT … #define mmCLK01_CLK0_CLK_PLL_REQ … #define mmCLK01_CLK0_CLK0_DFS_CNTL … #define mmCLK01_CLK0_CLK1_DFS_CNTL … #define mmCLK01_CLK0_CLK2_DFS_CNTL … #define mmCLK01_CLK0_CLK3_DFS_CNTL … #define mmCLK01_CLK0_CLK4_DFS_CNTL … #define CLK0_CLK_PLL_REQ__FbMult_int_MASK … #define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK … #define CLK0_CLK_PLL_REQ__FbMult_frac_MASK … #define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT … #define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT … #define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT … #undef FN #define FN(reg_name, field_name) … #define REG(reg) … #define BASE_INNER(seg) … #define BASE(seg) … #define SR(reg_name) … #define CLK_SR_DCN32(reg_name) … static const struct clk_mgr_registers clk_mgr_regs_dcn32 = …; static const struct clk_mgr_shift clk_mgr_shift_dcn32 = …; static const struct clk_mgr_mask clk_mgr_mask_dcn32 = …; #define CLK_SR_DCN321(reg_name, block, inst) … static const struct clk_mgr_registers clk_mgr_regs_dcn321 = …; static const struct clk_mgr_shift clk_mgr_shift_dcn321 = …; static const struct clk_mgr_mask clk_mgr_mask_dcn321 = …; /* Query SMU for all clock states for a particular clock */ static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels) { … } static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr) { … } void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) { … } static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dtbclk_khz) { … } /* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming), * update DPPCLK to be the exact frequency that will be set after the DPPCLK * divider is updated. This will prevent rounding issues that could cause DPP * refclk and DPP DTO to not match up. */ static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) { … } void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower) { … } static void dcn32_update_clocks_update_dentist( struct clk_mgr_internal *clk_mgr, struct dc_state *context) { … } static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) { … } static bool dcn32_check_native_scaling(struct pipe_ctx *pipe) { … } static void dcn32_auto_dpm_test_log( struct dc_clocks *new_clocks, struct clk_mgr_internal *clk_mgr, struct dc_state *context) { … } static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower) { … } static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) { … } static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) { … } static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr) { … } static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { … } /* Set min memclk to minimum, either constrained by the current mode or DPM0 */ static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode) { … } /* Set max memclk to highest DPM value */ static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) { … } /* Get current memclk states, update bounding box */ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) { … } static bool dcn32_are_clock_states_equal(struct dc_clocks *a, struct dc_clocks *b) { … } static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base) { … } static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base) { … } static void dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) { … } static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) { … } static struct clk_mgr_funcs dcn32_funcs = …; void dcn32_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu, struct dccg *dccg) { … } void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr) { … }
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