/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "dccg.h" #include "clk_mgr_internal.h" // For dce12_get_dp_ref_freq_khz #include "dce100/dce_clk_mgr.h" // For dcn20_update_clocks_update_dpp_dto #include "dcn20/dcn20_clk_mgr.h" #include "dcn31/dcn31_clk_mgr.h" #include "dcn316_clk_mgr.h" #include "reg_helper.h" #include "core_types.h" #include "dcn316_smu.h" #include "dm_helpers.h" #include "dc_dmub_srv.h" #include "link.h" // DCN316 this is CLK1 instance #define MAX_INSTANCE … #define MAX_SEGMENT … struct IP_BASE_INSTANCE { … }; struct IP_BASE { … }; #define regCLK1_CLK_PLL_REQ … #define regCLK1_CLK_PLL_REQ_BASE_IDX … #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT … #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT … #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT … #define CLK1_CLK_PLL_REQ__FbMult_int_MASK … #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK … #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK … #define TO_CLK_MGR_DCN316(clk_mgr) … static int dcn316_get_active_display_cnt_wa( struct dc *dc, struct dc_state *context) { … } static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower, bool disable) { … } static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base) { … } static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower) { … } static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) { … } static struct clk_bw_params dcn316_bw_params = …; static struct wm_table ddr4_wm_table = …; static struct wm_table lpddr5_wm_table = …; static DpmClocks_316_t dummy_clocks; static struct dcn316_watermarks dummy_wms = …; static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table) { … } static void dcn316_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { … } static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, struct dcn316_smu_dpm_clks *smu_dpm_clks) { … } static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks) { … } static unsigned int find_clk_for_voltage( const DpmClocks_316_t *clock_table, const uint32_t clocks[], unsigned int voltage) { … } static void dcn316_clk_mgr_helper_populate_bw_params( struct clk_mgr_internal *clk_mgr, struct integrated_info *bios_info, const DpmClocks_316_t *clock_table) { … } static struct clk_mgr_funcs dcn316_funcs = …; extern struct clk_mgr_funcs dcn3_fpga_funcs; void dcn316_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_dcn316 *clk_mgr, struct pp_smu_funcs *pp_smu, struct dccg *dccg) { … } void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) { … }
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