linux/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */
#ifndef __DCE_MEM_INPUT_H__
#define __DCE_MEM_INPUT_H__

#include "dc_hw_types.h"
#include "mem_input.h"

#define TO_DCE_MEM_INPUT(mem_input) …

#define MI_DCE_BASE_REG_LIST(id) …

#define MI_DCE_PTE_REG_LIST(id) …

#if defined(CONFIG_DRM_AMD_DC_SI)
#define MI_DCE6_REG_LIST(id) …
#endif

#define MI_DCE8_REG_LIST(id) …

#define MI_DCE11_2_REG_LIST(id) …

#define MI_DCE11_REG_LIST(id) …

#define MI_DCE12_REG_LIST(id) …

struct dce_mem_input_registers { … };

/* Set_Filed_for_Block */
#define SFB(blk_name, reg_name, field_name, post_fix) …

#if defined(CONFIG_DRM_AMD_DC_SI)
#define MI_GFX6_TILE_MASK_SH_LIST(mask_sh, blk) …
#endif

#define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk) …

#define MI_DCP_MASK_SH_LIST(mask_sh, blk) …

#if defined(CONFIG_DRM_AMD_DC_SI)
#define MI_DCP_MASK_SH_LIST_DCE6(mask_sh, blk) …
#endif

#define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk) …

#define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk) …

#if defined(CONFIG_DRM_AMD_DC_SI)
#define MI_DMIF_PG_MASK_SH_LIST_DCE6(mask_sh, blk) …

#define MI_DMIF_PG_MASK_SH_DCE6(mask_sh, blk) …

#define MI_DCE6_MASK_SH_LIST(mask_sh) …
#endif

#define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk) …

#define MI_DMIF_PG_MASK_SH_DCE(mask_sh, blk) …

#define MI_DCE8_MASK_SH_LIST(mask_sh) …

#define MI_DCE11_2_MASK_SH_LIST(mask_sh) …

#define MI_DCE11_MASK_SH_LIST(mask_sh) …

#define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk) …

#define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk) …

#define MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh) …

#define MI_DCE12_MASK_SH_LIST(mask_sh) …

#define MI_REG_FIELD_LIST(type) … \

struct dce_mem_input_shift { … };

struct dce_mem_input_mask { … };

struct dce_mem_input_wa { … };

struct dce_mem_input { … };

void dce_mem_input_construct(
	struct dce_mem_input *dce_mi,
	struct dc_context *ctx,
	int inst,
	const struct dce_mem_input_registers *regs,
	const struct dce_mem_input_shift *mi_shift,
	const struct dce_mem_input_mask *mi_mask);

#if defined(CONFIG_DRM_AMD_DC_SI)
void dce60_mem_input_construct(
	struct dce_mem_input *dce_mi,
	struct dc_context *ctx,
	int inst,
	const struct dce_mem_input_registers *regs,
	const struct dce_mem_input_shift *mi_shift,
	const struct dce_mem_input_mask *mi_mask);
#endif

void dce112_mem_input_construct(
	struct dce_mem_input *dce_mi,
	struct dc_context *ctx,
	int inst,
	const struct dce_mem_input_registers *regs,
	const struct dce_mem_input_shift *mi_shift,
	const struct dce_mem_input_mask *mi_mask);

void dce120_mem_input_construct(
	struct dce_mem_input *dce_mi,
	struct dc_context *ctx,
	int inst,
	const struct dce_mem_input_registers *regs,
	const struct dce_mem_input_shift *mi_shift,
	const struct dce_mem_input_mask *mi_mask);

#endif /*__DCE_MEM_INPUT_H__*/