/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #ifndef __DCE_HWSEQ_H__ #define __DCE_HWSEQ_H__ #include "dc_types.h" #define HWSEQ_DCEF_REG_LIST_DCE8() … #define HWSEQ_DCEF_REG_LIST() … #define HWSEQ_BLND_REG_LIST() … #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) … #define HWSEQ_PIXEL_RATE_REG_LIST(blk) … #define HWSEQ_PIXEL_RATE_REG_LIST_201(blk) … #define HWSEQ_PHYPLL_REG_LIST(blk) … #define HWSEQ_PIXEL_RATE_REG_LIST_3(blk) … #define HWSEQ_PHYPLL_REG_LIST_3(blk) … #define HWSEQ_PIXEL_RATE_REG_LIST_302(blk) … #define HWSEQ_PHYPLL_REG_LIST_302(blk) … #define HWSEQ_PIXEL_RATE_REG_LIST_303(blk) … #define HWSEQ_PHYPLL_REG_LIST_303(blk) … #define HWSEQ_PHYPLL_REG_LIST_201(blk) … #define HWSEQ_DCE11_REG_LIST_BASE() … #if defined(CONFIG_DRM_AMD_DC_SI) #define HWSEQ_DCE6_REG_LIST() … #endif #define HWSEQ_DCE8_REG_LIST() … #define HWSEQ_DCE10_REG_LIST() … #define HWSEQ_ST_REG_LIST() … #define HWSEQ_CZ_REG_LIST() … #define HWSEQ_DCE120_REG_LIST() … #define HWSEQ_VG20_REG_LIST() … #define HWSEQ_DCE112_REG_LIST() … #define HWSEQ_DCN_REG_LIST() … #define MMHUB_DCN_REG_LIST() … #define HWSEQ_DCN1_REG_LIST() … #define HWSEQ_DCN2_REG_LIST() … #define HWSEQ_DCN21_REG_LIST() … #define HWSEQ_DCN201_REG_LIST() … #define HWSEQ_DCN30_REG_LIST() … #define HWSEQ_DCN301_REG_LIST() … #define HWSEQ_DCN302_REG_LIST() … #define HWSEQ_DCN303_REG_LIST() … struct dce_hwseq_registers { … }; /* set field name */ #define HWS_SF(blk_name, reg_name, field_name, post_fix) … #define HWS_SF1(blk_name, reg_name, field_name, post_fix) … #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk) … #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk) … #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk) … #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk) … #if defined(CONFIG_DRM_AMD_DC_SI) #define HWSEQ_DCE6_MASK_SH_LIST(mask_sh) … #endif #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh) … #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh) … #define HWSEQ_VG20_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCN_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCN201_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCN30_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCN301_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCN302_MASK_SH_LIST(mask_sh) … #define HWSEQ_DCN303_MASK_SH_LIST(mask_sh) … #define HWSEQ_REG_FIELD_LIST(type) … #define HWSEQ_DCN_REG_FIELD_LIST(type) … #define HWSEQ_DCN3_REG_FIELD_LIST(type) … #define HWSEQ_DCN301_REG_FIELD_LIST(type) … #define HWSEQ_DCN31_REG_FIELD_LIST(type) … #define HWSEQ_DCN35_REG_FIELD_LIST(type) … #define HWSEQ_DCN401_REG_FIELD_LIST(type) … struct dce_hwseq_shift { … }; struct dce_hwseq_mask { … }; enum blnd_mode { … }; struct dce_hwseq; struct pipe_ctx; struct clock_source; void dce_enable_fe_clock(struct dce_hwseq *hwss, unsigned int inst, bool enable); void dce_pipe_control_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock); void dce_set_blender_mode(struct dce_hwseq *hws, unsigned int blnd_inst, enum blnd_mode mode); #if defined(CONFIG_DRM_AMD_DC_SI) void dce60_pipe_control_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock); #endif void dce_clock_gating_power_up(struct dce_hwseq *hws, bool enable); void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, struct clock_source *clk_src, unsigned int tg_inst); bool dce_use_lut(enum surface_pixel_format format); #endif /*__DCE_HWSEQ_H__*/
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