dcn20_hwseq.c | Explore in Territory

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */
#include <linux/delay.h>

#include "dm_services.h"
#include "basics/dc_common.h"
#include "dm_helpers.h"
#include "core_types.h"
#include "resource.h"
#include "dcn20/dcn20_resource.h"
#include "dcn20_hwseq.h"
#include "dce/dce_hwseq.h"
#include "dcn20/dcn20_dsc.h"
#include "dcn20/dcn20_optc.h"
#include "abm.h"
#include "clk_mgr.h"
#include "dmcu.h"
#include "hubp.h"
#include "timing_generator.h"
#include "opp.h"
#include "ipp.h"
#include "mpc.h"
#include "mcif_wb.h"
#include "dchubbub.h"
#include "reg_helper.h"
#include "dcn10/dcn10_cm_common.h"
#include "vm_helper.h"
#include "dccg.h"
#include "dc_dmub_srv.h"
#include "dce/dmub_hw_lock_mgr.h"
#include "hw_sequencer.h"
#include "dpcd_defs.h"
#include "inc/link_enc_cfg.h"
#include "link_hwss.h"
#include "link.h"
#include "dc_state_priv.h"

#define DC_LOGGER …
#define DC_LOGGER_INIT(logger) …

#define CTX …
#define REG(reg) …

#undef FN
#define FN(reg_name, field_name) …

void dcn20_log_color_state(struct dc *dc,
			   struct dc_log_buffer_ctx *log_ctx)
{ … }


static int find_free_gsl_group(const struct dc *dc)
{ … }

/* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
 * This is only used to lock pipes in pipe splitting case with immediate flip
 * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
 * so we get tearing with freesync since we cannot flip multiple pipes
 * atomically.
 * We use GSL for this:
 * - immediate flip: find first available GSL group if not already assigned
 *                   program gsl with that group, set current OTG as master
 *                   and always us 0x4 = AND of flip_ready from all pipes
 * - vsync flip: disable GSL if used
 *
 * Groups in stream_res are stored as +1 from HW registers, i.e.
 * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
 * Using a magic value like -1 would require tracking all inits/resets
 */
void dcn20_setup_gsl_group_as_lock(
		const struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		bool enable)
{ … }

void dcn20_set_flip_control_gsl(
		struct pipe_ctx *pipe_ctx,
		bool flip_immediate)
{ … }

void dcn20_enable_power_gating_plane(
	struct dce_hwseq *hws,
	bool enable)
{ … }

void dcn20_dccg_init(struct dce_hwseq *hws)
{ … }

void dcn20_disable_vga(
	struct dce_hwseq *hws)
{ … }

void dcn20_program_triple_buffer(
	const struct dc *dc,
	struct pipe_ctx *pipe_ctx,
	bool enable_triple_buffer)
{ … }

/* Blank pixel data during initialization */
void dcn20_init_blank(
		struct dc *dc,
		struct timing_generator *tg)
{ … }

void dcn20_dsc_pg_control(
		struct dce_hwseq *hws,
		unsigned int dsc_inst,
		bool power_on)
{ … }

void dcn20_dpp_pg_control(
		struct dce_hwseq *hws,
		unsigned int dpp_inst,
		bool power_on)
{ … }


void dcn20_hubp_pg_control(
		struct dce_hwseq *hws,
		unsigned int hubp_inst,
		bool power_on)
{ … }


/* disable HW used by plane.
 * note:  cannot disable until disconnect is complete
 */
void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
{ … }


void dcn20_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)
{ … }

void dcn20_disable_pixel_data(struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank)
{ … }

static int calc_mpc_flow_ctrl_cnt(const struct dc_stream_state *stream,
		int opp_cnt, bool is_two_pixels_per_container)
{ … }

static enum phyd32clk_clock_source get_phyd32clk_src(struct dc_link *link)
{ … }

static int get_odm_segment_count(struct pipe_ctx *pipe_ctx)
{ … }

enum dc_status dcn20_enable_stream_timing(
		struct pipe_ctx *pipe_ctx,
		struct dc_state *context,
		struct dc *dc)
{ … }

void dcn20_program_output_csc(struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		enum dc_color_space colorspace,
		uint16_t *matrix,
		int opp_id)
{ … }

bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
				const struct dc_stream_state *stream)
{ … }

bool dcn20_set_blend_lut(
	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
{ … }

bool dcn20_set_shaper_3dlut(
	struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
{ … }

bool dcn20_set_input_transfer_func(struct dc *dc,
				struct pipe_ctx *pipe_ctx,
				const struct dc_plane_state *plane_state)
{ … }

void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
{ … }

void dcn20_blank_pixel_data(
		struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		bool blank)
{ … }


static void dcn20_power_on_plane_resources(
	struct dce_hwseq *hws,
	struct pipe_ctx *pipe_ctx)
{ … }

static void dcn20_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,
			       struct dc_state *context)
{ … }

void dcn20_pipe_control_lock(
	struct dc *dc,
	struct pipe_ctx *pipe,
	bool lock)
{ … }

static void dcn20_detect_pipe_changes(struct dc_state *old_state,
		struct dc_state *new_state,
		struct pipe_ctx *old_pipe,
		struct pipe_ctx *new_pipe)
{ … }

static void dcn20_update_dchubp_dpp(
	struct dc *dc,
	struct pipe_ctx *pipe_ctx,
	struct dc_state *context)
{ … }

static int calculate_vready_offset_for_group(struct pipe_ctx *pipe)
{ … }

static void dcn20_program_pipe(
		struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		struct dc_state *context)
{ … }

void dcn20_program_front_end_for_ctx(
		struct dc *dc,
		struct dc_state *context)
{ … }

/* post_unlock_reset_opp - the function wait for corresponding double
 * buffered pending status clear and reset opp head pipe's none double buffered
 * registers to their initial state.
 */
static void post_unlock_reset_opp(struct dc *dc,
		struct pipe_ctx *opp_head)
{ … }

void dcn20_post_unlock_program_front_end(
		struct dc *dc,
		struct dc_state *context)
{ … }

void dcn20_prepare_bandwidth(
		struct dc *dc,
		struct dc_state *context)
{ … }

void dcn20_optimize_bandwidth(
		struct dc *dc,
		struct dc_state *context)
{ … }

bool dcn20_update_bandwidth(
		struct dc *dc,
		struct dc_state *context)
{ … }

void dcn20_enable_writeback(
		struct dc *dc,
		struct dc_writeback_info *wb_info,
		struct dc_state *context)
{ … }

void dcn20_disable_writeback(
		struct dc *dc,
		unsigned int dwb_pipe_inst)
{ … }

bool dcn20_wait_for_blank_complete(
		struct output_pixel_processor *opp)
{ … }

bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
{ … }

void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
{ … }

void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
{ … }

void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
{ … }

void dcn20_init_vm_ctx(
		struct dce_hwseq *hws,
		struct dc *dc,
		struct dc_virtual_addr_space_config *va_config,
		int vmid)
{ … }

int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
{ … }

static bool patch_address_for_sbs_tb_stereo(
		struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
{ … }

void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
{ … }

void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
		struct dc_link_settings *link_settings)
{ … }

void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
{ … }

void dcn20_reset_back_end_for_pipe(
		struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		struct dc_state *context)
{ … }

void dcn20_reset_hw_ctx_wrap(
		struct dc *dc,
		struct dc_state *context)
{ … }

void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
{ … }

void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
{ … }

void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
{ … }

void dcn20_fpga_init_hw(struct dc *dc)
{ … }

void dcn20_set_disp_pattern_generator(const struct dc *dc,
		struct pipe_ctx *pipe_ctx,
		enum controller_dp_test_pattern test_pattern,
		enum controller_dp_color_space color_space,
		enum dc_color_depth color_depth,
		const struct tg_color *solid_color,
		int width, int height, int offset)
{ … }
linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
