/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include <linux/delay.h> #include "dm_services.h" #include "basics/dc_common.h" #include "core_types.h" #include "resource.h" #include "custom_float.h" #include "dcn10_hwseq.h" #include "dcn10/dcn10_hw_sequencer_debug.h" #include "dce/dce_hwseq.h" #include "abm.h" #include "dmcu.h" #include "dcn10/dcn10_optc.h" #include "dcn10/dcn10_dpp.h" #include "dcn10/dcn10_mpc.h" #include "timing_generator.h" #include "opp.h" #include "ipp.h" #include "mpc.h" #include "reg_helper.h" #include "dcn10/dcn10_hubp.h" #include "dcn10/dcn10_hubbub.h" #include "dcn10/dcn10_cm_common.h" #include "dccg.h" #include "clk_mgr.h" #include "link_hwss.h" #include "dpcd_defs.h" #include "dsc.h" #include "dce/dmub_psr.h" #include "dc_dmub_srv.h" #include "dce/dmub_hw_lock_mgr.h" #include "dc_trace.h" #include "dce/dmub_outbox.h" #include "link.h" #include "dc_state_priv.h" #define DC_LOGGER … #define DC_LOGGER_INIT(logger) … #define CTX … #define REG(reg) … #undef FN #define FN(reg_name, field_name) … /*print is 17 wide, first two characters are spaces*/ #define DTN_INFO_MICRO_SEC(ref_cycle) … #define GAMMA_HW_POINTS_NUM … #define PGFSM_POWER_ON … #define PGFSM_POWER_OFF … static void print_microsec(struct dc_context *dc_ctx, struct dc_log_buffer_ctx *log_ctx, uint32_t ref_cycle) { … } void dcn10_lock_all_pipes(struct dc *dc, struct dc_state *context, bool lock) { … } static void log_mpc_crc(struct dc *dc, struct dc_log_buffer_ctx *log_ctx) { … } static void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx) { … } static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx) { … } static void dcn10_log_color_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx) { … } void dcn10_log_hw_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx) { … } bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx) { … } void dcn10_enable_power_gating_plane( struct dce_hwseq *hws, bool enable) { … } void dcn10_disable_vga( struct dce_hwseq *hws) { … } /** * dcn10_dpp_pg_control - DPP power gate control. * * @hws: dce_hwseq reference. * @dpp_inst: DPP instance reference. * @power_on: true if we want to enable power gate, false otherwise. * * Enable or disable power gate in the specific DPP instance. */ void dcn10_dpp_pg_control( struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) { … } /** * dcn10_hubp_pg_control - HUBP power gate control. * * @hws: dce_hwseq reference. * @hubp_inst: DPP instance reference. * @power_on: true if we want to enable power gate, false otherwise. * * Enable or disable power gate in the specific HUBP instance. */ void dcn10_hubp_pg_control( struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) { … } static void power_on_plane_resources( struct dce_hwseq *hws, int plane_id) { … } static void undo_DEGVIDCN10_253_wa(struct dc *dc) { … } static void apply_DEGVIDCN10_253_wa(struct dc *dc) { … } void dcn10_bios_golden_init(struct dc *dc) { … } static void false_optc_underflow_wa( struct dc *dc, const struct dc_stream_state *stream, struct timing_generator *tg) { … } static int calculate_vready_offset_for_group(struct pipe_ctx *pipe) { … } enum dc_status dcn10_enable_stream_timing( struct pipe_ctx *pipe_ctx, struct dc_state *context, struct dc *dc) { … } static void dcn10_reset_back_end_for_pipe( struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context) { … } static bool dcn10_hw_wa_force_recovery(struct dc *dc) { … } void dcn10_verify_allow_pstate_change_high(struct dc *dc) { … } /* trigger HW to start disconnect plane from stream on the next vsync */ void dcn10_plane_atomic_disconnect(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx) { … } /** * dcn10_plane_atomic_power_down - Power down plane components. * * @dc: dc struct reference. used for grab hwseq. * @dpp: dpp struct reference. * @hubp: hubp struct reference. * * Keep in mind that this operation requires a power gate configuration; * however, requests for switch power gate are precisely controlled to avoid * problems. For this reason, power gate request is usually disabled. This * function first needs to enable the power gate request before disabling DPP * and HUBP. Finally, it disables the power gate request again. */ void dcn10_plane_atomic_power_down(struct dc *dc, struct dpp *dpp, struct hubp *hubp) { … } /* disable HW used by plane. * note: cannot disable until disconnect is complete */ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) { … } void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx) { … } void dcn10_init_pipes(struct dc *dc, struct dc_state *context) { … } void dcn10_init_hw(struct dc *dc) { … } /* In headless boot cases, DIG may be turned * on which causes HW/SW discrepancies. * To avoid this, power down hardware on boot * if DIG is turned on */ void dcn10_power_down_on_boot(struct dc *dc) { … } void dcn10_reset_hw_ctx_wrap( struct dc *dc, struct dc_state *context) { … } static bool patch_address_for_sbs_tb_stereo( struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) { … } void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) { … } bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) { … } #define MAX_NUM_HW_POINTS … static void log_tf(struct dc_context *ctx, const struct dc_transfer_func *tf, uint32_t hw_points_num) { … } bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream) { … } void dcn10_pipe_control_lock( struct dc *dc, struct pipe_ctx *pipe, bool lock) { … } /** * delay_cursor_until_vupdate() - Delay cursor update if too close to VUPDATE. * * Software keepout workaround to prevent cursor update locking from stalling * out cursor updates indefinitely or from old values from being retained in * the case where the viewport changes in the same frame as the cursor. * * The idea is to calculate the remaining time from VPOS to VUPDATE. If it's * too close to VUPDATE, then stall out until VUPDATE finishes. * * TODO: Optimize cursor programming to be once per frame before VUPDATE * to avoid the need for this workaround. * * @dc: Current DC state * @pipe_ctx: Pipe_ctx pointer for delayed cursor update * * Return: void */ static void delay_cursor_until_vupdate(struct dc *dc, struct pipe_ctx *pipe_ctx) { … } void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock) { … } static bool wait_for_reset_trigger_to_occur( struct dc_context *dc_ctx, struct timing_generator *tg) { … } static uint64_t reduceSizeAndFraction(uint64_t *numerator, uint64_t *denominator, bool checkUint32Bounary) { … } static bool is_low_refresh_rate(struct pipe_ctx *pipe) { … } static uint8_t get_clock_divider(struct pipe_ctx *pipe, bool account_low_refresh_rate) { … } static int dcn10_align_pixel_clocks(struct dc *dc, int group_size, struct pipe_ctx *grouped_pipes[]) { … } void dcn10_enable_vblanks_synchronization( struct dc *dc, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]) { … } void dcn10_enable_timing_synchronization( struct dc *dc, struct dc_state *state, int group_index, int group_size, struct pipe_ctx *grouped_pipes[]) { … } void dcn10_enable_per_frame_crtc_position_reset( struct dc *dc, int group_size, struct pipe_ctx *grouped_pipes[]) { … } static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1, struct vm_system_aperture_param *apt, struct dce_hwseq *hws) { … } /* Temporary read settings, future will get values from kmd directly */ static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, struct vm_context0_param *vm0, struct dce_hwseq *hws) { … } static void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp) { … } static void dcn10_enable_plane( struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context) { … } void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx) { … } static bool dcn10_is_rear_mpo_fix_required(struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace) { … } static void dcn10_set_csc_adjustment_rgb_mpo_fix(struct pipe_ctx *pipe_ctx, uint16_t *matrix) { … } void dcn10_program_output_csc(struct dc *dc, struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace, uint16_t *matrix, int opp_id) { … } static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) { … } void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id) { … } void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) { … } static void update_scaler(struct pipe_ctx *pipe_ctx) { … } static void dcn10_update_dchubp_dpp( struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context) { … } void dcn10_blank_pixel_data( struct dc *dc, struct pipe_ctx *pipe_ctx, bool blank) { … } void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx) { … } void dcn10_program_pipe( struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context) { … } void dcn10_wait_for_pending_cleared(struct dc *dc, struct dc_state *context) { … } void dcn10_post_unlock_program_front_end( struct dc *dc, struct dc_state *context) { … } static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context) { … } void dcn10_prepare_bandwidth( struct dc *dc, struct dc_state *context) { … } void dcn10_optimize_bandwidth( struct dc *dc, struct dc_state *context) { … } void dcn10_set_drr(struct pipe_ctx **pipe_ctx, int num_pipes, struct dc_crtc_timing_adjust adjust) { … } void dcn10_get_position(struct pipe_ctx **pipe_ctx, int num_pipes, struct crtc_position *position) { … } void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) { … } static void dcn10_config_stereo_parameters( struct dc_stream_state *stream, struct crtc_stereo_flags *flags) { … } void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) { … } static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) { … } void dcn10_wait_for_mpcc_disconnect( struct dc *dc, struct resource_pool *res_pool, struct pipe_ctx *pipe_ctx) { … } bool dcn10_dummy_display_power_gating( struct dc *dc, uint8_t controller_id, struct dc_bios *dcb, enum pipe_gating_control power_gating) { … } void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) { … } void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data) { … } static bool dcn10_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) { … } void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) { … } void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx) { … } void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx) { … } /* * apply_front_porch_workaround TODO FPGA still need? * * This is a workaround for a bug that has existed since R5xx and has not been * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. */ static void apply_front_porch_workaround( struct dc_crtc_timing *timing) { … } int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx) { … } void dcn10_calc_vupdate_position( struct dc *dc, struct pipe_ctx *pipe_ctx, uint32_t *start_line, uint32_t *end_line) { … } static void dcn10_cal_vline_position( struct dc *dc, struct pipe_ctx *pipe_ctx, uint32_t *start_line, uint32_t *end_line) { … } void dcn10_setup_periodic_interrupt( struct dc *dc, struct pipe_ctx *pipe_ctx) { … } void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx) { … } void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings) { … } void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx, const uint8_t *custom_sdp_message, unsigned int sdp_message_size) { … } enum dc_status dcn10_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping) { … } void dcn10_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg) { … } void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits) { … }
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