linux/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h

/* Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DC_MPCC_DCN20_H__
#define __DC_MPCC_DCN20_H__

#include "dcn10/dcn10_mpc.h"

#define TO_DCN20_MPC(mpc_base) …

#define MPC_REG_LIST_DCN2_0(inst) …

#define MPC_OUT_MUX_REG_LIST_DCN2_0(inst) …

#define MPC_DBG_REG_LIST_DCN2_0() …

#define MPC_REG_VARIABLE_LIST_DCN2_0 …

#define MPC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) …

/*
 *	DCN2 MPC_OCSC debug status register:
 *
 *		Status index including current OCSC Mode is 1
 *			OCSC Mode: [1..0]
 */
#define MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX …

#define MPC_DEBUG_REG_LIST_SH_DCN20 …

#define MPC_DEBUG_REG_LIST_MASK_DCN20 …

#define MPC_REG_FIELD_LIST_DCN2_0(type) …

struct dcn20_mpc_registers { … };

struct dcn20_mpc_shift { … };

struct dcn20_mpc_mask { … };

struct dcn20_mpc { … };

void dcn20_mpc_construct(struct dcn20_mpc *mpcc20,
	struct dc_context *ctx,
	const struct dcn20_mpc_registers *mpc_regs,
	const struct dcn20_mpc_shift *mpc_shift,
	const struct dcn20_mpc_mask *mpc_mask,
	int num_mpcc);

void mpc2_update_blending(
	struct mpc *mpc,
	struct mpcc_blnd_cfg *blnd_cfg,
	int mpcc_id);

void mpc2_set_denorm(
	struct mpc *mpc,
	int opp_id,
	enum dc_color_depth output_depth);

void mpc2_set_denorm_clamp(
	struct mpc *mpc,
	int opp_id,
	struct mpc_denorm_clamp denorm_clamp);

void mpc2_set_output_csc(
	struct mpc *mpc,
	int opp_id,
	const uint16_t *regval,
	enum mpc_output_csc_mode ocsc_mode);

void mpc2_set_ocsc_default(
	struct mpc *mpc,
	int opp_id,
	enum dc_color_space color_space,
	enum mpc_output_csc_mode ocsc_mode);

void mpc2_set_output_gamma(
	struct mpc *mpc,
	int mpcc_id,
	const struct pwl_params *params);

void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);
void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
#endif