dcn30_mpc.h | Explore in Territory

/* Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DC_MPCC_DCN30_H__
#define __DC_MPCC_DCN30_H__

#include "dcn20/dcn20_mpc.h"

#define MAX_RMU …

#define TO_DCN30_MPC(mpc_base) …

#ifdef SRII_MPC_RMU
#undef SRII_MPC_RMU

#define SRII_MPC_RMU …

#endif


#define MPC_REG_LIST_DCN3_0(inst) …

#define MPC_OUT_MUX_REG_LIST_DCN3_0(inst) …

#define MPC_RMU_GLOBAL_REG_LIST_DCN3AG …

#define MPC_RMU_REG_LIST_DCN3AG(inst) …


#define MPC_DWB_MUX_REG_LIST_DCN3_0(inst) …

#define MPC_REG_VARIABLE_LIST_DCN3_0 …

#define MPC_REG_VARIABLE_LIST_DCN32 …

#define MPC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh) …


#define MPC_COMMON_MASK_SH_LIST_DCN30(mask_sh) …


#define MPC_REG_FIELD_LIST_DCN3_0(type) …

#define MPC_REG_FIELD_LIST_DCN32(type) …


#define MPC_COMMON_MASK_SH_LIST_DCN303(mask_sh) …

#define MPC_REG_FIELD_LIST_DCN3_03(type) …

struct dcn30_mpc_registers { … };

struct dcn30_mpc_shift { … };

struct dcn30_mpc_mask { … };

struct dcn30_mpc { … };

void dcn30_mpc_construct(struct dcn30_mpc *mpc30,
	struct dc_context *ctx,
	const struct dcn30_mpc_registers *mpc_regs,
	const struct dcn30_mpc_shift *mpc_shift,
	const struct dcn30_mpc_mask *mpc_mask,
	int num_mpcc,
	int num_rmu);

void mpc3_mpc_init(
	struct mpc *mpc);

void mpc3_mpc_init_single_inst(
	struct mpc *mpc,
	unsigned int mpcc_id);

bool mpc3_program_shaper(
		struct mpc *mpc,
		const struct pwl_params *params,
		uint32_t rmu_idx);

bool mpc3_program_3dlut(
		struct mpc *mpc,
		const struct tetrahedral_params *params,
		int rmu_idx);

uint32_t mpcc3_acquire_rmu(struct mpc *mpc,
		int mpcc_id, int rmu_idx);

void mpc3_set_denorm(
	struct mpc *mpc,
	int opp_id,
	enum dc_color_depth output_depth);

void mpc3_set_denorm_clamp(
	struct mpc *mpc,
	int opp_id,
	struct mpc_denorm_clamp denorm_clamp);

void mpc3_set_output_csc(
	struct mpc *mpc,
	int opp_id,
	const uint16_t *regval,
	enum mpc_output_csc_mode ocsc_mode);

void mpc3_set_ocsc_default(
	struct mpc *mpc,
	int opp_id,
	enum dc_color_space color_space,
	enum mpc_output_csc_mode ocsc_mode);

void mpc3_set_output_gamma(
	struct mpc *mpc,
	int mpcc_id,
	const struct pwl_params *params);

uint32_t mpc3_get_rmu_mux_status(
	struct mpc *mpc,
	int rmu_idx);

void mpc3_set_gamut_remap(
	struct mpc *mpc,
	int mpcc_id,
	const struct mpc_grph_gamut_adjustment *adjust);

void mpc3_get_gamut_remap(struct mpc *mpc,
			  int mpcc_id,
			  struct mpc_grph_gamut_adjustment *adjust);

void mpc3_set_rmu_mux(
	struct mpc *mpc,
	int rmu_idx,
	int value);

void mpc3_set_dwb_mux(
	struct mpc *mpc,
	int dwb_id,
	int mpcc_id);

void mpc3_disable_dwb_mux(
	struct mpc *mpc,
	int dwb_id);

bool mpc3_is_dwb_idle(
	struct mpc *mpc,
	int dwb_id);

void mpc3_power_on_ogam_lut(
	struct mpc *mpc, int mpcc_id,
	bool power_on);

void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);

enum dc_lut_mode mpc3_get_ogam_current(
	struct mpc *mpc,
	int mpcc_id);

#endif
linux/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.h
