/* SPDX-License-Identifier: MIT */ /* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "dm_services.h" #include "dm_helpers.h" #include "core_types.h" #include "resource.h" #include "dccg.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" #include "reg_helper.h" #include "abm.h" #include "hubp.h" #include "dchubbub.h" #include "timing_generator.h" #include "opp.h" #include "ipp.h" #include "mpc.h" #include "mcif_wb.h" #include "dc_dmub_srv.h" #include "dcn35_hwseq.h" #include "dcn35/dcn35_dccg.h" #include "link_hwss.h" #include "dpcd_defs.h" #include "dce/dmub_outbox.h" #include "link.h" #include "dcn10/dcn10_hwseq.h" #include "inc/link_enc_cfg.h" #include "dcn30/dcn30_vpg.h" #include "dce/dce_i2c_hw.h" #include "dsc.h" #include "dcn20/dcn20_optc.h" #include "dcn30/dcn30_cm_common.h" #include "dcn31/dcn31_hwseq.h" #include "dcn20/dcn20_hwseq.h" #include "dc_state_priv.h" #define DC_LOGGER_INIT(logger) … #define CTX … #define REG(reg) … #define DC_LOGGER … #undef FN #define FN(reg_name, field_name) … #if 0 static void enable_memory_low_power(struct dc *dc) { struct dce_hwseq *hws = dc->hwseq; int i; if (dc->debug.enable_mem_low_power.bits.dmcu) { // Force ERAM to shutdown if DMCU is not enabled if (dc->debug.disable_dmcu || dc->config.disable_dmcu) { REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3); } } /*dcn35 has default MEM_PWR enabled, make sure wake them up*/ // Set default OPTC memory power states if (dc->debug.enable_mem_low_power.bits.optc) { // Shutdown when unassigned and light sleep in VBLANK REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); } if (dc->debug.enable_mem_low_power.bits.vga) { // Power down VGA memory REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); } if (dc->debug.enable_mem_low_power.bits.mpc && dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { // Power down VPGs for (i = 0; i < dc->res_pool->stream_enc_count; i++) dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); #if defined(CONFIG_DRM_AMD_DC_DP2_0) for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); #endif } } #endif void dcn35_set_dmu_fgcg(struct dce_hwseq *hws, bool enable) { … } void dcn35_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable) { … } void dcn35_init_hw(struct dc *dc) { … } static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) { … } // Given any pipe_ctx, return the total ODM combine factor, and optionally return // the OPPids which are used static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) { … } void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx) { … } void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on) { … } void dcn35_dpstream_root_clock_control(struct dce_hwseq *hws, unsigned int dp_hpo_inst, bool clock_on) { … } void dcn35_physymclk_root_clock_control(struct dce_hwseq *hws, unsigned int phy_inst, bool clock_on) { … } void dcn35_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) { … } void dcn35_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) { … } /* In headless boot cases, DIG may be turned * on which causes HW/SW discrepancies. * To avoid this, power down hardware on boot * if DIG is turned on */ void dcn35_power_down_on_boot(struct dc *dc) { … } bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable) { … } void dcn35_z10_restore(const struct dc *dc) { … } void dcn35_init_pipes(struct dc *dc, struct dc_state *context) { … } void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context) { … } /* disable HW used by plane. * note: cannot disable until disconnect is complete */ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) { … } void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx) { … } void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, struct pg_block_update *update_state) { … } void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, struct pg_block_update *update_state) { … } /** * dcn35_hw_block_power_down() - power down sequence * * The following sequence describes the ON-OFF (ONO) for power down: * * ONO Region 3, DCPG 25: hpo - SKIPPED * ONO Region 4, DCPG 0: dchubp0, dpp0 * ONO Region 6, DCPG 1: dchubp1, dpp1 * ONO Region 8, DCPG 2: dchubp2, dpp2 * ONO Region 10, DCPG 3: dchubp3, dpp3 * ONO Region 1, DCPG 23: dchubbub dchvm dchubbubmem - SKIPPED. PMFW will pwr dwn at IPS2 entry * ONO Region 5, DCPG 16: dsc0 * ONO Region 7, DCPG 17: dsc1 * ONO Region 9, DCPG 18: dsc2 * ONO Region 11, DCPG 19: dsc3 * ONO Region 2, DCPG 24: mpc opp optc dwb * ONO Region 0, DCPG 22: dccg dio dcio - SKIPPED. will be pwr dwn after lono timer is armed * * If sequential ONO is specified the order is modified from ONO Region 11 -> ONO Region 0 descending. * * @dc: Current DC state * @update_state: update PG sequence states for HW block */ void dcn35_hw_block_power_down(struct dc *dc, struct pg_block_update *update_state) { … } /** * dcn35_hw_block_power_up() - power up sequence * * The following sequence describes the ON-OFF (ONO) for power up: * * ONO Region 0, DCPG 22: dccg dio dcio - SKIPPED * ONO Region 2, DCPG 24: mpc opp optc dwb * ONO Region 5, DCPG 16: dsc0 * ONO Region 7, DCPG 17: dsc1 * ONO Region 9, DCPG 18: dsc2 * ONO Region 11, DCPG 19: dsc3 * ONO Region 1, DCPG 23: dchubbub dchvm dchubbubmem - SKIPPED. PMFW will power up at IPS2 exit * ONO Region 4, DCPG 0: dchubp0, dpp0 * ONO Region 6, DCPG 1: dchubp1, dpp1 * ONO Region 8, DCPG 2: dchubp2, dpp2 * ONO Region 10, DCPG 3: dchubp3, dpp3 * ONO Region 3, DCPG 25: hpo - SKIPPED * * If sequential ONO is specified the order is modified from ONO Region 0 -> ONO Region 11 ascending. * * @dc: Current DC state * @update_state: update PG sequence states for HW block */ void dcn35_hw_block_power_up(struct dc *dc, struct pg_block_update *update_state) { … } void dcn35_root_clock_control(struct dc *dc, struct pg_block_update *update_state, bool power_on) { … } void dcn35_prepare_bandwidth( struct dc *dc, struct dc_state *context) { … } void dcn35_optimize_bandwidth( struct dc *dc, struct dc_state *context) { … } void dcn35_set_drr(struct pipe_ctx **pipe_ctx, int num_pipes, struct dc_crtc_timing_adjust adjust) { … } void dcn35_set_static_screen_control(struct pipe_ctx **pipe_ctx, int num_pipes, const struct dc_static_screen_params *params) { … } void dcn35_set_long_vblank(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max) { … } static bool should_avoid_empty_tu(struct pipe_ctx *pipe_ctx) { … } bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx) { … }
Codebase Browser
linux