/* * Copyright 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD * */ #include "dccg.h" #include "clk_mgr_internal.h" #include "dcn30_clk_mgr_smu_msg.h" #include "dcn20/dcn20_clk_mgr.h" #include "dce100/dce_clk_mgr.h" #include "dcn30/dcn30_clk_mgr.h" #include "dml/dcn30/dcn30_fpu.h" #include "reg_helper.h" #include "core_types.h" #include "dm_helpers.h" #include "atomfirmware.h" #include "sienna_cichlid_ip_offset.h" #include "dcn/dcn_3_0_0_offset.h" #include "dcn/dcn_3_0_0_sh_mask.h" #include "nbio/nbio_7_4_offset.h" #include "dpcs/dpcs_3_0_0_offset.h" #include "dpcs/dpcs_3_0_0_sh_mask.h" #include "mmhub/mmhub_2_0_0_offset.h" #include "mmhub/mmhub_2_0_0_sh_mask.h" #include "dcn30_smu11_driver_if.h" #undef FN #define FN(reg_name, field_name) … #define REG(reg) … #define BASE_INNER(seg) … #define BASE(seg) … #define SR(reg_name) … #undef CLK_SRI #define CLK_SRI(reg_name, block, inst) … static const struct clk_mgr_registers clk_mgr_regs = …; static const struct clk_mgr_shift clk_mgr_shift = …; static const struct clk_mgr_mask clk_mgr_mask = …; /* Query SMU for all clock states for a particular clock */ static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels) { … } static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) { … } void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) { … } static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) { … } static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower) { … } static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base) { … } /* Set min memclk to minimum, either constrained by the current mode or DPM0 */ static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode) { … } /* Set max memclk to highest DPM value */ static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base) { … } static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) { … } static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) { … } /* Get current memclk states, update bounding box */ static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base) { … } static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base) { … } static bool dcn3_are_clock_states_equal(struct dc_clocks *a, struct dc_clocks *b) { … } static void dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base) { … } /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link) { … } static struct clk_mgr_funcs dcn3_funcs = …; static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr) { … } struct clk_mgr_funcs dcn3_fpga_funcs = …; /*todo for dcn30 for clk register offset*/ void dcn3_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu, struct dccg *dccg) { … } void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr) { … }
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