linux/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h

// SPDX-License-Identifier: MIT
/*
 * Copyright (C) 2021 Advanced Micro Devices, Inc.
 *
 * Authors: AMD
 */

#ifndef _dcn_3_0_3_OFFSET_HEADER
#define _dcn_3_0_3_OFFSET_HEADER

// addressBlock: dce_dc_mmhubbub_vga_dispdec
// base address: 0x0
#define mmVGA_MEM_WRITE_PAGE_ADDR
#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX
#define mmVGA_MEM_READ_PAGE_ADDR
#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX
#define mmVGA_RENDER_CONTROL
#define mmVGA_RENDER_CONTROL_BASE_IDX
#define mmVGA_SEQUENCER_RESET_CONTROL
#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX
#define mmVGA_MODE_CONTROL
#define mmVGA_MODE_CONTROL_BASE_IDX
#define mmVGA_SURFACE_PITCH_SELECT
#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX
#define mmVGA_MEMORY_BASE_ADDRESS
#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX
#define mmVGA_DISPBUF1_SURFACE_ADDR
#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX
#define mmVGA_DISPBUF2_SURFACE_ADDR
#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX
#define mmVGA_HDP_CONTROL
#define mmVGA_HDP_CONTROL_BASE_IDX
#define mmVGA_CACHE_CONTROL
#define mmVGA_CACHE_CONTROL_BASE_IDX
#define mmD1VGA_CONTROL
#define mmD1VGA_CONTROL_BASE_IDX
#define mmD2VGA_CONTROL
#define mmD2VGA_CONTROL_BASE_IDX
#define mmVGA_STATUS
#define mmVGA_STATUS_BASE_IDX
#define mmVGA_INTERRUPT_CONTROL
#define mmVGA_INTERRUPT_CONTROL_BASE_IDX
#define mmVGA_STATUS_CLEAR
#define mmVGA_STATUS_CLEAR_BASE_IDX
#define mmVGA_INTERRUPT_STATUS
#define mmVGA_INTERRUPT_STATUS_BASE_IDX
#define mmVGA_MAIN_CONTROL
#define mmVGA_MAIN_CONTROL_BASE_IDX
#define mmVGA_TEST_CONTROL
#define mmVGA_TEST_CONTROL_BASE_IDX
#define mmVGA_QOS_CTRL
#define mmVGA_QOS_CTRL_BASE_IDX
#define mmCRTC8_IDX
#define mmCRTC8_IDX_BASE_IDX
#define mmCRTC8_DATA
#define mmCRTC8_DATA_BASE_IDX
#define mmGENFC_WT
#define mmGENFC_WT_BASE_IDX
#define mmGENS1
#define mmGENS1_BASE_IDX
#define mmATTRDW
#define mmATTRDW_BASE_IDX
#define mmATTRX
#define mmATTRX_BASE_IDX
#define mmATTRDR
#define mmATTRDR_BASE_IDX
#define mmGENMO_WT
#define mmGENMO_WT_BASE_IDX
#define mmGENS0
#define mmGENS0_BASE_IDX
#define mmGENENB
#define mmGENENB_BASE_IDX
#define mmSEQ8_IDX
#define mmSEQ8_IDX_BASE_IDX
#define mmSEQ8_DATA
#define mmSEQ8_DATA_BASE_IDX
#define mmDAC_MASK
#define mmDAC_MASK_BASE_IDX
#define mmDAC_R_INDEX
#define mmDAC_R_INDEX_BASE_IDX
#define mmDAC_W_INDEX
#define mmDAC_W_INDEX_BASE_IDX
#define mmDAC_DATA
#define mmDAC_DATA_BASE_IDX
#define mmGENFC_RD
#define mmGENFC_RD_BASE_IDX
#define mmGENMO_RD
#define mmGENMO_RD_BASE_IDX
#define mmGRPH8_IDX
#define mmGRPH8_IDX_BASE_IDX
#define mmGRPH8_DATA
#define mmGRPH8_DATA_BASE_IDX
#define mmCRTC8_IDX_1
#define mmCRTC8_IDX_1_BASE_IDX
#define mmCRTC8_DATA_1
#define mmCRTC8_DATA_1_BASE_IDX
#define mmGENFC_WT_1
#define mmGENFC_WT_1_BASE_IDX
#define mmGENS1_1
#define mmGENS1_1_BASE_IDX
#define mmD3VGA_CONTROL
#define mmD3VGA_CONTROL_BASE_IDX
#define mmD4VGA_CONTROL
#define mmD4VGA_CONTROL_BASE_IDX
#define mmD5VGA_CONTROL
#define mmD5VGA_CONTROL_BASE_IDX
#define mmD6VGA_CONTROL
#define mmD6VGA_CONTROL_BASE_IDX
#define mmVGA_SOURCE_SELECT
#define mmVGA_SOURCE_SELECT_BASE_IDX


// addressBlock: dce_dc_dccg_dccg_dispdec
// base address: 0x0
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX
#define mmDP_DTO_DBUF_EN
#define mmDP_DTO_DBUF_EN_BASE_IDX
#define mmDPREFCLK_CGTT_BLK_CTRL_REG
#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX
#define mmREFCLK_CNTL
#define mmREFCLK_CNTL_BASE_IDX
#define mmREFCLK_CGTT_BLK_CTRL_REG
#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX
#define mmDCCG_PERFMON_CNTL2
#define mmDCCG_PERFMON_CNTL2_BASE_IDX
#define mmDCCG_DS_DTO_INCR
#define mmDCCG_DS_DTO_INCR_BASE_IDX
#define mmDCCG_DS_DTO_MODULO
#define mmDCCG_DS_DTO_MODULO_BASE_IDX
#define mmDCCG_DS_CNTL
#define mmDCCG_DS_CNTL_BASE_IDX
#define mmDCCG_DS_HW_CAL_INTERVAL
#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX
#define mmDPREFCLK_CNTL
#define mmDPREFCLK_CNTL_BASE_IDX
#define mmDCE_VERSION
#define mmDCE_VERSION_BASE_IDX
#define mmDCCG_GTC_CNTL
#define mmDCCG_GTC_CNTL_BASE_IDX
#define mmDCCG_GTC_DTO_INCR
#define mmDCCG_GTC_DTO_INCR_BASE_IDX
#define mmDCCG_GTC_DTO_MODULO
#define mmDCCG_GTC_DTO_MODULO_BASE_IDX
#define mmDCCG_GTC_CURRENT
#define mmDCCG_GTC_CURRENT_BASE_IDX
#define mmDSCCLK0_DTO_PARAM
#define mmDSCCLK0_DTO_PARAM_BASE_IDX
#define mmDSCCLK1_DTO_PARAM
#define mmDSCCLK1_DTO_PARAM_BASE_IDX
#define mmMILLISECOND_TIME_BASE_DIV
#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX
#define mmDISPCLK_FREQ_CHANGE_CNTL
#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX
#define mmDCCG_PERFMON_CNTL
#define mmDCCG_PERFMON_CNTL_BASE_IDX
#define mmDCCG_GATE_DISABLE_CNTL
#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX
#define mmDISPCLK_CGTT_BLK_CTRL_REG
#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX
#define mmSOCCLK_CGTT_BLK_CTRL_REG
#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX
#define mmDCCG_CAC_STATUS
#define mmDCCG_CAC_STATUS_BASE_IDX
#define mmMICROSECOND_TIME_BASE_DIV
#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX
#define mmDCCG_GATE_DISABLE_CNTL2
#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX
#define mmSYMCLK_CGTT_BLK_CTRL_REG
#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX
#define mmDCCG_DISP_CNTL_REG
#define mmDCCG_DISP_CNTL_REG_BASE_IDX
#define mmOTG0_PIXEL_RATE_CNTL
#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX
#define mmDP_DTO0_PHASE
#define mmDP_DTO0_PHASE_BASE_IDX
#define mmDP_DTO0_MODULO
#define mmDP_DTO0_MODULO_BASE_IDX
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX
#define mmOTG1_PIXEL_RATE_CNTL
#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX
#define mmDP_DTO1_PHASE
#define mmDP_DTO1_PHASE_BASE_IDX
#define mmDP_DTO1_MODULO
#define mmDP_DTO1_MODULO_BASE_IDX
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX
#define mmDPPCLK_CGTT_BLK_CTRL_REG
#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX
#define mmDPPCLK0_DTO_PARAM
#define mmDPPCLK0_DTO_PARAM_BASE_IDX
#define mmDPPCLK1_DTO_PARAM
#define mmDPPCLK1_DTO_PARAM_BASE_IDX
#define mmDCCG_CAC_STATUS2
#define mmDCCG_CAC_STATUS2_BASE_IDX
#define mmSYMCLKA_CLOCK_ENABLE
#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX
#define mmSYMCLKB_CLOCK_ENABLE
#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX
#define mmDCCG_SOFT_RESET
#define mmDCCG_SOFT_RESET_BASE_IDX
#define mmDSCCLK_DTO_CTRL
#define mmDSCCLK_DTO_CTRL_BASE_IDX
#define mmDCCG_AUDIO_DTO_SOURCE
#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX
#define mmDCCG_AUDIO_DTO0_PHASE
#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX
#define mmDCCG_AUDIO_DTO0_MODULE
#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX
#define mmDCCG_AUDIO_DTO1_PHASE
#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX
#define mmDCCG_AUDIO_DTO1_MODULE
#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX
#define mmDPPCLK_DTO_CTRL
#define mmDPPCLK_DTO_CTRL_BASE_IDX
#define mmDCCG_VSYNC_CNT_CTRL
#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX
#define mmDCCG_VSYNC_CNT_INT_CTRL
#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX
#define mmFORCE_SYMCLK_DISABLE
#define mmFORCE_SYMCLK_DISABLE_BASE_IDX
#define mmPHYASYMCLK_CLOCK_CNTL
#define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX
#define mmPHYBSYMCLK_CLOCK_CNTL
#define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX


// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
// base address: 0x0
#define mmDENTIST_DISPCLK_CNTL
#define mmDENTIST_DISPCLK_CNTL_BASE_IDX


// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
// base address: 0x0
#define mmDC_PERFMON0_PERFCOUNTER_CNTL
#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON0_PERFCOUNTER_STATE
#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON0_PERFMON_CNTL
#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON0_PERFMON_CNTL2
#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON0_PERFMON_HI
#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON0_PERFMON_LOW
#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
// base address: 0x2f8
#define mmDC_PERFMON1_PERFCOUNTER_CNTL
#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON1_PERFCOUNTER_STATE
#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON1_PERFMON_CNTL
#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON1_PERFMON_CNTL2
#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON1_PERFMON_HI
#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON1_PERFMON_LOW
#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_dmu_dmu_misc_dispdec
// base address: 0x0
#define mmCC_DC_PIPE_DIS
#define mmCC_DC_PIPE_DIS_BASE_IDX
#define mmDMU_CLK_CNTL
#define mmDMU_CLK_CNTL_BASE_IDX
#define mmDMU_MEM_PWR_CNTL
#define mmDMU_MEM_PWR_CNTL_BASE_IDX
#define mmDMCU_SMU_INTERRUPT_CNTL
#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX
#define mmSMU_INTERRUPT_CONTROL
#define mmSMU_INTERRUPT_CONTROL_BASE_IDX
#define mmDMU_MISC_ALLOW_DS_FORCE
#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX


// addressBlock: dce_dc_dmu_dmcu_dispdec
// base address: 0x0
#define mmDMCU_CTRL
#define mmDMCU_CTRL_BASE_IDX
#define mmDMCU_STATUS
#define mmDMCU_STATUS_BASE_IDX
#define mmDMCU_PC_START_ADDR
#define mmDMCU_PC_START_ADDR_BASE_IDX
#define mmDMCU_FW_START_ADDR
#define mmDMCU_FW_START_ADDR_BASE_IDX
#define mmDMCU_FW_END_ADDR
#define mmDMCU_FW_END_ADDR_BASE_IDX
#define mmDMCU_FW_ISR_START_ADDR
#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX
#define mmDMCU_FW_CS_HI
#define mmDMCU_FW_CS_HI_BASE_IDX
#define mmDMCU_FW_CS_LO
#define mmDMCU_FW_CS_LO_BASE_IDX
#define mmDMCU_RAM_ACCESS_CTRL
#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX
#define mmDMCU_ERAM_WR_CTRL
#define mmDMCU_ERAM_WR_CTRL_BASE_IDX
#define mmDMCU_ERAM_WR_DATA
#define mmDMCU_ERAM_WR_DATA_BASE_IDX
#define mmDMCU_ERAM_RD_CTRL
#define mmDMCU_ERAM_RD_CTRL_BASE_IDX
#define mmDMCU_ERAM_RD_DATA
#define mmDMCU_ERAM_RD_DATA_BASE_IDX
#define mmDMCU_IRAM_WR_CTRL
#define mmDMCU_IRAM_WR_CTRL_BASE_IDX
#define mmDMCU_IRAM_WR_DATA
#define mmDMCU_IRAM_WR_DATA_BASE_IDX
#define mmDMCU_IRAM_RD_CTRL
#define mmDMCU_IRAM_RD_CTRL_BASE_IDX
#define mmDMCU_IRAM_RD_DATA
#define mmDMCU_IRAM_RD_DATA_BASE_IDX
#define mmDMCU_EVENT_TRIGGER
#define mmDMCU_EVENT_TRIGGER_BASE_IDX
#define mmDMCU_UC_INTERNAL_INT_STATUS
#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX
#define mmDMCU_INTERRUPT_STATUS
#define mmDMCU_INTERRUPT_STATUS_BASE_IDX
#define mmDMCU_INTERRUPT_STATUS_1
#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX
#define mmDC_DMCU_SCRATCH
#define mmDC_DMCU_SCRATCH_BASE_IDX
#define mmDMCU_INT_CNT
#define mmDMCU_INT_CNT_BASE_IDX
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX
#define mmDMCU_UC_CLK_GATING_CNTL
#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX
#define mmMASTER_COMM_DATA_REG1
#define mmMASTER_COMM_DATA_REG1_BASE_IDX
#define mmMASTER_COMM_DATA_REG2
#define mmMASTER_COMM_DATA_REG2_BASE_IDX
#define mmMASTER_COMM_DATA_REG3
#define mmMASTER_COMM_DATA_REG3_BASE_IDX
#define mmMASTER_COMM_CMD_REG
#define mmMASTER_COMM_CMD_REG_BASE_IDX
#define mmMASTER_COMM_CNTL_REG
#define mmMASTER_COMM_CNTL_REG_BASE_IDX
#define mmSLAVE_COMM_DATA_REG1
#define mmSLAVE_COMM_DATA_REG1_BASE_IDX
#define mmSLAVE_COMM_DATA_REG2
#define mmSLAVE_COMM_DATA_REG2_BASE_IDX
#define mmSLAVE_COMM_DATA_REG3
#define mmSLAVE_COMM_DATA_REG3_BASE_IDX
#define mmSLAVE_COMM_CMD_REG
#define mmSLAVE_COMM_CMD_REG_BASE_IDX
#define mmSLAVE_COMM_CNTL_REG
#define mmSLAVE_COMM_CNTL_REG_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_STATUS1
#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_STATUS2
#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_STATUS3
#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_STATUS4
#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_STATUS5
#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX
#define mmDMCU_DPRX_INTERRUPT_STATUS1
#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX
#define mmDMCU_INTERRUPT_STATUS_CONTINUE
#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX
#define mmDMCU_INT_CNT_CONTINUE
#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX
#define mmDMCU_INTERRUPT_STATUS_2
#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX


// addressBlock: dce_dc_dmu_ihc_dispdec
// base address: 0x0
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX
#define mmDC_GPU_TIMER_READ
#define mmDC_GPU_TIMER_READ_BASE_IDX
#define mmDC_GPU_TIMER_READ_CNTL
#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX
#define mmDISP_INTERRUPT_STATUS
#define mmDISP_INTERRUPT_STATUS_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE
#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE2
#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE3
#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE4
#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE5
#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE6
#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE7
#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE8
#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE9
#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE10
#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE11
#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE12
#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE13
#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE14
#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE15
#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE16
#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE17
#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE18
#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE19
#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE20
#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE21
#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE22
#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX
#define mmDC_GPU_TIMER_START_POSITION_VREADY
#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX
#define mmDC_GPU_TIMER_START_POSITION_FLIP
#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE23
#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE24
#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX
#define mmDISP_INTERRUPT_STATUS_CONTINUE25
#define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX
#define mmDCCG_INTERRUPT_DEST
#define mmDCCG_INTERRUPT_DEST_BASE_IDX
#define mmDMU_INTERRUPT_DEST
#define mmDMU_INTERRUPT_DEST_BASE_IDX
#define mmDMU_INTERRUPT_DEST2
#define mmDMU_INTERRUPT_DEST2_BASE_IDX
#define mmDCPG_INTERRUPT_DEST
#define mmDCPG_INTERRUPT_DEST_BASE_IDX
#define mmDCPG_INTERRUPT_DEST2
#define mmDCPG_INTERRUPT_DEST2_BASE_IDX
#define mmMMHUBBUB_INTERRUPT_DEST
#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX
#define mmWB_INTERRUPT_DEST
#define mmWB_INTERRUPT_DEST_BASE_IDX
#define mmDCHUB_INTERRUPT_DEST
#define mmDCHUB_INTERRUPT_DEST_BASE_IDX
#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST
#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX
#define mmDCHUB_INTERRUPT_DEST2
#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX
#define mmDPP_PERFCOUNTER_INTERRUPT_DEST
#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX
#define mmMPC_INTERRUPT_DEST
#define mmMPC_INTERRUPT_DEST_BASE_IDX
#define mmOPP_INTERRUPT_DEST
#define mmOPP_INTERRUPT_DEST_BASE_IDX
#define mmOPTC_INTERRUPT_DEST
#define mmOPTC_INTERRUPT_DEST_BASE_IDX
#define mmOTG0_INTERRUPT_DEST
#define mmOTG0_INTERRUPT_DEST_BASE_IDX
#define mmOTG1_INTERRUPT_DEST
#define mmOTG1_INTERRUPT_DEST_BASE_IDX
#define mmOTG2_INTERRUPT_DEST
#define mmOTG2_INTERRUPT_DEST_BASE_IDX
#define mmOTG3_INTERRUPT_DEST
#define mmOTG3_INTERRUPT_DEST_BASE_IDX
#define mmOTG4_INTERRUPT_DEST
#define mmOTG4_INTERRUPT_DEST_BASE_IDX
#define mmOTG5_INTERRUPT_DEST
#define mmOTG5_INTERRUPT_DEST_BASE_IDX
#define mmDIG_INTERRUPT_DEST
#define mmDIG_INTERRUPT_DEST_BASE_IDX
#define mmI2C_DDC_HPD_INTERRUPT_DEST
#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX
#define mmDIO_INTERRUPT_DEST
#define mmDIO_INTERRUPT_DEST_BASE_IDX
#define mmDCIO_INTERRUPT_DEST
#define mmDCIO_INTERRUPT_DEST_BASE_IDX
#define mmHPD_INTERRUPT_DEST
#define mmHPD_INTERRUPT_DEST_BASE_IDX
#define mmAZ_INTERRUPT_DEST
#define mmAZ_INTERRUPT_DEST_BASE_IDX
#define mmAUX_INTERRUPT_DEST
#define mmAUX_INTERRUPT_DEST_BASE_IDX
#define mmDSC_INTERRUPT_DEST
#define mmDSC_INTERRUPT_DEST_BASE_IDX


// addressBlock: dce_dc_dmu_fgsec_dispdec
// base address: 0x0
#define mmDMCUB_RBBMIF_SEC_CNTL
#define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX


// addressBlock: dce_dc_dmu_rbbmif_dispdec
// base address: 0x0
#define mmRBBMIF_TIMEOUT
#define mmRBBMIF_TIMEOUT_BASE_IDX
#define mmRBBMIF_STATUS
#define mmRBBMIF_STATUS_BASE_IDX
#define mmRBBMIF_STATUS_2
#define mmRBBMIF_STATUS_2_BASE_IDX
#define mmRBBMIF_INT_STATUS
#define mmRBBMIF_INT_STATUS_BASE_IDX
#define mmRBBMIF_TIMEOUT_DIS
#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX
#define mmRBBMIF_TIMEOUT_DIS_2
#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX
#define mmRBBMIF_STATUS_FLAG
#define mmRBBMIF_STATUS_FLAG_BASE_IDX


// addressBlock: dce_dc_dmu_dmcub_dispdec
// base address: 0x0
#define mmDMCUB_REGION0_OFFSET
#define mmDMCUB_REGION0_OFFSET_BASE_IDX
#define mmDMCUB_REGION0_OFFSET_HIGH
#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION1_OFFSET
#define mmDMCUB_REGION1_OFFSET_BASE_IDX
#define mmDMCUB_REGION1_OFFSET_HIGH
#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION2_OFFSET
#define mmDMCUB_REGION2_OFFSET_BASE_IDX
#define mmDMCUB_REGION2_OFFSET_HIGH
#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION4_OFFSET
#define mmDMCUB_REGION4_OFFSET_BASE_IDX
#define mmDMCUB_REGION4_OFFSET_HIGH
#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION5_OFFSET
#define mmDMCUB_REGION5_OFFSET_BASE_IDX
#define mmDMCUB_REGION5_OFFSET_HIGH
#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION6_OFFSET
#define mmDMCUB_REGION6_OFFSET_BASE_IDX
#define mmDMCUB_REGION6_OFFSET_HIGH
#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION7_OFFSET
#define mmDMCUB_REGION7_OFFSET_BASE_IDX
#define mmDMCUB_REGION7_OFFSET_HIGH
#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION0_TOP_ADDRESS
#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION1_TOP_ADDRESS
#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION2_TOP_ADDRESS
#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION4_TOP_ADDRESS
#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION5_TOP_ADDRESS
#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION6_TOP_ADDRESS
#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION7_TOP_ADDRESS
#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW0_BASE_ADDRESS
#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW1_BASE_ADDRESS
#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW2_BASE_ADDRESS
#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW3_BASE_ADDRESS
#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW4_BASE_ADDRESS
#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW5_BASE_ADDRESS
#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW6_BASE_ADDRESS
#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW7_BASE_ADDRESS
#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW0_TOP_ADDRESS
#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW1_TOP_ADDRESS
#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW2_TOP_ADDRESS
#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW3_TOP_ADDRESS
#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW4_TOP_ADDRESS
#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW5_TOP_ADDRESS
#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW6_TOP_ADDRESS
#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW7_TOP_ADDRESS
#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX
#define mmDMCUB_REGION3_CW0_OFFSET
#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX
#define mmDMCUB_REGION3_CW0_OFFSET_HIGH
#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION3_CW1_OFFSET
#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX
#define mmDMCUB_REGION3_CW1_OFFSET_HIGH
#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION3_CW2_OFFSET
#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX
#define mmDMCUB_REGION3_CW2_OFFSET_HIGH
#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION3_CW3_OFFSET
#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX
#define mmDMCUB_REGION3_CW3_OFFSET_HIGH
#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION3_CW4_OFFSET
#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX
#define mmDMCUB_REGION3_CW4_OFFSET_HIGH
#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION3_CW5_OFFSET
#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX
#define mmDMCUB_REGION3_CW5_OFFSET_HIGH
#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION3_CW6_OFFSET
#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX
#define mmDMCUB_REGION3_CW6_OFFSET_HIGH
#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_REGION3_CW7_OFFSET
#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX
#define mmDMCUB_REGION3_CW7_OFFSET_HIGH
#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX
#define mmDMCUB_INTERRUPT_ENABLE
#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX
#define mmDMCUB_INTERRUPT_ACK
#define mmDMCUB_INTERRUPT_ACK_BASE_IDX
#define mmDMCUB_INTERRUPT_STATUS
#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX
#define mmDMCUB_INTERRUPT_TYPE
#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX
#define mmDMCUB_EXT_INTERRUPT_STATUS
#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX
#define mmDMCUB_EXT_INTERRUPT_CTXID
#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX
#define mmDMCUB_EXT_INTERRUPT_ACK
#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX
#define mmDMCUB_INST_FETCH_FAULT_ADDR
#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX
#define mmDMCUB_DATA_WRITE_FAULT_ADDR
#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX
#define mmDMCUB_SEC_CNTL
#define mmDMCUB_SEC_CNTL_BASE_IDX
#define mmDMCUB_MEM_CNTL
#define mmDMCUB_MEM_CNTL_BASE_IDX
#define mmDMCUB_INBOX0_BASE_ADDRESS
#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_INBOX0_SIZE
#define mmDMCUB_INBOX0_SIZE_BASE_IDX
#define mmDMCUB_INBOX0_WPTR
#define mmDMCUB_INBOX0_WPTR_BASE_IDX
#define mmDMCUB_INBOX0_RPTR
#define mmDMCUB_INBOX0_RPTR_BASE_IDX
#define mmDMCUB_INBOX1_BASE_ADDRESS
#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_INBOX1_SIZE
#define mmDMCUB_INBOX1_SIZE_BASE_IDX
#define mmDMCUB_INBOX1_WPTR
#define mmDMCUB_INBOX1_WPTR_BASE_IDX
#define mmDMCUB_INBOX1_RPTR
#define mmDMCUB_INBOX1_RPTR_BASE_IDX
#define mmDMCUB_OUTBOX0_BASE_ADDRESS
#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_OUTBOX0_SIZE
#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX
#define mmDMCUB_OUTBOX0_WPTR
#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX
#define mmDMCUB_OUTBOX0_RPTR
#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX
#define mmDMCUB_OUTBOX1_BASE_ADDRESS
#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX
#define mmDMCUB_OUTBOX1_SIZE
#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX
#define mmDMCUB_OUTBOX1_WPTR
#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX
#define mmDMCUB_OUTBOX1_RPTR
#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX
#define mmDMCUB_TIMER_TRIGGER0
#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX
#define mmDMCUB_TIMER_TRIGGER1
#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX
#define mmDMCUB_TIMER_WINDOW
#define mmDMCUB_TIMER_WINDOW_BASE_IDX
#define mmDMCUB_SCRATCH0
#define mmDMCUB_SCRATCH0_BASE_IDX
#define mmDMCUB_SCRATCH1
#define mmDMCUB_SCRATCH1_BASE_IDX
#define mmDMCUB_SCRATCH2
#define mmDMCUB_SCRATCH2_BASE_IDX
#define mmDMCUB_SCRATCH3
#define mmDMCUB_SCRATCH3_BASE_IDX
#define mmDMCUB_SCRATCH4
#define mmDMCUB_SCRATCH4_BASE_IDX
#define mmDMCUB_SCRATCH5
#define mmDMCUB_SCRATCH5_BASE_IDX
#define mmDMCUB_SCRATCH6
#define mmDMCUB_SCRATCH6_BASE_IDX
#define mmDMCUB_SCRATCH7
#define mmDMCUB_SCRATCH7_BASE_IDX
#define mmDMCUB_SCRATCH8
#define mmDMCUB_SCRATCH8_BASE_IDX
#define mmDMCUB_SCRATCH9
#define mmDMCUB_SCRATCH9_BASE_IDX
#define mmDMCUB_SCRATCH10
#define mmDMCUB_SCRATCH10_BASE_IDX
#define mmDMCUB_SCRATCH11
#define mmDMCUB_SCRATCH11_BASE_IDX
#define mmDMCUB_SCRATCH12
#define mmDMCUB_SCRATCH12_BASE_IDX
#define mmDMCUB_SCRATCH13
#define mmDMCUB_SCRATCH13_BASE_IDX
#define mmDMCUB_SCRATCH14
#define mmDMCUB_SCRATCH14_BASE_IDX
#define mmDMCUB_SCRATCH15
#define mmDMCUB_SCRATCH15_BASE_IDX
#define mmDMCUB_CNTL
#define mmDMCUB_CNTL_BASE_IDX
#define mmDMCUB_GPINT_DATAIN0
#define mmDMCUB_GPINT_DATAIN0_BASE_IDX
#define mmDMCUB_GPINT_DATAIN1
#define mmDMCUB_GPINT_DATAIN1_BASE_IDX
#define mmDMCUB_GPINT_DATAOUT
#define mmDMCUB_GPINT_DATAOUT_BASE_IDX
#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR
#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX
#define mmDMCUB_LS_WAKE_INT_ENABLE
#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX
#define mmDMCUB_MEM_PWR_CNTL
#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX
#define mmDMCUB_TIMER_CURRENT
#define mmDMCUB_TIMER_CURRENT_BASE_IDX
#define mmDMCUB_PROC_ID
#define mmDMCUB_PROC_ID_BASE_IDX


// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
// base address: 0x0
#define mmMCIF_WB_BUFMGR_SW_CONTROL
#define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX
#define mmMCIF_WB_BUFMGR_STATUS
#define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX
#define mmMCIF_WB_BUF_PITCH
#define mmMCIF_WB_BUF_PITCH_BASE_IDX
#define mmMCIF_WB_BUF_1_STATUS
#define mmMCIF_WB_BUF_1_STATUS_BASE_IDX
#define mmMCIF_WB_BUF_1_STATUS2
#define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX
#define mmMCIF_WB_BUF_2_STATUS
#define mmMCIF_WB_BUF_2_STATUS_BASE_IDX
#define mmMCIF_WB_BUF_2_STATUS2
#define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX
#define mmMCIF_WB_BUF_3_STATUS
#define mmMCIF_WB_BUF_3_STATUS_BASE_IDX
#define mmMCIF_WB_BUF_3_STATUS2
#define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX
#define mmMCIF_WB_BUF_4_STATUS
#define mmMCIF_WB_BUF_4_STATUS_BASE_IDX
#define mmMCIF_WB_BUF_4_STATUS2
#define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX
#define mmMCIF_WB_ARBITRATION_CONTROL
#define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX
#define mmMCIF_WB_SCLK_CHANGE
#define mmMCIF_WB_SCLK_CHANGE_BASE_IDX
#define mmMCIF_WB_BUF_1_ADDR_Y
#define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX
#define mmMCIF_WB_BUF_1_ADDR_C
#define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX
#define mmMCIF_WB_BUF_2_ADDR_Y
#define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX
#define mmMCIF_WB_BUF_2_ADDR_C
#define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX
#define mmMCIF_WB_BUF_3_ADDR_Y
#define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX
#define mmMCIF_WB_BUF_3_ADDR_C
#define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX
#define mmMCIF_WB_BUF_4_ADDR_Y
#define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX
#define mmMCIF_WB_BUF_4_ADDR_C
#define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX
#define mmMCIF_WB_BUFMGR_VCE_CONTROL
#define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX
#define mmMCIF_WB_NB_PSTATE_CONTROL
#define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX
#define mmMCIF_WB_CLOCK_GATER_CONTROL
#define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX
#define mmMCIF_WB_SELF_REFRESH_CONTROL
#define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX
#define mmMULTI_LEVEL_QOS_CTRL
#define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX
#define mmMCIF_WB_BUF_LUMA_SIZE
#define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX
#define mmMCIF_WB_BUF_CHROMA_SIZE
#define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX
#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH
#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX
#define mmMCIF_WB_BUF_1_ADDR_C_HIGH
#define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX
#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH
#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX
#define mmMCIF_WB_BUF_2_ADDR_C_HIGH
#define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX
#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH
#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX
#define mmMCIF_WB_BUF_3_ADDR_C_HIGH
#define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX
#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH
#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX
#define mmMCIF_WB_BUF_4_ADDR_C_HIGH
#define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX
#define mmMCIF_WB_BUF_1_RESOLUTION
#define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX
#define mmMCIF_WB_BUF_2_RESOLUTION
#define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX
#define mmMCIF_WB_BUF_3_RESOLUTION
#define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX
#define mmMCIF_WB_BUF_4_RESOLUTION
#define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX
#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI
#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX
#define mmMCIF_WB_VMID_CONTROL
#define mmMCIF_WB_VMID_CONTROL_BASE_IDX
#define mmMCIF_WB_MIN_TTO
#define mmMCIF_WB_MIN_TTO_BASE_IDX


// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
// base address: 0x0
#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK
#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX
#define mmMCIF_WB_WATERMARK
#define mmMCIF_WB_WATERMARK_BASE_IDX
#define mmMMHUBBUB_WARMUP_CONFIG
#define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX
#define mmMMHUBBUB_WARMUP_CONTROL_STATUS
#define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX
#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW
#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX
#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH
#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX
#define mmMMHUBBUB_WARMUP_ADDR_REGION
#define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX
#define mmMMHUBBUB_MIN_TTO
#define mmMMHUBBUB_MIN_TTO_BASE_IDX
#define mmWBIF_SMU_WM_CONTROL
#define mmWBIF_SMU_WM_CONTROL_BASE_IDX
#define mmWBIF0_MISC_CTRL
#define mmWBIF0_MISC_CTRL_BASE_IDX
#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER
#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX
#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER
#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX
#define mmVGA_SRC_SPLIT_CNTL
#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX
#define mmMMHUBBUB_MEM_PWR_STATUS
#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX
#define mmMMHUBBUB_MEM_PWR_CNTL
#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX
#define mmMMHUBBUB_CLOCK_CNTL
#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX
#define mmMMHUBBUB_SOFT_RESET
#define mmMMHUBBUB_SOFT_RESET_BASE_IDX
#define mmDMU_IF_ERR_STATUS
#define mmDMU_IF_ERR_STATUS_BASE_IDX
#define mmMMHUBBUB_CLIENT_UNIT_ID
#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX
#define mmMMHUBBUB_WARMUP_VMID_CONTROL
#define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX


// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
// base address: 0x0
#define mmMCIF_CONTROL
#define mmMCIF_CONTROL_BASE_IDX
#define mmMCIF_WRITE_COMBINE_CONTROL
#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX


// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
// base address: 0xd48
#define mmDC_PERFMON2_PERFCOUNTER_CNTL
#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON2_PERFCOUNTER_STATE
#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON2_PERFMON_CNTL
#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON2_PERFMON_CNTL2
#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON2_PERFMON_HI
#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON2_PERFMON_LOW
#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream0_dispdec
// base address: 0x0
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM0_AZALIA_STREAM_DATA
#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream1_dispdec
// base address: 0x8
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM1_AZALIA_STREAM_DATA
#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream2_dispdec
// base address: 0x10
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM2_AZALIA_STREAM_DATA
#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream3_dispdec
// base address: 0x18
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM3_AZALIA_STREAM_DATA
#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream4_dispdec
// base address: 0x20
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM4_AZALIA_STREAM_DATA
#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream5_dispdec
// base address: 0x28
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM5_AZALIA_STREAM_DATA
#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream6_dispdec
// base address: 0x30
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM6_AZALIA_STREAM_DATA
#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream7_dispdec
// base address: 0x38
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM7_AZALIA_STREAM_DATA
#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_az_misc_dispdec
// base address: 0x0
#define mmAZ_CLOCK_CNTL
#define mmAZ_CLOCK_CNTL_BASE_IDX


// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
// base address: 0xde8
#define mmDC_PERFMON3_PERFCOUNTER_CNTL
#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON3_PERFCOUNTER_STATE
#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON3_PERFMON_CNTL
#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON3_PERFMON_CNTL2
#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON3_PERFMON_HI
#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON3_PERFMON_LOW
#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
// base address: 0x0
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
// base address: 0x18
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
// base address: 0x30
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
// base address: 0x48
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
// base address: 0x60
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
// base address: 0x78
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
// base address: 0x90
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
// base address: 0xa8
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0controller_dispdec
// base address: 0x0
#define mmAZALIA_CONTROLLER_CLOCK_GATING
#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX
#define mmAZALIA_AUDIO_DTO
#define mmAZALIA_AUDIO_DTO_BASE_IDX
#define mmAZALIA_AUDIO_DTO_CONTROL
#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX
#define mmAZALIA_SOCCLK_CONTROL
#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX
#define mmAZALIA_DATA_DMA_CONTROL
#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX
#define mmAZALIA_BDL_DMA_CONTROL
#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX
#define mmAZALIA_RIRB_AND_DP_CONTROL
#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX
#define mmAZALIA_CORB_DMA_CONTROL
#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX
#define mmAZALIA_CYCLIC_BUFFER_SYNC
#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX
#define mmAZALIA_GLOBAL_CAPABILITIES
#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX
#define mmAZALIA_INPUT_CRC0_CONTROL0
#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX
#define mmAZALIA_INPUT_CRC0_CONTROL1
#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX
#define mmAZALIA_INPUT_CRC0_CONTROL2
#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX
#define mmAZALIA_INPUT_CRC0_CONTROL3
#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX
#define mmAZALIA_INPUT_CRC0_RESULT
#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX
#define mmAZALIA_INPUT_CRC1_CONTROL0
#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX
#define mmAZALIA_INPUT_CRC1_CONTROL1
#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX
#define mmAZALIA_INPUT_CRC1_CONTROL2
#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX
#define mmAZALIA_INPUT_CRC1_CONTROL3
#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX
#define mmAZALIA_INPUT_CRC1_RESULT
#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX
#define mmAZALIA_CRC0_CONTROL0
#define mmAZALIA_CRC0_CONTROL0_BASE_IDX
#define mmAZALIA_CRC0_CONTROL1
#define mmAZALIA_CRC0_CONTROL1_BASE_IDX
#define mmAZALIA_CRC0_CONTROL2
#define mmAZALIA_CRC0_CONTROL2_BASE_IDX
#define mmAZALIA_CRC0_CONTROL3
#define mmAZALIA_CRC0_CONTROL3_BASE_IDX
#define mmAZALIA_CRC0_RESULT
#define mmAZALIA_CRC0_RESULT_BASE_IDX
#define mmAZALIA_CRC1_CONTROL0
#define mmAZALIA_CRC1_CONTROL0_BASE_IDX
#define mmAZALIA_CRC1_CONTROL1
#define mmAZALIA_CRC1_CONTROL1_BASE_IDX
#define mmAZALIA_CRC1_CONTROL2
#define mmAZALIA_CRC1_CONTROL2_BASE_IDX
#define mmAZALIA_CRC1_CONTROL3
#define mmAZALIA_CRC1_CONTROL3_BASE_IDX
#define mmAZALIA_CRC1_RESULT
#define mmAZALIA_CRC1_RESULT_BASE_IDX
#define mmAZALIA_MEM_PWR_CTRL
#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX
#define mmAZALIA_MEM_PWR_STATUS
#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX


// addressBlock: dce_dc_hda_azf0root_dispdec
// base address: 0x0
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX
#define mmAZALIA_F0_GTC_GROUP_OFFSET0
#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX
#define mmAZALIA_F0_GTC_GROUP_OFFSET1
#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX
#define mmAZALIA_F0_GTC_GROUP_OFFSET2
#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX
#define mmAZALIA_F0_GTC_GROUP_OFFSET3
#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX
#define mmAZALIA_F0_GTC_GROUP_OFFSET4
#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX
#define mmAZALIA_F0_GTC_GROUP_OFFSET5
#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX
#define mmAZALIA_F0_GTC_GROUP_OFFSET6
#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream8_dispdec
// base address: 0x320
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM8_AZALIA_STREAM_DATA
#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream9_dispdec
// base address: 0x328
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM9_AZALIA_STREAM_DATA
#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream10_dispdec
// base address: 0x330
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM10_AZALIA_STREAM_DATA
#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream11_dispdec
// base address: 0x338
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM11_AZALIA_STREAM_DATA
#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream12_dispdec
// base address: 0x340
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM12_AZALIA_STREAM_DATA
#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream13_dispdec
// base address: 0x348
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM13_AZALIA_STREAM_DATA
#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream14_dispdec
// base address: 0x350
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM14_AZALIA_STREAM_DATA
#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0stream15_dispdec
// base address: 0x358
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX
#define mmAZF0STREAM15_AZALIA_STREAM_DATA
#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
// base address: 0x0
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
// base address: 0x10
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
// base address: 0x20
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
// base address: 0x30
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
// base address: 0x40
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
// base address: 0x50
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
// base address: 0x60
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
// base address: 0x70
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX


// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
// base address: 0x0
#define mmDCHUBBUB_SDPIF_CFG0
#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX
#define mmVM_REQUEST_PHYSICAL
#define mmVM_REQUEST_PHYSICAL_BASE_IDX
#define mmDCHUBBUB_FORCE_IO_STATUS_0
#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX
#define mmDCHUBBUB_FORCE_IO_STATUS_1
#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX
#define mmDCN_VM_FB_LOCATION_BASE
#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX
#define mmDCN_VM_FB_LOCATION_TOP
#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX
#define mmDCN_VM_FB_OFFSET
#define mmDCN_VM_FB_OFFSET_BASE_IDX
#define mmDCN_VM_AGP_BOT
#define mmDCN_VM_AGP_BOT_BASE_IDX
#define mmDCN_VM_AGP_TOP
#define mmDCN_VM_AGP_TOP_BASE_IDX
#define mmDCN_VM_AGP_BASE
#define mmDCN_VM_AGP_BASE_BASE_IDX
#define mmDCN_VM_LOCAL_HBM_ADDRESS_START
#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX
#define mmDCN_VM_LOCAL_HBM_ADDRESS_END
#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX
#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX
#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL
#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX
#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS
#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX
#define mmDCHUBBUB_SDPIF_CFG1
#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX
#define mmDCHUBBUB_SDPIF_CFG2
#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX


// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
// base address: 0x0
#define mmDCHUBBUB_RET_PATH_DCC_CFG
#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX
#define mmDCHUBBUB_CRC_CTRL
#define mmDCHUBBUB_CRC_CTRL_BASE_IDX
#define mmDCHUBBUB_CRC0_VAL_R_G
#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX
#define mmDCHUBBUB_CRC0_VAL_B_A
#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX
#define mmDCHUBBUB_CRC1_VAL_R_G
#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX
#define mmDCHUBBUB_CRC1_VAL_B_A
#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX


// addressBlock: dce_dc_dchubbub_hubbub_dispdec
// base address: 0x0
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX
#define mmDCHUBBUB_ARB_SAT_LEVEL
#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX
#define mmDCHUBBUB_ARB_QOS_FORCE
#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX
#define mmSURFACE_CHECK0_ADDRESS_LSB
#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX
#define mmSURFACE_CHECK0_ADDRESS_MSB
#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX
#define mmSURFACE_CHECK1_ADDRESS_LSB
#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX
#define mmSURFACE_CHECK1_ADDRESS_MSB
#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX
#define mmSURFACE_CHECK2_ADDRESS_LSB
#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX
#define mmSURFACE_CHECK2_ADDRESS_MSB
#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX
#define mmSURFACE_CHECK3_ADDRESS_LSB
#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX
#define mmSURFACE_CHECK3_ADDRESS_MSB
#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX
#define mmVTG0_CONTROL
#define mmVTG0_CONTROL_BASE_IDX
#define mmVTG1_CONTROL
#define mmVTG1_CONTROL_BASE_IDX
#define mmDCHUBBUB_SOFT_RESET
#define mmDCHUBBUB_SOFT_RESET_BASE_IDX
#define mmDCHUBBUB_CLOCK_CNTL
#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX
#define mmDCFCLK_CNTL
#define mmDCFCLK_CNTL_BASE_IDX
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX
#define mmDCHUBBUB_VLINE_SNAPSHOT
#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX
#define mmDCHUBBUB_CTRL_STATUS
#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX
#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS
#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX
#define mmDCHUBBUB_TEST_DEBUG_INDEX
#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX
#define mmDCHUBBUB_TEST_DEBUG_DATA
#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX
#define mmFMON_CTRL
#define mmFMON_CTRL_BASE_IDX
#define mmFMON_CTRL_1
#define mmFMON_CTRL_1_BASE_IDX


// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
// base address: 0x1534
#define mmDC_PERFMON4_PERFCOUNTER_CNTL
#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON4_PERFCOUNTER_STATE
#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON4_PERFMON_CNTL
#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON4_PERFMON_CNTL2
#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON4_PERFMON_HI
#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON4_PERFMON_LOW
#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
// base address: 0x0
#define mmDCN_VM_CONTEXT0_CNTL
#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT1_CNTL
#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT2_CNTL
#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT3_CNTL
#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT4_CNTL
#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT5_CNTL
#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT6_CNTL
#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT7_CNTL
#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT8_CNTL
#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT9_CNTL
#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT10_CNTL
#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT11_CNTL
#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT12_CNTL
#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT13_CNTL
#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT14_CNTL
#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT15_CNTL
#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX
#define mmDCN_VM_DEFAULT_ADDR_MSB
#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX
#define mmDCN_VM_DEFAULT_ADDR_LSB
#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX
#define mmDCN_VM_FAULT_CNTL
#define mmDCN_VM_FAULT_CNTL_BASE_IDX
#define mmDCN_VM_FAULT_STATUS
#define mmDCN_VM_FAULT_STATUS_BASE_IDX
#define mmDCN_VM_FAULT_ADDR_MSB
#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX
#define mmDCN_VM_FAULT_ADDR_LSB
#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX


// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
// base address: 0x0
#define mmHUBP0_DCSURF_SURFACE_CONFIG
#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX
#define mmHUBP0_DCSURF_ADDR_CONFIG
#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX
#define mmHUBP0_DCSURF_TILING_CONFIG
#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX
#define mmHUBP0_DCHUBP_CNTL
#define mmHUBP0_DCHUBP_CNTL_BASE_IDX
#define mmHUBP0_HUBP_CLK_CNTL
#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX
#define mmHUBP0_DCHUBP_VMPG_CONFIG
#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX
#define mmHUBP0_HUBPREQ_DEBUG_DB
#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX
#define mmHUBP0_HUBPREQ_DEBUG
#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX


// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
// base address: 0x0
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX
#define mmHUBPREQ0_VMID_SETTINGS_0
#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX
#define mmHUBPREQ0_DCN_EXPANSION_MODE
#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX
#define mmHUBPREQ0_DCN_TTU_QOS_WM
#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX
#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL
#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX
#define mmHUBPREQ0_BLANK_OFFSET_0
#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX
#define mmHUBPREQ0_BLANK_OFFSET_1
#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX
#define mmHUBPREQ0_DST_DIMENSIONS
#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX
#define mmHUBPREQ0_DST_AFTER_SCALER
#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX
#define mmHUBPREQ0_PREFETCH_SETTINGS
#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX
#define mmHUBPREQ0_PREFETCH_SETTINGS_C
#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX
#define mmHUBPREQ0_VBLANK_PARAMETERS_0
#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX
#define mmHUBPREQ0_VBLANK_PARAMETERS_1
#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX
#define mmHUBPREQ0_VBLANK_PARAMETERS_2
#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX
#define mmHUBPREQ0_VBLANK_PARAMETERS_3
#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX
#define mmHUBPREQ0_VBLANK_PARAMETERS_4
#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX
#define mmHUBPREQ0_FLIP_PARAMETERS_0
#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX
#define mmHUBPREQ0_FLIP_PARAMETERS_1
#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX
#define mmHUBPREQ0_FLIP_PARAMETERS_2
#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX
#define mmHUBPREQ0_NOM_PARAMETERS_0
#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX
#define mmHUBPREQ0_NOM_PARAMETERS_1
#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX
#define mmHUBPREQ0_NOM_PARAMETERS_2
#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX
#define mmHUBPREQ0_NOM_PARAMETERS_3
#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX
#define mmHUBPREQ0_NOM_PARAMETERS_4
#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX
#define mmHUBPREQ0_NOM_PARAMETERS_5
#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX
#define mmHUBPREQ0_NOM_PARAMETERS_6
#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX
#define mmHUBPREQ0_NOM_PARAMETERS_7
#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX
#define mmHUBPREQ0_PER_LINE_DELIVERY
#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX
#define mmHUBPREQ0_CURSOR_SETTINGS
#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX
#define mmHUBPREQ0_VBLANK_PARAMETERS_5
#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX
#define mmHUBPREQ0_VBLANK_PARAMETERS_6
#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX
#define mmHUBPREQ0_FLIP_PARAMETERS_3
#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX
#define mmHUBPREQ0_FLIP_PARAMETERS_4
#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX
#define mmHUBPREQ0_FLIP_PARAMETERS_5
#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX
#define mmHUBPREQ0_FLIP_PARAMETERS_6
#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX


// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
// base address: 0x0
#define mmHUBPRET0_HUBPRET_CONTROL
#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX
#define mmHUBPRET0_HUBPRET_READ_LINE0
#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX
#define mmHUBPRET0_HUBPRET_READ_LINE1
#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX
#define mmHUBPRET0_HUBPRET_INTERRUPT
#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX


// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
// base address: 0x0
#define mmCURSOR0_0_CURSOR_CONTROL
#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX
#define mmCURSOR0_0_CURSOR_SIZE
#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX
#define mmCURSOR0_0_CURSOR_POSITION
#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX
#define mmCURSOR0_0_CURSOR_HOT_SPOT
#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX
#define mmCURSOR0_0_CURSOR_STEREO_CONTROL
#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX
#define mmCURSOR0_0_CURSOR_DST_OFFSET
#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX
#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL
#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX
#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS
#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX
#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH
#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX
#define mmCURSOR0_0_DMDATA_ADDRESS_LOW
#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX
#define mmCURSOR0_0_DMDATA_CNTL
#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX
#define mmCURSOR0_0_DMDATA_QOS_CNTL
#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX
#define mmCURSOR0_0_DMDATA_STATUS
#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX
#define mmCURSOR0_0_DMDATA_SW_CNTL
#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX
#define mmCURSOR0_0_DMDATA_SW_DATA
#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX


// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x1a74
#define mmDC_PERFMON5_PERFCOUNTER_CNTL
#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON5_PERFCOUNTER_STATE
#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON5_PERFMON_CNTL
#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON5_PERFMON_CNTL2
#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON5_PERFMON_HI
#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON5_PERFMON_LOW
#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
// base address: 0x370
#define mmHUBP1_DCSURF_SURFACE_CONFIG
#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX
#define mmHUBP1_DCSURF_ADDR_CONFIG
#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX
#define mmHUBP1_DCSURF_TILING_CONFIG
#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX
#define mmHUBP1_DCHUBP_CNTL
#define mmHUBP1_DCHUBP_CNTL_BASE_IDX
#define mmHUBP1_HUBP_CLK_CNTL
#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX
#define mmHUBP1_DCHUBP_VMPG_CONFIG
#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX
#define mmHUBP1_HUBPREQ_DEBUG_DB
#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX
#define mmHUBP1_HUBPREQ_DEBUG
#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX


// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
// base address: 0x370
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX
#define mmHUBPREQ1_VMID_SETTINGS_0
#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX
#define mmHUBPREQ1_DCN_EXPANSION_MODE
#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX
#define mmHUBPREQ1_DCN_TTU_QOS_WM
#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX
#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL
#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX
#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL
#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX
#define mmHUBPREQ1_BLANK_OFFSET_0
#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX
#define mmHUBPREQ1_BLANK_OFFSET_1
#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX
#define mmHUBPREQ1_DST_DIMENSIONS
#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX
#define mmHUBPREQ1_DST_AFTER_SCALER
#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX
#define mmHUBPREQ1_PREFETCH_SETTINGS
#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX
#define mmHUBPREQ1_PREFETCH_SETTINGS_C
#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX
#define mmHUBPREQ1_VBLANK_PARAMETERS_0
#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX
#define mmHUBPREQ1_VBLANK_PARAMETERS_1
#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX
#define mmHUBPREQ1_VBLANK_PARAMETERS_2
#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX
#define mmHUBPREQ1_VBLANK_PARAMETERS_3
#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX
#define mmHUBPREQ1_VBLANK_PARAMETERS_4
#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX
#define mmHUBPREQ1_FLIP_PARAMETERS_0
#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX
#define mmHUBPREQ1_FLIP_PARAMETERS_1
#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX
#define mmHUBPREQ1_FLIP_PARAMETERS_2
#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX
#define mmHUBPREQ1_NOM_PARAMETERS_0
#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX
#define mmHUBPREQ1_NOM_PARAMETERS_1
#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX
#define mmHUBPREQ1_NOM_PARAMETERS_2
#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX
#define mmHUBPREQ1_NOM_PARAMETERS_3
#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX
#define mmHUBPREQ1_NOM_PARAMETERS_4
#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX
#define mmHUBPREQ1_NOM_PARAMETERS_5
#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX
#define mmHUBPREQ1_NOM_PARAMETERS_6
#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX
#define mmHUBPREQ1_NOM_PARAMETERS_7
#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX
#define mmHUBPREQ1_PER_LINE_DELIVERY
#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX
#define mmHUBPREQ1_CURSOR_SETTINGS
#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX
#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT
#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX
#define mmHUBPREQ1_VBLANK_PARAMETERS_5
#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX
#define mmHUBPREQ1_VBLANK_PARAMETERS_6
#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX
#define mmHUBPREQ1_FLIP_PARAMETERS_3
#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX
#define mmHUBPREQ1_FLIP_PARAMETERS_4
#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX
#define mmHUBPREQ1_FLIP_PARAMETERS_5
#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX
#define mmHUBPREQ1_FLIP_PARAMETERS_6
#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX


// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
// base address: 0x370
#define mmHUBPRET1_HUBPRET_CONTROL
#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX
#define mmHUBPRET1_HUBPRET_READ_LINE0
#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX
#define mmHUBPRET1_HUBPRET_READ_LINE1
#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX
#define mmHUBPRET1_HUBPRET_INTERRUPT
#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX


// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
// base address: 0x370
#define mmCURSOR0_1_CURSOR_CONTROL
#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX
#define mmCURSOR0_1_CURSOR_SIZE
#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX
#define mmCURSOR0_1_CURSOR_POSITION
#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX
#define mmCURSOR0_1_CURSOR_HOT_SPOT
#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX
#define mmCURSOR0_1_CURSOR_STEREO_CONTROL
#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX
#define mmCURSOR0_1_CURSOR_DST_OFFSET
#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX
#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL
#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX
#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS
#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX
#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH
#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX
#define mmCURSOR0_1_DMDATA_ADDRESS_LOW
#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX
#define mmCURSOR0_1_DMDATA_CNTL
#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX
#define mmCURSOR0_1_DMDATA_QOS_CNTL
#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX
#define mmCURSOR0_1_DMDATA_STATUS
#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX
#define mmCURSOR0_1_DMDATA_SW_CNTL
#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX
#define mmCURSOR0_1_DMDATA_SW_DATA
#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX


// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x1de4
#define mmDC_PERFMON6_PERFCOUNTER_CNTL
#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON6_PERFCOUNTER_STATE
#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON6_PERFMON_CNTL
#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON6_PERFMON_CNTL2
#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON6_PERFMON_HI
#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON6_PERFMON_LOW
#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
// base address: 0x0
#define mmDPP_TOP0_DPP_CONTROL
#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX
#define mmDPP_TOP0_DPP_SOFT_RESET
#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX
#define mmDPP_TOP0_DPP_CRC_VAL_R_G
#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX
#define mmDPP_TOP0_DPP_CRC_VAL_B_A
#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX
#define mmDPP_TOP0_DPP_CRC_CTRL
#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX
#define mmDPP_TOP0_HOST_READ_CONTROL
#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX


// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
// base address: 0x0
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX
#define mmCNVC_CFG0_FORMAT_CONTROL
#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX
#define mmCNVC_CFG0_FCNV_FP_BIAS_R
#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX
#define mmCNVC_CFG0_FCNV_FP_BIAS_G
#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX
#define mmCNVC_CFG0_FCNV_FP_BIAS_B
#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX
#define mmCNVC_CFG0_FCNV_FP_SCALE_R
#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX
#define mmCNVC_CFG0_FCNV_FP_SCALE_G
#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX
#define mmCNVC_CFG0_FCNV_FP_SCALE_B
#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX
#define mmCNVC_CFG0_COLOR_KEYER_CONTROL
#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX
#define mmCNVC_CFG0_COLOR_KEYER_RED
#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX
#define mmCNVC_CFG0_COLOR_KEYER_GREEN
#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX
#define mmCNVC_CFG0_COLOR_KEYER_BLUE
#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX
#define mmCNVC_CFG0_ALPHA_2BIT_LUT
#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX
#define mmCNVC_CFG0_PRE_DEALPHA
#define mmCNVC_CFG0_PRE_DEALPHA_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_MODE
#define mmCNVC_CFG0_PRE_CSC_MODE_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_C11_C12
#define mmCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_C13_C14
#define mmCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_C21_C22
#define mmCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_C23_C24
#define mmCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_C31_C32
#define mmCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_C33_C34
#define mmCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_B_C11_C12
#define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_B_C13_C14
#define mmCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_B_C21_C22
#define mmCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_B_C23_C24
#define mmCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_B_C31_C32
#define mmCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX
#define mmCNVC_CFG0_PRE_CSC_B_C33_C34
#define mmCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX
#define mmCNVC_CFG0_CNVC_COEF_FORMAT
#define mmCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX
#define mmCNVC_CFG0_PRE_DEGAM
#define mmCNVC_CFG0_PRE_DEGAM_BASE_IDX
#define mmCNVC_CFG0_PRE_REALPHA
#define mmCNVC_CFG0_PRE_REALPHA_BASE_IDX


// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
// base address: 0x0
#define mmCNVC_CUR0_CURSOR0_CONTROL
#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX
#define mmCNVC_CUR0_CURSOR0_COLOR0
#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX
#define mmCNVC_CUR0_CURSOR0_COLOR1
#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX
#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS
#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX


// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
// base address: 0x0
#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT
#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX
#define mmDSCL0_SCL_COEF_RAM_TAP_DATA
#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX
#define mmDSCL0_SCL_MODE
#define mmDSCL0_SCL_MODE_BASE_IDX
#define mmDSCL0_SCL_TAP_CONTROL
#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX
#define mmDSCL0_DSCL_CONTROL
#define mmDSCL0_DSCL_CONTROL_BASE_IDX
#define mmDSCL0_DSCL_2TAP_CONTROL
#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX
#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL
#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX
#define mmDSCL0_SCL_HORZ_FILTER_INIT
#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX
#define mmDSCL0_SCL_HORZ_FILTER_INIT_C
#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX
#define mmDSCL0_SCL_VERT_FILTER_INIT
#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX
#define mmDSCL0_SCL_VERT_FILTER_INIT_C
#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX
#define mmDSCL0_SCL_BLACK_COLOR
#define mmDSCL0_SCL_BLACK_COLOR_BASE_IDX
#define mmDSCL0_DSCL_UPDATE
#define mmDSCL0_DSCL_UPDATE_BASE_IDX
#define mmDSCL0_DSCL_AUTOCAL
#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX
#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT
#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX
#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM
#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX
#define mmDSCL0_OTG_H_BLANK
#define mmDSCL0_OTG_H_BLANK_BASE_IDX
#define mmDSCL0_OTG_V_BLANK
#define mmDSCL0_OTG_V_BLANK_BASE_IDX
#define mmDSCL0_RECOUT_START
#define mmDSCL0_RECOUT_START_BASE_IDX
#define mmDSCL0_RECOUT_SIZE
#define mmDSCL0_RECOUT_SIZE_BASE_IDX
#define mmDSCL0_MPC_SIZE
#define mmDSCL0_MPC_SIZE_BASE_IDX
#define mmDSCL0_LB_DATA_FORMAT
#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX
#define mmDSCL0_LB_MEMORY_CTRL
#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX
#define mmDSCL0_LB_V_COUNTER
#define mmDSCL0_LB_V_COUNTER_BASE_IDX
#define mmDSCL0_DSCL_MEM_PWR_CTRL
#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX
#define mmDSCL0_DSCL_MEM_PWR_STATUS
#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX
#define mmDSCL0_OBUF_CONTROL
#define mmDSCL0_OBUF_CONTROL_BASE_IDX
#define mmDSCL0_OBUF_MEM_PWR_CTRL
#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX


// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
// base address: 0x0
#define mmCM0_CM_CONTROL
#define mmCM0_CM_CONTROL_BASE_IDX
#define mmCM0_CM_POST_CSC_CONTROL
#define mmCM0_CM_POST_CSC_CONTROL_BASE_IDX
#define mmCM0_CM_POST_CSC_C11_C12
#define mmCM0_CM_POST_CSC_C11_C12_BASE_IDX
#define mmCM0_CM_POST_CSC_C13_C14
#define mmCM0_CM_POST_CSC_C13_C14_BASE_IDX
#define mmCM0_CM_POST_CSC_C21_C22
#define mmCM0_CM_POST_CSC_C21_C22_BASE_IDX
#define mmCM0_CM_POST_CSC_C23_C24
#define mmCM0_CM_POST_CSC_C23_C24_BASE_IDX
#define mmCM0_CM_POST_CSC_C31_C32
#define mmCM0_CM_POST_CSC_C31_C32_BASE_IDX
#define mmCM0_CM_POST_CSC_C33_C34
#define mmCM0_CM_POST_CSC_C33_C34_BASE_IDX
#define mmCM0_CM_POST_CSC_B_C11_C12
#define mmCM0_CM_POST_CSC_B_C11_C12_BASE_IDX
#define mmCM0_CM_POST_CSC_B_C13_C14
#define mmCM0_CM_POST_CSC_B_C13_C14_BASE_IDX
#define mmCM0_CM_POST_CSC_B_C21_C22
#define mmCM0_CM_POST_CSC_B_C21_C22_BASE_IDX
#define mmCM0_CM_POST_CSC_B_C23_C24
#define mmCM0_CM_POST_CSC_B_C23_C24_BASE_IDX
#define mmCM0_CM_POST_CSC_B_C31_C32
#define mmCM0_CM_POST_CSC_B_C31_C32_BASE_IDX
#define mmCM0_CM_POST_CSC_B_C33_C34
#define mmCM0_CM_POST_CSC_B_C33_C34_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_CONTROL
#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_C11_C12
#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_C13_C14
#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_C21_C22
#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_C23_C24
#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_C31_C32
#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_C33_C34
#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_B_C11_C12
#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_B_C13_C14
#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_B_C21_C22
#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_B_C23_C24
#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_B_C31_C32
#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX
#define mmCM0_CM_GAMUT_REMAP_B_C33_C34
#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX
#define mmCM0_CM_BIAS_CR_R
#define mmCM0_CM_BIAS_CR_R_BASE_IDX
#define mmCM0_CM_BIAS_Y_G_CB_B
#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX
#define mmCM0_CM_GAMCOR_CONTROL
#define mmCM0_CM_GAMCOR_CONTROL_BASE_IDX
#define mmCM0_CM_GAMCOR_LUT_INDEX
#define mmCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX
#define mmCM0_CM_GAMCOR_LUT_DATA
#define mmCM0_CM_GAMCOR_LUT_DATA_BASE_IDX
#define mmCM0_CM_GAMCOR_LUT_CONTROL
#define mmCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1
#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3
#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5
#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7
#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9
#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11
#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13
#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15
#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17
#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19
#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21
#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23
#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25
#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27
#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29
#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31
#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33
#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1
#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3
#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5
#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7
#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9
#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11
#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13
#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15
#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17
#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19
#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21
#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23
#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25
#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27
#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29
#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31
#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX
#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33
#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX
#define mmCM0_CM_BLNDGAM_CONTROL
#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX
#define mmCM0_CM_BLNDGAM_LUT_INDEX
#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX
#define mmCM0_CM_BLNDGAM_LUT_DATA
#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX
#define mmCM0_CM_BLNDGAM_LUT_CONTROL
#define mmCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1
#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3
#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5
#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7
#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9
#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11
#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13
#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15
#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17
#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19
#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21
#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23
#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25
#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27
#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29
#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31
#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33
#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1
#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3
#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5
#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7
#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9
#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11
#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13
#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15
#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17
#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19
#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21
#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23
#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25
#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27
#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29
#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31
#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX
#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33
#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX
#define mmCM0_CM_HDR_MULT_COEF
#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX
#define mmCM0_CM_MEM_PWR_CTRL
#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX
#define mmCM0_CM_MEM_PWR_STATUS
#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX
#define mmCM0_CM_DEALPHA
#define mmCM0_CM_DEALPHA_BASE_IDX
#define mmCM0_CM_COEF_FORMAT
#define mmCM0_CM_COEF_FORMAT_BASE_IDX
#define mmCM0_CM_SHAPER_CONTROL
#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX
#define mmCM0_CM_SHAPER_OFFSET_R
#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX
#define mmCM0_CM_SHAPER_OFFSET_G
#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX
#define mmCM0_CM_SHAPER_OFFSET_B
#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX
#define mmCM0_CM_SHAPER_SCALE_R
#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX
#define mmCM0_CM_SHAPER_SCALE_G_B
#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX
#define mmCM0_CM_SHAPER_LUT_INDEX
#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX
#define mmCM0_CM_SHAPER_LUT_DATA
#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX
#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK
#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_0_1
#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_2_3
#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_4_5
#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_6_7
#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_8_9
#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_10_11
#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_12_13
#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_14_15
#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_16_17
#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_18_19
#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_20_21
#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_22_23
#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_24_25
#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_26_27
#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_28_29
#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_30_31
#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX
#define mmCM0_CM_SHAPER_RAMA_REGION_32_33
#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_0_1
#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_2_3
#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_4_5
#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_6_7
#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_8_9
#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_10_11
#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_12_13
#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_14_15
#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_16_17
#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_18_19
#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_20_21
#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_22_23
#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_24_25
#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_26_27
#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_28_29
#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_30_31
#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX
#define mmCM0_CM_SHAPER_RAMB_REGION_32_33
#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX
#define mmCM0_CM_MEM_PWR_CTRL2
#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX
#define mmCM0_CM_MEM_PWR_STATUS2
#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX
#define mmCM0_CM_3DLUT_MODE
#define mmCM0_CM_3DLUT_MODE_BASE_IDX
#define mmCM0_CM_3DLUT_INDEX
#define mmCM0_CM_3DLUT_INDEX_BASE_IDX
#define mmCM0_CM_3DLUT_DATA
#define mmCM0_CM_3DLUT_DATA_BASE_IDX
#define mmCM0_CM_3DLUT_DATA_30BIT
#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX
#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL
#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX
#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR
#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX
#define mmCM0_CM_3DLUT_OUT_OFFSET_R
#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX
#define mmCM0_CM_3DLUT_OUT_OFFSET_G
#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX
#define mmCM0_CM_3DLUT_OUT_OFFSET_B
#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX
#define mmCM0_CM_TEST_DEBUG_INDEX
#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX
#define mmCM0_CM_TEST_DEBUG_DATA
#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX


// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x3890
#define mmDC_PERFMON7_PERFCOUNTER_CNTL
#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON7_PERFCOUNTER_STATE
#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON7_PERFMON_CNTL
#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON7_PERFMON_CNTL2
#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON7_PERFMON_HI
#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON7_PERFMON_LOW
#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
// base address: 0x5ac
#define mmDPP_TOP1_DPP_CONTROL
#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX
#define mmDPP_TOP1_DPP_SOFT_RESET
#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX
#define mmDPP_TOP1_DPP_CRC_VAL_R_G
#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX
#define mmDPP_TOP1_DPP_CRC_VAL_B_A
#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX
#define mmDPP_TOP1_DPP_CRC_CTRL
#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX
#define mmDPP_TOP1_HOST_READ_CONTROL
#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX


// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
// base address: 0x5ac
#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT
#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX
#define mmCNVC_CFG1_FORMAT_CONTROL
#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX
#define mmCNVC_CFG1_FCNV_FP_BIAS_R
#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX
#define mmCNVC_CFG1_FCNV_FP_BIAS_G
#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX
#define mmCNVC_CFG1_FCNV_FP_BIAS_B
#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX
#define mmCNVC_CFG1_FCNV_FP_SCALE_R
#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX
#define mmCNVC_CFG1_FCNV_FP_SCALE_G
#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX
#define mmCNVC_CFG1_FCNV_FP_SCALE_B
#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX
#define mmCNVC_CFG1_COLOR_KEYER_CONTROL
#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX
#define mmCNVC_CFG1_COLOR_KEYER_ALPHA
#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX
#define mmCNVC_CFG1_COLOR_KEYER_RED
#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX
#define mmCNVC_CFG1_COLOR_KEYER_GREEN
#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX
#define mmCNVC_CFG1_COLOR_KEYER_BLUE
#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX
#define mmCNVC_CFG1_ALPHA_2BIT_LUT
#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX
#define mmCNVC_CFG1_PRE_DEALPHA
#define mmCNVC_CFG1_PRE_DEALPHA_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_MODE
#define mmCNVC_CFG1_PRE_CSC_MODE_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_C11_C12
#define mmCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_C13_C14
#define mmCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_C21_C22
#define mmCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_C23_C24
#define mmCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_C31_C32
#define mmCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_C33_C34
#define mmCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_B_C11_C12
#define mmCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_B_C13_C14
#define mmCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_B_C21_C22
#define mmCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_B_C23_C24
#define mmCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_B_C31_C32
#define mmCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX
#define mmCNVC_CFG1_PRE_CSC_B_C33_C34
#define mmCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX
#define mmCNVC_CFG1_CNVC_COEF_FORMAT
#define mmCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX
#define mmCNVC_CFG1_PRE_DEGAM
#define mmCNVC_CFG1_PRE_DEGAM_BASE_IDX
#define mmCNVC_CFG1_PRE_REALPHA
#define mmCNVC_CFG1_PRE_REALPHA_BASE_IDX


// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
// base address: 0x5ac
#define mmCNVC_CUR1_CURSOR0_CONTROL
#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX
#define mmCNVC_CUR1_CURSOR0_COLOR0
#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX
#define mmCNVC_CUR1_CURSOR0_COLOR1
#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX
#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS
#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX


// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
// base address: 0x5ac
#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT
#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX
#define mmDSCL1_SCL_COEF_RAM_TAP_DATA
#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX
#define mmDSCL1_SCL_MODE
#define mmDSCL1_SCL_MODE_BASE_IDX
#define mmDSCL1_SCL_TAP_CONTROL
#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX
#define mmDSCL1_DSCL_CONTROL
#define mmDSCL1_DSCL_CONTROL_BASE_IDX
#define mmDSCL1_DSCL_2TAP_CONTROL
#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX
#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL
#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX
#define mmDSCL1_SCL_HORZ_FILTER_INIT
#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX
#define mmDSCL1_SCL_HORZ_FILTER_INIT_C
#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX
#define mmDSCL1_SCL_VERT_FILTER_INIT
#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX
#define mmDSCL1_SCL_VERT_FILTER_INIT_C
#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX
#define mmDSCL1_SCL_BLACK_COLOR
#define mmDSCL1_SCL_BLACK_COLOR_BASE_IDX
#define mmDSCL1_DSCL_UPDATE
#define mmDSCL1_DSCL_UPDATE_BASE_IDX
#define mmDSCL1_DSCL_AUTOCAL
#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX
#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT
#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX
#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM
#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX
#define mmDSCL1_OTG_H_BLANK
#define mmDSCL1_OTG_H_BLANK_BASE_IDX
#define mmDSCL1_OTG_V_BLANK
#define mmDSCL1_OTG_V_BLANK_BASE_IDX
#define mmDSCL1_RECOUT_START
#define mmDSCL1_RECOUT_START_BASE_IDX
#define mmDSCL1_RECOUT_SIZE
#define mmDSCL1_RECOUT_SIZE_BASE_IDX
#define mmDSCL1_MPC_SIZE
#define mmDSCL1_MPC_SIZE_BASE_IDX
#define mmDSCL1_LB_DATA_FORMAT
#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX
#define mmDSCL1_LB_MEMORY_CTRL
#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX
#define mmDSCL1_LB_V_COUNTER
#define mmDSCL1_LB_V_COUNTER_BASE_IDX
#define mmDSCL1_DSCL_MEM_PWR_CTRL
#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX
#define mmDSCL1_DSCL_MEM_PWR_STATUS
#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX
#define mmDSCL1_OBUF_CONTROL
#define mmDSCL1_OBUF_CONTROL_BASE_IDX
#define mmDSCL1_OBUF_MEM_PWR_CTRL
#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX


// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
// base address: 0x5ac
#define mmCM1_CM_CONTROL
#define mmCM1_CM_CONTROL_BASE_IDX
#define mmCM1_CM_POST_CSC_CONTROL
#define mmCM1_CM_POST_CSC_CONTROL_BASE_IDX
#define mmCM1_CM_POST_CSC_C11_C12
#define mmCM1_CM_POST_CSC_C11_C12_BASE_IDX
#define mmCM1_CM_POST_CSC_C13_C14
#define mmCM1_CM_POST_CSC_C13_C14_BASE_IDX
#define mmCM1_CM_POST_CSC_C21_C22
#define mmCM1_CM_POST_CSC_C21_C22_BASE_IDX
#define mmCM1_CM_POST_CSC_C23_C24
#define mmCM1_CM_POST_CSC_C23_C24_BASE_IDX
#define mmCM1_CM_POST_CSC_C31_C32
#define mmCM1_CM_POST_CSC_C31_C32_BASE_IDX
#define mmCM1_CM_POST_CSC_C33_C34
#define mmCM1_CM_POST_CSC_C33_C34_BASE_IDX
#define mmCM1_CM_POST_CSC_B_C11_C12
#define mmCM1_CM_POST_CSC_B_C11_C12_BASE_IDX
#define mmCM1_CM_POST_CSC_B_C13_C14
#define mmCM1_CM_POST_CSC_B_C13_C14_BASE_IDX
#define mmCM1_CM_POST_CSC_B_C21_C22
#define mmCM1_CM_POST_CSC_B_C21_C22_BASE_IDX
#define mmCM1_CM_POST_CSC_B_C23_C24
#define mmCM1_CM_POST_CSC_B_C23_C24_BASE_IDX
#define mmCM1_CM_POST_CSC_B_C31_C32
#define mmCM1_CM_POST_CSC_B_C31_C32_BASE_IDX
#define mmCM1_CM_POST_CSC_B_C33_C34
#define mmCM1_CM_POST_CSC_B_C33_C34_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_CONTROL
#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_C11_C12
#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_C13_C14
#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_C21_C22
#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_C23_C24
#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_C31_C32
#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_C33_C34
#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_B_C11_C12
#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_B_C13_C14
#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_B_C21_C22
#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_B_C23_C24
#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_B_C31_C32
#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX
#define mmCM1_CM_GAMUT_REMAP_B_C33_C34
#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX
#define mmCM1_CM_BIAS_CR_R
#define mmCM1_CM_BIAS_CR_R_BASE_IDX
#define mmCM1_CM_BIAS_Y_G_CB_B
#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX
#define mmCM1_CM_GAMCOR_CONTROL
#define mmCM1_CM_GAMCOR_CONTROL_BASE_IDX
#define mmCM1_CM_GAMCOR_LUT_INDEX
#define mmCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX
#define mmCM1_CM_GAMCOR_LUT_DATA
#define mmCM1_CM_GAMCOR_LUT_DATA_BASE_IDX
#define mmCM1_CM_GAMCOR_LUT_CONTROL
#define mmCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1
#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3
#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5
#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7
#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9
#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11
#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13
#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15
#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17
#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19
#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21
#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23
#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25
#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27
#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29
#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31
#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33
#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1
#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3
#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5
#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7
#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9
#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11
#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13
#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15
#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17
#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19
#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21
#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23
#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25
#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27
#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29
#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31
#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX
#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33
#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX
#define mmCM1_CM_BLNDGAM_CONTROL
#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX
#define mmCM1_CM_BLNDGAM_LUT_INDEX
#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX
#define mmCM1_CM_BLNDGAM_LUT_DATA
#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX
#define mmCM1_CM_BLNDGAM_LUT_CONTROL
#define mmCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1
#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3
#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5
#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7
#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9
#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11
#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13
#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15
#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17
#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19
#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21
#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23
#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25
#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27
#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29
#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31
#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33
#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1
#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3
#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5
#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7
#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9
#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11
#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13
#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15
#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17
#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19
#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21
#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23
#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25
#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27
#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29
#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31
#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX
#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33
#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX
#define mmCM1_CM_HDR_MULT_COEF
#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX
#define mmCM1_CM_MEM_PWR_CTRL
#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX
#define mmCM1_CM_MEM_PWR_STATUS
#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX
#define mmCM1_CM_DEALPHA
#define mmCM1_CM_DEALPHA_BASE_IDX
#define mmCM1_CM_COEF_FORMAT
#define mmCM1_CM_COEF_FORMAT_BASE_IDX
#define mmCM1_CM_SHAPER_CONTROL
#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX
#define mmCM1_CM_SHAPER_OFFSET_R
#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX
#define mmCM1_CM_SHAPER_OFFSET_G
#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX
#define mmCM1_CM_SHAPER_OFFSET_B
#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX
#define mmCM1_CM_SHAPER_SCALE_R
#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX
#define mmCM1_CM_SHAPER_SCALE_G_B
#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX
#define mmCM1_CM_SHAPER_LUT_INDEX
#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX
#define mmCM1_CM_SHAPER_LUT_DATA
#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX
#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK
#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_0_1
#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_2_3
#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_4_5
#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_6_7
#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_8_9
#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_10_11
#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_12_13
#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_14_15
#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_16_17
#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_18_19
#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_20_21
#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_22_23
#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_24_25
#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_26_27
#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_28_29
#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_30_31
#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX
#define mmCM1_CM_SHAPER_RAMA_REGION_32_33
#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_0_1
#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_2_3
#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_4_5
#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_6_7
#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_8_9
#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_10_11
#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_12_13
#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_14_15
#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_16_17
#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_18_19
#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_20_21
#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_22_23
#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_24_25
#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_26_27
#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_28_29
#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_30_31
#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX
#define mmCM1_CM_SHAPER_RAMB_REGION_32_33
#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX
#define mmCM1_CM_MEM_PWR_CTRL2
#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX
#define mmCM1_CM_MEM_PWR_STATUS2
#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX
#define mmCM1_CM_3DLUT_MODE
#define mmCM1_CM_3DLUT_MODE_BASE_IDX
#define mmCM1_CM_3DLUT_INDEX
#define mmCM1_CM_3DLUT_INDEX_BASE_IDX
#define mmCM1_CM_3DLUT_DATA
#define mmCM1_CM_3DLUT_DATA_BASE_IDX
#define mmCM1_CM_3DLUT_DATA_30BIT
#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX
#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL
#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX
#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR
#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX
#define mmCM1_CM_3DLUT_OUT_OFFSET_R
#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX
#define mmCM1_CM_3DLUT_OUT_OFFSET_G
#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX
#define mmCM1_CM_3DLUT_OUT_OFFSET_B
#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX
#define mmCM1_CM_TEST_DEBUG_INDEX
#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX
#define mmCM1_CM_TEST_DEBUG_DATA
#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX


// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x3e3c
#define mmDC_PERFMON8_PERFCOUNTER_CNTL
#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON8_PERFCOUNTER_CNTL2
#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON8_PERFCOUNTER_STATE
#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON8_PERFMON_CNTL
#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON8_PERFMON_CNTL2
#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON8_PERFMON_HI
#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON8_PERFMON_LOW
#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_opp_fmt0_dispdec
// base address: 0x0
#define mmFMT0_FMT_CLAMP_COMPONENT_R
#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX
#define mmFMT0_FMT_CLAMP_COMPONENT_G
#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX
#define mmFMT0_FMT_CLAMP_COMPONENT_B
#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX
#define mmFMT0_FMT_CONTROL
#define mmFMT0_FMT_CONTROL_BASE_IDX
#define mmFMT0_FMT_BIT_DEPTH_CONTROL
#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX
#define mmFMT0_FMT_DITHER_RAND_R_SEED
#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX
#define mmFMT0_FMT_DITHER_RAND_G_SEED
#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX
#define mmFMT0_FMT_DITHER_RAND_B_SEED
#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX
#define mmFMT0_FMT_CLAMP_CNTL
#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX
#define mmFMT0_FMT_422_CONTROL
#define mmFMT0_FMT_422_CONTROL_BASE_IDX


// addressBlock: dce_dc_opp_dpg0_dispdec
// base address: 0x0
#define mmDPG0_DPG_CONTROL
#define mmDPG0_DPG_CONTROL_BASE_IDX
#define mmDPG0_DPG_RAMP_CONTROL
#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX
#define mmDPG0_DPG_DIMENSIONS
#define mmDPG0_DPG_DIMENSIONS_BASE_IDX
#define mmDPG0_DPG_COLOUR_R_CR
#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX
#define mmDPG0_DPG_COLOUR_G_Y
#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX
#define mmDPG0_DPG_COLOUR_B_CB
#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX
#define mmDPG0_DPG_OFFSET_SEGMENT
#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX
#define mmDPG0_DPG_STATUS
#define mmDPG0_DPG_STATUS_BASE_IDX


// addressBlock: dce_dc_opp_oppbuf0_dispdec
// base address: 0x0
#define mmOPPBUF0_OPPBUF_CONTROL
#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX
#define mmOPPBUF0_OPPBUF_CONTROL1
#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX


// addressBlock: dce_dc_opp_opp_pipe0_dispdec
// base address: 0x0
#define mmOPP_PIPE0_OPP_PIPE_CONTROL
#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX


// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
// base address: 0x0
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX


// addressBlock: dce_dc_opp_fmt1_dispdec
// base address: 0x168
#define mmFMT1_FMT_CLAMP_COMPONENT_R
#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX
#define mmFMT1_FMT_CLAMP_COMPONENT_G
#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX
#define mmFMT1_FMT_CLAMP_COMPONENT_B
#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX
#define mmFMT1_FMT_CONTROL
#define mmFMT1_FMT_CONTROL_BASE_IDX
#define mmFMT1_FMT_BIT_DEPTH_CONTROL
#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX
#define mmFMT1_FMT_DITHER_RAND_R_SEED
#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX
#define mmFMT1_FMT_DITHER_RAND_G_SEED
#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX
#define mmFMT1_FMT_DITHER_RAND_B_SEED
#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX
#define mmFMT1_FMT_CLAMP_CNTL
#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX
#define mmFMT1_FMT_422_CONTROL
#define mmFMT1_FMT_422_CONTROL_BASE_IDX


// addressBlock: dce_dc_opp_dpg1_dispdec
// base address: 0x168
#define mmDPG1_DPG_CONTROL
#define mmDPG1_DPG_CONTROL_BASE_IDX
#define mmDPG1_DPG_RAMP_CONTROL
#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX
#define mmDPG1_DPG_DIMENSIONS
#define mmDPG1_DPG_DIMENSIONS_BASE_IDX
#define mmDPG1_DPG_COLOUR_R_CR
#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX
#define mmDPG1_DPG_COLOUR_G_Y
#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX
#define mmDPG1_DPG_COLOUR_B_CB
#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX
#define mmDPG1_DPG_OFFSET_SEGMENT
#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX
#define mmDPG1_DPG_STATUS
#define mmDPG1_DPG_STATUS_BASE_IDX


// addressBlock: dce_dc_opp_oppbuf1_dispdec
// base address: 0x168
#define mmOPPBUF1_OPPBUF_CONTROL
#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX
#define mmOPPBUF1_OPPBUF_CONTROL1
#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX


// addressBlock: dce_dc_opp_opp_pipe1_dispdec
// base address: 0x168
#define mmOPP_PIPE1_OPP_PIPE_CONTROL
#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX


// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
// base address: 0x168
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX


// addressBlock: dce_dc_opp_opp_top_dispdec
// base address: 0x0
#define mmOPP_TOP_CLK_CONTROL
#define mmOPP_TOP_CLK_CONTROL_BASE_IDX
#define mmOPP_ABM_CONTROL
#define mmOPP_ABM_CONTROL_BASE_IDX


// addressBlock: dce_dc_opp_dscrm0_dispdec
// base address: 0x0
#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG
#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX


// addressBlock: dce_dc_opp_dscrm1_dispdec
// base address: 0x4
#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG
#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX


// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
// base address: 0x6af8
#define mmDC_PERFMON9_PERFCOUNTER_CNTL
#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON9_PERFCOUNTER_STATE
#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON9_PERFMON_CNTL
#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON9_PERFMON_CNTL2
#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON9_PERFMON_HI
#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON9_PERFMON_LOW
#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_optc_odm0_dispdec
// base address: 0x0
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX
#define mmODM0_OPTC_DATA_SOURCE_SELECT
#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX
#define mmODM0_OPTC_DATA_FORMAT_CONTROL
#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX
#define mmODM0_OPTC_BYTES_PER_PIXEL
#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX
#define mmODM0_OPTC_WIDTH_CONTROL
#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX
#define mmODM0_OPTC_MEMORY_CONFIG
#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX
#define mmODM0_OPTC_INPUT_SPARE_REGISTER
#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX


// addressBlock: dce_dc_optc_odm1_dispdec
// base address: 0x40
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX
#define mmODM1_OPTC_DATA_SOURCE_SELECT
#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX
#define mmODM1_OPTC_DATA_FORMAT_CONTROL
#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX
#define mmODM1_OPTC_BYTES_PER_PIXEL
#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX
#define mmODM1_OPTC_WIDTH_CONTROL
#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX
#define mmODM1_OPTC_INPUT_CLOCK_CONTROL
#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX
#define mmODM1_OPTC_MEMORY_CONFIG
#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX
#define mmODM1_OPTC_INPUT_SPARE_REGISTER
#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX


// addressBlock: dce_dc_optc_otg0_dispdec
// base address: 0x0
#define mmOTG0_OTG_H_TOTAL
#define mmOTG0_OTG_H_TOTAL_BASE_IDX
#define mmOTG0_OTG_H_BLANK_START_END
#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX
#define mmOTG0_OTG_H_SYNC_A
#define mmOTG0_OTG_H_SYNC_A_BASE_IDX
#define mmOTG0_OTG_H_SYNC_A_CNTL
#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX
#define mmOTG0_OTG_H_TIMING_CNTL
#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX
#define mmOTG0_OTG_V_TOTAL
#define mmOTG0_OTG_V_TOTAL_BASE_IDX
#define mmOTG0_OTG_V_TOTAL_MIN
#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX
#define mmOTG0_OTG_V_TOTAL_MAX
#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX
#define mmOTG0_OTG_V_TOTAL_MID
#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX
#define mmOTG0_OTG_V_TOTAL_CONTROL
#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX
#define mmOTG0_OTG_V_TOTAL_INT_STATUS
#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX
#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS
#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX
#define mmOTG0_OTG_V_BLANK_START_END
#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX
#define mmOTG0_OTG_V_SYNC_A
#define mmOTG0_OTG_V_SYNC_A_BASE_IDX
#define mmOTG0_OTG_V_SYNC_A_CNTL
#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX
#define mmOTG0_OTG_TRIGA_CNTL
#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX
#define mmOTG0_OTG_TRIGA_MANUAL_TRIG
#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX
#define mmOTG0_OTG_TRIGB_CNTL
#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX
#define mmOTG0_OTG_TRIGB_MANUAL_TRIG
#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX
#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL
#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX
#define mmOTG0_OTG_FLOW_CONTROL
#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX
#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE
#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX
#define mmOTG0_OTG_CONTROL
#define mmOTG0_OTG_CONTROL_BASE_IDX
#define mmOTG0_OTG_INTERLACE_CONTROL
#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX
#define mmOTG0_OTG_INTERLACE_STATUS
#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX
#define mmOTG0_OTG_PIXEL_DATA_READBACK0
#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX
#define mmOTG0_OTG_PIXEL_DATA_READBACK1
#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX
#define mmOTG0_OTG_STATUS
#define mmOTG0_OTG_STATUS_BASE_IDX
#define mmOTG0_OTG_STATUS_POSITION
#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX
#define mmOTG0_OTG_NOM_VERT_POSITION
#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX
#define mmOTG0_OTG_STATUS_FRAME_COUNT
#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX
#define mmOTG0_OTG_STATUS_VF_COUNT
#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX
#define mmOTG0_OTG_STATUS_HV_COUNT
#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX
#define mmOTG0_OTG_COUNT_CONTROL
#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX
#define mmOTG0_OTG_COUNT_RESET
#define mmOTG0_OTG_COUNT_RESET_BASE_IDX
#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX
#define mmOTG0_OTG_VERT_SYNC_CONTROL
#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX
#define mmOTG0_OTG_STEREO_STATUS
#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX
#define mmOTG0_OTG_STEREO_CONTROL
#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX
#define mmOTG0_OTG_SNAPSHOT_STATUS
#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX
#define mmOTG0_OTG_SNAPSHOT_CONTROL
#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX
#define mmOTG0_OTG_SNAPSHOT_POSITION
#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX
#define mmOTG0_OTG_SNAPSHOT_FRAME
#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX
#define mmOTG0_OTG_INTERRUPT_CONTROL
#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX
#define mmOTG0_OTG_UPDATE_LOCK
#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX
#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL
#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX
#define mmOTG0_OTG_MASTER_EN
#define mmOTG0_OTG_MASTER_EN_BASE_IDX
#define mmOTG0_OTG_BLANK_DATA_COLOR
#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX
#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT
#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX
#define mmOTG0_OTG_CRC_CNTL
#define mmOTG0_OTG_CRC_CNTL_BASE_IDX
#define mmOTG0_OTG_CRC_CNTL2
#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX
#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL
#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX
#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL
#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX
#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL
#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX
#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL
#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX
#define mmOTG0_OTG_CRC0_DATA_RG
#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX
#define mmOTG0_OTG_CRC0_DATA_B
#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX
#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL
#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX
#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL
#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX
#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL
#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX
#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL
#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX
#define mmOTG0_OTG_CRC1_DATA_RG
#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX
#define mmOTG0_OTG_CRC1_DATA_B
#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX
#define mmOTG0_OTG_CRC2_DATA_RG
#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX
#define mmOTG0_OTG_CRC2_DATA_B
#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX
#define mmOTG0_OTG_CRC3_DATA_RG
#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX
#define mmOTG0_OTG_CRC3_DATA_B
#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX
#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK
#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX
#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK
#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX
#define mmOTG0_OTG_STATIC_SCREEN_CONTROL
#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX
#define mmOTG0_OTG_3D_STRUCTURE_CONTROL
#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX
#define mmOTG0_OTG_GSL_VSYNC_GAP
#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX
#define mmOTG0_OTG_MASTER_UPDATE_MODE
#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX
#define mmOTG0_OTG_CLOCK_CONTROL
#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX
#define mmOTG0_OTG_VSTARTUP_PARAM
#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX
#define mmOTG0_OTG_VUPDATE_PARAM
#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX
#define mmOTG0_OTG_VREADY_PARAM
#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX
#define mmOTG0_OTG_GLOBAL_SYNC_STATUS
#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX
#define mmOTG0_OTG_MASTER_UPDATE_LOCK
#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX
#define mmOTG0_OTG_GSL_CONTROL
#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX
#define mmOTG0_OTG_GSL_WINDOW_X
#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX
#define mmOTG0_OTG_GSL_WINDOW_Y
#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX
#define mmOTG0_OTG_VUPDATE_KEEPOUT
#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX
#define mmOTG0_OTG_GLOBAL_CONTROL0
#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX
#define mmOTG0_OTG_GLOBAL_CONTROL1
#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX
#define mmOTG0_OTG_GLOBAL_CONTROL2
#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX
#define mmOTG0_OTG_GLOBAL_CONTROL3
#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX
#define mmOTG0_OTG_GLOBAL_CONTROL4
#define mmOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX
#define mmOTG0_OTG_TRIG_MANUAL_CONTROL
#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX
#define mmOTG0_OTG_MANUAL_FLOW_CONTROL
#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX
#define mmOTG0_OTG_DRR_TIMING_INT_STATUS
#define mmOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX
#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE
#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX
#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE
#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX
#define mmOTG0_OTG_DRR_TRIGGER_WINDOW
#define mmOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX
#define mmOTG0_OTG_DRR_CONTROL
#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX
#define mmOTG0_OTG_M_CONST_DTO0
#define mmOTG0_OTG_M_CONST_DTO0_BASE_IDX
#define mmOTG0_OTG_M_CONST_DTO1
#define mmOTG0_OTG_M_CONST_DTO1_BASE_IDX
#define mmOTG0_OTG_REQUEST_CONTROL
#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX
#define mmOTG0_OTG_DSC_START_POSITION
#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX
#define mmOTG0_OTG_PIPE_UPDATE_STATUS
#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX
#define mmOTG0_OTG_SPARE_REGISTER
#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX


// addressBlock: dce_dc_optc_otg1_dispdec
// base address: 0x200
#define mmOTG1_OTG_H_TOTAL
#define mmOTG1_OTG_H_TOTAL_BASE_IDX
#define mmOTG1_OTG_H_BLANK_START_END
#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX
#define mmOTG1_OTG_H_SYNC_A
#define mmOTG1_OTG_H_SYNC_A_BASE_IDX
#define mmOTG1_OTG_H_SYNC_A_CNTL
#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX
#define mmOTG1_OTG_H_TIMING_CNTL
#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX
#define mmOTG1_OTG_V_TOTAL
#define mmOTG1_OTG_V_TOTAL_BASE_IDX
#define mmOTG1_OTG_V_TOTAL_MIN
#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX
#define mmOTG1_OTG_V_TOTAL_MAX
#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX
#define mmOTG1_OTG_V_TOTAL_MID
#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX
#define mmOTG1_OTG_V_TOTAL_CONTROL
#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX
#define mmOTG1_OTG_V_TOTAL_INT_STATUS
#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX
#define mmOTG1_OTG_V_BLANK_START_END
#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX
#define mmOTG1_OTG_V_SYNC_A
#define mmOTG1_OTG_V_SYNC_A_BASE_IDX
#define mmOTG1_OTG_V_SYNC_A_CNTL
#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX
#define mmOTG1_OTG_TRIGA_CNTL
#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX
#define mmOTG1_OTG_TRIGB_CNTL
#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX
#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL
#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX
#define mmOTG1_OTG_FLOW_CONTROL
#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX
#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE
#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX
#define mmOTG1_OTG_CONTROL
#define mmOTG1_OTG_CONTROL_BASE_IDX
#define mmOTG1_OTG_INTERLACE_CONTROL
#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX
#define mmOTG1_OTG_INTERLACE_STATUS
#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX
#define mmOTG1_OTG_PIXEL_DATA_READBACK0
#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX
#define mmOTG1_OTG_PIXEL_DATA_READBACK1
#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX
#define mmOTG1_OTG_STATUS
#define mmOTG1_OTG_STATUS_BASE_IDX
#define mmOTG1_OTG_STATUS_POSITION
#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX
#define mmOTG1_OTG_NOM_VERT_POSITION
#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX
#define mmOTG1_OTG_STATUS_FRAME_COUNT
#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX
#define mmOTG1_OTG_STATUS_VF_COUNT
#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX
#define mmOTG1_OTG_STATUS_HV_COUNT
#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX
#define mmOTG1_OTG_COUNT_CONTROL
#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX
#define mmOTG1_OTG_COUNT_RESET
#define mmOTG1_OTG_COUNT_RESET_BASE_IDX
#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX
#define mmOTG1_OTG_VERT_SYNC_CONTROL
#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX
#define mmOTG1_OTG_STEREO_STATUS
#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX
#define mmOTG1_OTG_STEREO_CONTROL
#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX
#define mmOTG1_OTG_SNAPSHOT_STATUS
#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX
#define mmOTG1_OTG_SNAPSHOT_CONTROL
#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX
#define mmOTG1_OTG_SNAPSHOT_POSITION
#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX
#define mmOTG1_OTG_SNAPSHOT_FRAME
#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX
#define mmOTG1_OTG_INTERRUPT_CONTROL
#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX
#define mmOTG1_OTG_UPDATE_LOCK
#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX
#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL
#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX
#define mmOTG1_OTG_MASTER_EN
#define mmOTG1_OTG_MASTER_EN_BASE_IDX
#define mmOTG1_OTG_BLANK_DATA_COLOR
#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX
#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT
#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX
#define mmOTG1_OTG_CRC_CNTL
#define mmOTG1_OTG_CRC_CNTL_BASE_IDX
#define mmOTG1_OTG_CRC_CNTL2
#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX
#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL
#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX
#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL
#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX
#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL
#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX
#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL
#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX
#define mmOTG1_OTG_CRC0_DATA_RG
#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX
#define mmOTG1_OTG_CRC0_DATA_B
#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX
#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL
#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX
#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL
#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX
#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL
#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX
#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL
#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX
#define mmOTG1_OTG_CRC1_DATA_RG
#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX
#define mmOTG1_OTG_CRC1_DATA_B
#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX
#define mmOTG1_OTG_CRC2_DATA_RG
#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX
#define mmOTG1_OTG_CRC2_DATA_B
#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX
#define mmOTG1_OTG_CRC3_DATA_RG
#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX
#define mmOTG1_OTG_CRC3_DATA_B
#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX
#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK
#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX
#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK
#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX
#define mmOTG1_OTG_STATIC_SCREEN_CONTROL
#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX
#define mmOTG1_OTG_3D_STRUCTURE_CONTROL
#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX
#define mmOTG1_OTG_GSL_VSYNC_GAP
#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX
#define mmOTG1_OTG_MASTER_UPDATE_MODE
#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX
#define mmOTG1_OTG_CLOCK_CONTROL
#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX
#define mmOTG1_OTG_VSTARTUP_PARAM
#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX
#define mmOTG1_OTG_VUPDATE_PARAM
#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX
#define mmOTG1_OTG_VREADY_PARAM
#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX
#define mmOTG1_OTG_GLOBAL_SYNC_STATUS
#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX
#define mmOTG1_OTG_MASTER_UPDATE_LOCK
#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX
#define mmOTG1_OTG_GSL_CONTROL
#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX
#define mmOTG1_OTG_GSL_WINDOW_X
#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX
#define mmOTG1_OTG_GSL_WINDOW_Y
#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX
#define mmOTG1_OTG_VUPDATE_KEEPOUT
#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX
#define mmOTG1_OTG_GLOBAL_CONTROL0
#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX
#define mmOTG1_OTG_GLOBAL_CONTROL1
#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX
#define mmOTG1_OTG_GLOBAL_CONTROL2
#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX
#define mmOTG1_OTG_GLOBAL_CONTROL3
#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX
#define mmOTG1_OTG_GLOBAL_CONTROL4
#define mmOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX
#define mmOTG1_OTG_TRIG_MANUAL_CONTROL
#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX
#define mmOTG1_OTG_MANUAL_FLOW_CONTROL
#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX
#define mmOTG1_OTG_DRR_TIMING_INT_STATUS
#define mmOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX
#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE
#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX
#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE
#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX
#define mmOTG1_OTG_DRR_TRIGGER_WINDOW
#define mmOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX
#define mmOTG1_OTG_DRR_CONTROL
#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX
#define mmOTG1_OTG_M_CONST_DTO0
#define mmOTG1_OTG_M_CONST_DTO0_BASE_IDX
#define mmOTG1_OTG_M_CONST_DTO1
#define mmOTG1_OTG_M_CONST_DTO1_BASE_IDX
#define mmOTG1_OTG_REQUEST_CONTROL
#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX
#define mmOTG1_OTG_DSC_START_POSITION
#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX
#define mmOTG1_OTG_PIPE_UPDATE_STATUS
#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX
#define mmOTG1_OTG_SPARE_REGISTER
#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX


// addressBlock: dce_dc_optc_optc_misc_dispdec
// base address: 0x0
#define mmDWB_SOURCE_SELECT
#define mmDWB_SOURCE_SELECT_BASE_IDX
#define mmGSL_SOURCE_SELECT
#define mmGSL_SOURCE_SELECT_BASE_IDX
#define mmOPTC_CLOCK_CONTROL
#define mmOPTC_CLOCK_CONTROL_BASE_IDX
#define mmODM_MEM_PWR_CTRL
#define mmODM_MEM_PWR_CTRL_BASE_IDX
#define mmODM_MEM_PWR_CTRL2
#define mmODM_MEM_PWR_CTRL2_BASE_IDX
#define mmODM_MEM_PWR_CTRL3
#define mmODM_MEM_PWR_CTRL3_BASE_IDX
#define mmODM_MEM_PWR_STATUS
#define mmODM_MEM_PWR_STATUS_BASE_IDX
#define mmOPTC_MISC_SPARE_REGISTER
#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX


// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
// base address: 0x79a8
#define mmDC_PERFMON10_PERFCOUNTER_CNTL
#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON10_PERFCOUNTER_CNTL2
#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON10_PERFCOUNTER_STATE
#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON10_PERFMON_CNTL
#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON10_PERFMON_CNTL2
#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON10_PERFMON_CVALUE_LOW
#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON10_PERFMON_HI
#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON10_PERFMON_LOW
#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_dio_dout_i2c_dispdec
// base address: 0x0
#define mmDC_I2C_CONTROL
#define mmDC_I2C_CONTROL_BASE_IDX
#define mmDC_I2C_ARBITRATION
#define mmDC_I2C_ARBITRATION_BASE_IDX
#define mmDC_I2C_INTERRUPT_CONTROL
#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX
#define mmDC_I2C_SW_STATUS
#define mmDC_I2C_SW_STATUS_BASE_IDX
#define mmDC_I2C_DDC1_HW_STATUS
#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX
#define mmDC_I2C_DDC2_HW_STATUS
#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX
#define mmDC_I2C_DDC1_SPEED
#define mmDC_I2C_DDC1_SPEED_BASE_IDX
#define mmDC_I2C_DDC1_SETUP
#define mmDC_I2C_DDC1_SETUP_BASE_IDX
#define mmDC_I2C_DDC2_SPEED
#define mmDC_I2C_DDC2_SPEED_BASE_IDX
#define mmDC_I2C_DDC2_SETUP
#define mmDC_I2C_DDC2_SETUP_BASE_IDX
#define mmDC_I2C_TRANSACTION0
#define mmDC_I2C_TRANSACTION0_BASE_IDX
#define mmDC_I2C_TRANSACTION1
#define mmDC_I2C_TRANSACTION1_BASE_IDX
#define mmDC_I2C_TRANSACTION2
#define mmDC_I2C_TRANSACTION2_BASE_IDX
#define mmDC_I2C_TRANSACTION3
#define mmDC_I2C_TRANSACTION3_BASE_IDX
#define mmDC_I2C_DATA
#define mmDC_I2C_DATA_BASE_IDX
#define mmDC_I2C_EDID_DETECT_CTRL
#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX
#define mmDC_I2C_READ_REQUEST_INTERRUPT
#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX


// addressBlock: dce_dc_dio_dio_misc_dispdec
// base address: 0x0
#define mmDIO_SCRATCH0
#define mmDIO_SCRATCH0_BASE_IDX
#define mmDIO_SCRATCH1
#define mmDIO_SCRATCH1_BASE_IDX
#define mmDIO_SCRATCH2
#define mmDIO_SCRATCH2_BASE_IDX
#define mmDIO_SCRATCH3
#define mmDIO_SCRATCH3_BASE_IDX
#define mmDIO_SCRATCH4
#define mmDIO_SCRATCH4_BASE_IDX
#define mmDIO_SCRATCH5
#define mmDIO_SCRATCH5_BASE_IDX
#define mmDIO_SCRATCH6
#define mmDIO_SCRATCH6_BASE_IDX
#define mmDIO_SCRATCH7
#define mmDIO_SCRATCH7_BASE_IDX
#define mmDIO_MEM_PWR_STATUS
#define mmDIO_MEM_PWR_STATUS_BASE_IDX
#define mmDIO_MEM_PWR_CTRL
#define mmDIO_MEM_PWR_CTRL_BASE_IDX
#define mmDIO_MEM_PWR_CTRL2
#define mmDIO_MEM_PWR_CTRL2_BASE_IDX
#define mmDIO_CLK_CNTL
#define mmDIO_CLK_CNTL_BASE_IDX
#define mmDIO_POWER_MANAGEMENT_CNTL
#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX
#define mmDIG_SOFT_RESET
#define mmDIG_SOFT_RESET_BASE_IDX
#define mmDIO_CLK_CNTL2
#define mmDIO_CLK_CNTL2_BASE_IDX
#define mmDIO_CLK_CNTL3
#define mmDIO_CLK_CNTL3_BASE_IDX
#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL
#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX
#define mmDIO_GENERIC_INTERRUPT_MESSAGE
#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX
#define mmDIO_GENERIC_INTERRUPT_CLEAR
#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX


// addressBlock: dce_dc_dio_hpd0_dispdec
// base address: 0x0
#define mmHPD0_DC_HPD_INT_STATUS
#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX
#define mmHPD0_DC_HPD_INT_CONTROL
#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX
#define mmHPD0_DC_HPD_CONTROL
#define mmHPD0_DC_HPD_CONTROL_BASE_IDX
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX


// addressBlock: dce_dc_dio_hpd1_dispdec
// base address: 0x20
#define mmHPD1_DC_HPD_INT_STATUS
#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX
#define mmHPD1_DC_HPD_INT_CONTROL
#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX
#define mmHPD1_DC_HPD_CONTROL
#define mmHPD1_DC_HPD_CONTROL_BASE_IDX
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX


// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
// base address: 0x7d10
#define mmDC_PERFMON11_PERFCOUNTER_CNTL
#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON11_PERFCOUNTER_CNTL2
#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON11_PERFCOUNTER_STATE
#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON11_PERFMON_CNTL
#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON11_PERFMON_CNTL2
#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON11_PERFMON_CVALUE_LOW
#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON11_PERFMON_HI
#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON11_PERFMON_LOW
#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_dio_dp_aux0_dispdec
// base address: 0x0
#define mmDP_AUX0_AUX_CONTROL
#define mmDP_AUX0_AUX_CONTROL_BASE_IDX
#define mmDP_AUX0_AUX_SW_CONTROL
#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX
#define mmDP_AUX0_AUX_ARB_CONTROL
#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX
#define mmDP_AUX0_AUX_SW_STATUS
#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX
#define mmDP_AUX0_AUX_LS_STATUS
#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX
#define mmDP_AUX0_AUX_SW_DATA
#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX
#define mmDP_AUX0_AUX_LS_DATA
#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX
#define mmDP_AUX0_AUX_DPHY_TX_STATUS
#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX
#define mmDP_AUX0_AUX_DPHY_RX_STATUS
#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX
#define mmDP_AUX0_AUX_PHY_WAKE_CNTL
#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX


// addressBlock: dce_dc_dio_dp_aux1_dispdec
// base address: 0x70
#define mmDP_AUX1_AUX_CONTROL
#define mmDP_AUX1_AUX_CONTROL_BASE_IDX
#define mmDP_AUX1_AUX_SW_CONTROL
#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX
#define mmDP_AUX1_AUX_ARB_CONTROL
#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX
#define mmDP_AUX1_AUX_SW_STATUS
#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX
#define mmDP_AUX1_AUX_LS_STATUS
#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX
#define mmDP_AUX1_AUX_SW_DATA
#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX
#define mmDP_AUX1_AUX_LS_DATA
#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX
#define mmDP_AUX1_AUX_DPHY_TX_STATUS
#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX
#define mmDP_AUX1_AUX_DPHY_RX_STATUS
#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX
#define mmDP_AUX1_AUX_PHY_WAKE_CNTL
#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX


// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
// base address: 0x154a0
#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL
#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX
#define mmVPG0_VPG_GENERIC_PACKET_DATA
#define mmVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX
#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL
#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX
#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL
#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX
#define mmVPG0_VPG_GENERIC_STATUS
#define mmVPG0_VPG_GENERIC_STATUS_BASE_IDX
#define mmVPG0_VPG_MEM_PWR
#define mmVPG0_VPG_MEM_PWR_BASE_IDX
#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL
#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX
#define mmVPG0_VPG_ISRC1_2_DATA
#define mmVPG0_VPG_ISRC1_2_DATA_BASE_IDX
#define mmVPG0_VPG_MPEG_INFO0
#define mmVPG0_VPG_MPEG_INFO0_BASE_IDX
#define mmVPG0_VPG_MPEG_INFO1
#define mmVPG0_VPG_MPEG_INFO1_BASE_IDX


// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
// base address: 0x154cc
#define mmAFMT0_AFMT_VBI_PACKET_CONTROL
#define mmAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX
#define mmAFMT0_AFMT_AUDIO_INFO0
#define mmAFMT0_AFMT_AUDIO_INFO0_BASE_IDX
#define mmAFMT0_AFMT_AUDIO_INFO1
#define mmAFMT0_AFMT_AUDIO_INFO1_BASE_IDX
#define mmAFMT0_AFMT_60958_0
#define mmAFMT0_AFMT_60958_0_BASE_IDX
#define mmAFMT0_AFMT_60958_1
#define mmAFMT0_AFMT_60958_1_BASE_IDX
#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL
#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX
#define mmAFMT0_AFMT_RAMP_CONTROL0
#define mmAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX
#define mmAFMT0_AFMT_RAMP_CONTROL1
#define mmAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX
#define mmAFMT0_AFMT_RAMP_CONTROL2
#define mmAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX
#define mmAFMT0_AFMT_RAMP_CONTROL3
#define mmAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX
#define mmAFMT0_AFMT_60958_2
#define mmAFMT0_AFMT_60958_2_BASE_IDX
#define mmAFMT0_AFMT_AUDIO_CRC_RESULT
#define mmAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX
#define mmAFMT0_AFMT_STATUS
#define mmAFMT0_AFMT_STATUS_BASE_IDX
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX
#define mmAFMT0_AFMT_INFOFRAME_CONTROL0
#define mmAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX
#define mmAFMT0_AFMT_INTERRUPT_STATUS
#define mmAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX
#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL
#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX
#define mmAFMT0_AFMT_MEM_PWR
#define mmAFMT0_AFMT_MEM_PWR_BASE_IDX


// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
// base address: 0x15524
#define mmDME0_DME_CONTROL
#define mmDME0_DME_CONTROL_BASE_IDX
#define mmDME0_DME_MEMORY_CONTROL
#define mmDME0_DME_MEMORY_CONTROL_BASE_IDX


// addressBlock: dce_dc_dio_dig0_dispdec
// base address: 0x0
#define mmDIG0_DIG_FE_CNTL
#define mmDIG0_DIG_FE_CNTL_BASE_IDX
#define mmDIG0_DIG_OUTPUT_CRC_CNTL
#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX
#define mmDIG0_DIG_OUTPUT_CRC_RESULT
#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX
#define mmDIG0_DIG_CLOCK_PATTERN
#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX
#define mmDIG0_DIG_TEST_PATTERN
#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX
#define mmDIG0_DIG_RANDOM_PATTERN_SEED
#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX
#define mmDIG0_DIG_FIFO_STATUS
#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX
#define mmDIG0_HDMI_METADATA_PACKET_CONTROL
#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX
#define mmDIG0_HDMI_CONTROL
#define mmDIG0_HDMI_CONTROL_BASE_IDX
#define mmDIG0_HDMI_STATUS
#define mmDIG0_HDMI_STATUS_BASE_IDX
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX
#define mmDIG0_HDMI_ACR_PACKET_CONTROL
#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX
#define mmDIG0_HDMI_VBI_PACKET_CONTROL
#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX
#define mmDIG0_HDMI_INFOFRAME_CONTROL0
#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX
#define mmDIG0_HDMI_INFOFRAME_CONTROL1
#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX
#define mmDIG0_HDMI_GC
#define mmDIG0_HDMI_GC_BASE_IDX
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX
#define mmDIG0_HDMI_DB_CONTROL
#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX
#define mmDIG0_HDMI_ACR_32_0
#define mmDIG0_HDMI_ACR_32_0_BASE_IDX
#define mmDIG0_HDMI_ACR_32_1
#define mmDIG0_HDMI_ACR_32_1_BASE_IDX
#define mmDIG0_HDMI_ACR_44_0
#define mmDIG0_HDMI_ACR_44_0_BASE_IDX
#define mmDIG0_HDMI_ACR_44_1
#define mmDIG0_HDMI_ACR_44_1_BASE_IDX
#define mmDIG0_HDMI_ACR_48_0
#define mmDIG0_HDMI_ACR_48_0_BASE_IDX
#define mmDIG0_HDMI_ACR_48_1
#define mmDIG0_HDMI_ACR_48_1_BASE_IDX
#define mmDIG0_HDMI_ACR_STATUS_0
#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX
#define mmDIG0_HDMI_ACR_STATUS_1
#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX
#define mmDIG0_AFMT_CNTL
#define mmDIG0_AFMT_CNTL_BASE_IDX
#define mmDIG0_DIG_BE_CNTL
#define mmDIG0_DIG_BE_CNTL_BASE_IDX
#define mmDIG0_DIG_BE_EN_CNTL
#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX
#define mmDIG0_TMDS_CNTL
#define mmDIG0_TMDS_CNTL_BASE_IDX
#define mmDIG0_TMDS_CONTROL_CHAR
#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX
#define mmDIG0_TMDS_CONTROL0_FEEDBACK
#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX
#define mmDIG0_TMDS_CTL_BITS
#define mmDIG0_TMDS_CTL_BITS_BASE_IDX
#define mmDIG0_TMDS_DCBALANCER_CONTROL
#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX
#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR
#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX
#define mmDIG0_DIG_VERSION
#define mmDIG0_DIG_VERSION_BASE_IDX
#define mmDIG0_DIG_LANE_ENABLE
#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX
#define mmDIG0_FORCE_DIG_DISABLE
#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX

// addressBlock: dce_dc_dio_dp0_dispdec
// base address: 0x0
#define mmDP0_DP_LINK_CNTL
#define mmDP0_DP_LINK_CNTL_BASE_IDX
#define mmDP0_DP_PIXEL_FORMAT
#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX
#define mmDP0_DP_MSA_COLORIMETRY
#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX
#define mmDP0_DP_CONFIG
#define mmDP0_DP_CONFIG_BASE_IDX
#define mmDP0_DP_VID_STREAM_CNTL
#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX
#define mmDP0_DP_STEER_FIFO
#define mmDP0_DP_STEER_FIFO_BASE_IDX
#define mmDP0_DP_MSA_MISC
#define mmDP0_DP_MSA_MISC_BASE_IDX
#define mmDP0_DP_DPHY_INTERNAL_CTRL
#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX
#define mmDP0_DP_VID_TIMING
#define mmDP0_DP_VID_TIMING_BASE_IDX
#define mmDP0_DP_VID_N
#define mmDP0_DP_VID_N_BASE_IDX
#define mmDP0_DP_VID_M
#define mmDP0_DP_VID_M_BASE_IDX
#define mmDP0_DP_LINK_FRAMING_CNTL
#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX
#define mmDP0_DP_HBR2_EYE_PATTERN
#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX
#define mmDP0_DP_VID_MSA_VBID
#define mmDP0_DP_VID_MSA_VBID_BASE_IDX
#define mmDP0_DP_VID_INTERRUPT_CNTL
#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX
#define mmDP0_DP_DPHY_CNTL
#define mmDP0_DP_DPHY_CNTL_BASE_IDX
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX
#define mmDP0_DP_DPHY_SYM0
#define mmDP0_DP_DPHY_SYM0_BASE_IDX
#define mmDP0_DP_DPHY_SYM1
#define mmDP0_DP_DPHY_SYM1_BASE_IDX
#define mmDP0_DP_DPHY_SYM2
#define mmDP0_DP_DPHY_SYM2_BASE_IDX
#define mmDP0_DP_DPHY_8B10B_CNTL
#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX
#define mmDP0_DP_DPHY_PRBS_CNTL
#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX
#define mmDP0_DP_DPHY_SCRAM_CNTL
#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX
#define mmDP0_DP_DPHY_CRC_EN
#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX
#define mmDP0_DP_DPHY_CRC_CNTL
#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX
#define mmDP0_DP_DPHY_CRC_RESULT
#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX
#define mmDP0_DP_DPHY_CRC_MST_CNTL
#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX
#define mmDP0_DP_DPHY_CRC_MST_STATUS
#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX
#define mmDP0_DP_DPHY_FAST_TRAINING
#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX
#define mmDP0_DP_SEC_CNTL
#define mmDP0_DP_SEC_CNTL_BASE_IDX
#define mmDP0_DP_SEC_CNTL1
#define mmDP0_DP_SEC_CNTL1_BASE_IDX
#define mmDP0_DP_SEC_FRAMING1
#define mmDP0_DP_SEC_FRAMING1_BASE_IDX
#define mmDP0_DP_SEC_FRAMING2
#define mmDP0_DP_SEC_FRAMING2_BASE_IDX
#define mmDP0_DP_SEC_FRAMING3
#define mmDP0_DP_SEC_FRAMING3_BASE_IDX
#define mmDP0_DP_SEC_FRAMING4
#define mmDP0_DP_SEC_FRAMING4_BASE_IDX
#define mmDP0_DP_SEC_AUD_N
#define mmDP0_DP_SEC_AUD_N_BASE_IDX
#define mmDP0_DP_SEC_AUD_N_READBACK
#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX
#define mmDP0_DP_SEC_AUD_M
#define mmDP0_DP_SEC_AUD_M_BASE_IDX
#define mmDP0_DP_SEC_AUD_M_READBACK
#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX
#define mmDP0_DP_SEC_TIMESTAMP
#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX
#define mmDP0_DP_SEC_PACKET_CNTL
#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX
#define mmDP0_DP_MSE_RATE_CNTL
#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX
#define mmDP0_DP_MSE_RATE_UPDATE
#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX
#define mmDP0_DP_MSE_SAT0
#define mmDP0_DP_MSE_SAT0_BASE_IDX
#define mmDP0_DP_MSE_SAT1
#define mmDP0_DP_MSE_SAT1_BASE_IDX
#define mmDP0_DP_MSE_SAT2
#define mmDP0_DP_MSE_SAT2_BASE_IDX
#define mmDP0_DP_MSE_SAT_UPDATE
#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX
#define mmDP0_DP_MSE_LINK_TIMING
#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX
#define mmDP0_DP_MSE_MISC_CNTL
#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX
#define mmDP0_DP_MSE_SAT0_STATUS
#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX
#define mmDP0_DP_MSE_SAT1_STATUS
#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX
#define mmDP0_DP_MSE_SAT2_STATUS
#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX
#define mmDP0_DP_MSA_TIMING_PARAM1
#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX
#define mmDP0_DP_MSA_TIMING_PARAM2
#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX
#define mmDP0_DP_MSA_TIMING_PARAM3
#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX
#define mmDP0_DP_MSA_TIMING_PARAM4
#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX
#define mmDP0_DP_MSO_CNTL
#define mmDP0_DP_MSO_CNTL_BASE_IDX
#define mmDP0_DP_MSO_CNTL1
#define mmDP0_DP_MSO_CNTL1_BASE_IDX
#define mmDP0_DP_DSC_CNTL
#define mmDP0_DP_DSC_CNTL_BASE_IDX
#define mmDP0_DP_SEC_CNTL2
#define mmDP0_DP_SEC_CNTL2_BASE_IDX
#define mmDP0_DP_SEC_CNTL3
#define mmDP0_DP_SEC_CNTL3_BASE_IDX
#define mmDP0_DP_SEC_CNTL4
#define mmDP0_DP_SEC_CNTL4_BASE_IDX
#define mmDP0_DP_SEC_CNTL5
#define mmDP0_DP_SEC_CNTL5_BASE_IDX
#define mmDP0_DP_SEC_CNTL6
#define mmDP0_DP_SEC_CNTL6_BASE_IDX
#define mmDP0_DP_SEC_CNTL7
#define mmDP0_DP_SEC_CNTL7_BASE_IDX
#define mmDP0_DP_DB_CNTL
#define mmDP0_DP_DB_CNTL_BASE_IDX
#define mmDP0_DP_MSA_VBID_MISC
#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX
#define mmDP0_DP_SEC_METADATA_TRANSMISSION
#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX
#define mmDP0_DP_DSC_BYTES_PER_PIXEL
#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX
#define mmDP0_DP_ALPM_CNTL
#define mmDP0_DP_ALPM_CNTL_BASE_IDX
#define mmDP0_DP_GSP8_CNTL
#define mmDP0_DP_GSP8_CNTL_BASE_IDX
#define mmDP0_DP_GSP9_CNTL
#define mmDP0_DP_GSP9_CNTL_BASE_IDX
#define mmDP0_DP_GSP10_CNTL
#define mmDP0_DP_GSP10_CNTL_BASE_IDX
#define mmDP0_DP_GSP11_CNTL
#define mmDP0_DP_GSP11_CNTL_BASE_IDX
#define mmDP0_DP_GSP_EN_DB_STATUS
#define mmDP0_DP_GSP_EN_DB_STATUS_BASE_IDX


// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
// base address: 0x158a0
#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL
#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX
#define mmVPG1_VPG_GENERIC_PACKET_DATA
#define mmVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX
#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL
#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX
#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL
#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX
#define mmVPG1_VPG_GENERIC_STATUS
#define mmVPG1_VPG_GENERIC_STATUS_BASE_IDX
#define mmVPG1_VPG_MEM_PWR
#define mmVPG1_VPG_MEM_PWR_BASE_IDX
#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL
#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX
#define mmVPG1_VPG_ISRC1_2_DATA
#define mmVPG1_VPG_ISRC1_2_DATA_BASE_IDX
#define mmVPG1_VPG_MPEG_INFO0
#define mmVPG1_VPG_MPEG_INFO0_BASE_IDX
#define mmVPG1_VPG_MPEG_INFO1
#define mmVPG1_VPG_MPEG_INFO1_BASE_IDX


// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
// base address: 0x158cc
#define mmAFMT1_AFMT_VBI_PACKET_CONTROL
#define mmAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX
#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2
#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX
#define mmAFMT1_AFMT_AUDIO_INFO0
#define mmAFMT1_AFMT_AUDIO_INFO0_BASE_IDX
#define mmAFMT1_AFMT_AUDIO_INFO1
#define mmAFMT1_AFMT_AUDIO_INFO1_BASE_IDX
#define mmAFMT1_AFMT_60958_0
#define mmAFMT1_AFMT_60958_0_BASE_IDX
#define mmAFMT1_AFMT_60958_1
#define mmAFMT1_AFMT_60958_1_BASE_IDX
#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL
#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX
#define mmAFMT1_AFMT_RAMP_CONTROL0
#define mmAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX
#define mmAFMT1_AFMT_RAMP_CONTROL1
#define mmAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX
#define mmAFMT1_AFMT_RAMP_CONTROL2
#define mmAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX
#define mmAFMT1_AFMT_RAMP_CONTROL3
#define mmAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX
#define mmAFMT1_AFMT_60958_2
#define mmAFMT1_AFMT_60958_2_BASE_IDX
#define mmAFMT1_AFMT_AUDIO_CRC_RESULT
#define mmAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX
#define mmAFMT1_AFMT_STATUS
#define mmAFMT1_AFMT_STATUS_BASE_IDX
#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL
#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX
#define mmAFMT1_AFMT_INFOFRAME_CONTROL0
#define mmAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX
#define mmAFMT1_AFMT_INTERRUPT_STATUS
#define mmAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX
#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL
#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX
#define mmAFMT1_AFMT_MEM_PWR
#define mmAFMT1_AFMT_MEM_PWR_BASE_IDX


// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
// base address: 0x15924
#define mmDME1_DME_CONTROL
#define mmDME1_DME_CONTROL_BASE_IDX
#define mmDME1_DME_MEMORY_CONTROL
#define mmDME1_DME_MEMORY_CONTROL_BASE_IDX


// addressBlock: dce_dc_dio_dig1_dispdec
// base address: 0x400
#define mmDIG1_DIG_FE_CNTL
#define mmDIG1_DIG_FE_CNTL_BASE_IDX
#define mmDIG1_DIG_OUTPUT_CRC_CNTL
#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX
#define mmDIG1_DIG_OUTPUT_CRC_RESULT
#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX
#define mmDIG1_DIG_CLOCK_PATTERN
#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX
#define mmDIG1_DIG_TEST_PATTERN
#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX
#define mmDIG1_DIG_RANDOM_PATTERN_SEED
#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX
#define mmDIG1_DIG_FIFO_STATUS
#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX
#define mmDIG1_HDMI_METADATA_PACKET_CONTROL
#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX
#define mmDIG1_HDMI_CONTROL
#define mmDIG1_HDMI_CONTROL_BASE_IDX
#define mmDIG1_HDMI_STATUS
#define mmDIG1_HDMI_STATUS_BASE_IDX
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX
#define mmDIG1_HDMI_ACR_PACKET_CONTROL
#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX
#define mmDIG1_HDMI_VBI_PACKET_CONTROL
#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX
#define mmDIG1_HDMI_INFOFRAME_CONTROL0
#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX
#define mmDIG1_HDMI_INFOFRAME_CONTROL1
#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX
#define mmDIG1_HDMI_GC
#define mmDIG1_HDMI_GC_BASE_IDX
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX
#define mmDIG1_HDMI_DB_CONTROL
#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX
#define mmDIG1_HDMI_ACR_32_0
#define mmDIG1_HDMI_ACR_32_0_BASE_IDX
#define mmDIG1_HDMI_ACR_32_1
#define mmDIG1_HDMI_ACR_32_1_BASE_IDX
#define mmDIG1_HDMI_ACR_44_0
#define mmDIG1_HDMI_ACR_44_0_BASE_IDX
#define mmDIG1_HDMI_ACR_44_1
#define mmDIG1_HDMI_ACR_44_1_BASE_IDX
#define mmDIG1_HDMI_ACR_48_0
#define mmDIG1_HDMI_ACR_48_0_BASE_IDX
#define mmDIG1_HDMI_ACR_48_1
#define mmDIG1_HDMI_ACR_48_1_BASE_IDX
#define mmDIG1_HDMI_ACR_STATUS_0
#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX
#define mmDIG1_HDMI_ACR_STATUS_1
#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX
#define mmDIG1_AFMT_CNTL
#define mmDIG1_AFMT_CNTL_BASE_IDX
#define mmDIG1_DIG_BE_CNTL
#define mmDIG1_DIG_BE_CNTL_BASE_IDX
#define mmDIG1_DIG_BE_EN_CNTL
#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX
#define mmDIG1_TMDS_CNTL
#define mmDIG1_TMDS_CNTL_BASE_IDX
#define mmDIG1_TMDS_CONTROL_CHAR
#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX
#define mmDIG1_TMDS_CONTROL0_FEEDBACK
#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX
#define mmDIG1_TMDS_CTL_BITS
#define mmDIG1_TMDS_CTL_BITS_BASE_IDX
#define mmDIG1_TMDS_DCBALANCER_CONTROL
#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX
#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR
#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX
#define mmDIG1_DIG_VERSION
#define mmDIG1_DIG_VERSION_BASE_IDX
#define mmDIG1_DIG_LANE_ENABLE
#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX
#define mmDIG1_FORCE_DIG_DISABLE
#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX

// addressBlock: dce_dc_dio_dp1_dispdec
// base address: 0x400
#define mmDP1_DP_LINK_CNTL
#define mmDP1_DP_LINK_CNTL_BASE_IDX
#define mmDP1_DP_PIXEL_FORMAT
#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX
#define mmDP1_DP_MSA_COLORIMETRY
#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX
#define mmDP1_DP_CONFIG
#define mmDP1_DP_CONFIG_BASE_IDX
#define mmDP1_DP_VID_STREAM_CNTL
#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX
#define mmDP1_DP_STEER_FIFO
#define mmDP1_DP_STEER_FIFO_BASE_IDX
#define mmDP1_DP_MSA_MISC
#define mmDP1_DP_MSA_MISC_BASE_IDX
#define mmDP1_DP_DPHY_INTERNAL_CTRL
#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX
#define mmDP1_DP_VID_TIMING
#define mmDP1_DP_VID_TIMING_BASE_IDX
#define mmDP1_DP_VID_N
#define mmDP1_DP_VID_N_BASE_IDX
#define mmDP1_DP_VID_M
#define mmDP1_DP_VID_M_BASE_IDX
#define mmDP1_DP_LINK_FRAMING_CNTL
#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX
#define mmDP1_DP_HBR2_EYE_PATTERN
#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX
#define mmDP1_DP_VID_MSA_VBID
#define mmDP1_DP_VID_MSA_VBID_BASE_IDX
#define mmDP1_DP_VID_INTERRUPT_CNTL
#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX
#define mmDP1_DP_DPHY_CNTL
#define mmDP1_DP_DPHY_CNTL_BASE_IDX
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX
#define mmDP1_DP_DPHY_SYM0
#define mmDP1_DP_DPHY_SYM0_BASE_IDX
#define mmDP1_DP_DPHY_SYM1
#define mmDP1_DP_DPHY_SYM1_BASE_IDX
#define mmDP1_DP_DPHY_SYM2
#define mmDP1_DP_DPHY_SYM2_BASE_IDX
#define mmDP1_DP_DPHY_8B10B_CNTL
#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX
#define mmDP1_DP_DPHY_PRBS_CNTL
#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX
#define mmDP1_DP_DPHY_SCRAM_CNTL
#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX
#define mmDP1_DP_DPHY_CRC_EN
#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX
#define mmDP1_DP_DPHY_CRC_CNTL
#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX
#define mmDP1_DP_DPHY_CRC_RESULT
#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX
#define mmDP1_DP_DPHY_CRC_MST_CNTL
#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX
#define mmDP1_DP_DPHY_CRC_MST_STATUS
#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX
#define mmDP1_DP_DPHY_FAST_TRAINING
#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX
#define mmDP1_DP_SEC_CNTL
#define mmDP1_DP_SEC_CNTL_BASE_IDX
#define mmDP1_DP_SEC_CNTL1
#define mmDP1_DP_SEC_CNTL1_BASE_IDX
#define mmDP1_DP_SEC_FRAMING1
#define mmDP1_DP_SEC_FRAMING1_BASE_IDX
#define mmDP1_DP_SEC_FRAMING2
#define mmDP1_DP_SEC_FRAMING2_BASE_IDX
#define mmDP1_DP_SEC_FRAMING3
#define mmDP1_DP_SEC_FRAMING3_BASE_IDX
#define mmDP1_DP_SEC_FRAMING4
#define mmDP1_DP_SEC_FRAMING4_BASE_IDX
#define mmDP1_DP_SEC_AUD_N
#define mmDP1_DP_SEC_AUD_N_BASE_IDX
#define mmDP1_DP_SEC_AUD_N_READBACK
#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX
#define mmDP1_DP_SEC_AUD_M
#define mmDP1_DP_SEC_AUD_M_BASE_IDX
#define mmDP1_DP_SEC_AUD_M_READBACK
#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX
#define mmDP1_DP_SEC_TIMESTAMP
#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX
#define mmDP1_DP_SEC_PACKET_CNTL
#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX
#define mmDP1_DP_MSE_RATE_CNTL
#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX
#define mmDP1_DP_MSE_RATE_UPDATE
#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX
#define mmDP1_DP_MSE_SAT0
#define mmDP1_DP_MSE_SAT0_BASE_IDX
#define mmDP1_DP_MSE_SAT1
#define mmDP1_DP_MSE_SAT1_BASE_IDX
#define mmDP1_DP_MSE_SAT2
#define mmDP1_DP_MSE_SAT2_BASE_IDX
#define mmDP1_DP_MSE_SAT_UPDATE
#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX
#define mmDP1_DP_MSE_LINK_TIMING
#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX
#define mmDP1_DP_MSE_MISC_CNTL
#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX
#define mmDP1_DP_MSE_SAT0_STATUS
#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX
#define mmDP1_DP_MSE_SAT1_STATUS
#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX
#define mmDP1_DP_MSE_SAT2_STATUS
#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX
#define mmDP1_DP_MSA_TIMING_PARAM1
#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX
#define mmDP1_DP_MSA_TIMING_PARAM2
#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX
#define mmDP1_DP_MSA_TIMING_PARAM3
#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX
#define mmDP1_DP_MSA_TIMING_PARAM4
#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX
#define mmDP1_DP_MSO_CNTL
#define mmDP1_DP_MSO_CNTL_BASE_IDX
#define mmDP1_DP_MSO_CNTL1
#define mmDP1_DP_MSO_CNTL1_BASE_IDX
#define mmDP1_DP_DSC_CNTL
#define mmDP1_DP_DSC_CNTL_BASE_IDX
#define mmDP1_DP_SEC_CNTL2
#define mmDP1_DP_SEC_CNTL2_BASE_IDX
#define mmDP1_DP_SEC_CNTL3
#define mmDP1_DP_SEC_CNTL3_BASE_IDX
#define mmDP1_DP_SEC_CNTL4
#define mmDP1_DP_SEC_CNTL4_BASE_IDX
#define mmDP1_DP_SEC_CNTL5
#define mmDP1_DP_SEC_CNTL5_BASE_IDX
#define mmDP1_DP_SEC_CNTL6
#define mmDP1_DP_SEC_CNTL6_BASE_IDX
#define mmDP1_DP_SEC_CNTL7
#define mmDP1_DP_SEC_CNTL7_BASE_IDX
#define mmDP1_DP_DB_CNTL
#define mmDP1_DP_DB_CNTL_BASE_IDX
#define mmDP1_DP_MSA_VBID_MISC
#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX
#define mmDP1_DP_SEC_METADATA_TRANSMISSION
#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX
#define mmDP1_DP_DSC_BYTES_PER_PIXEL
#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX
#define mmDP1_DP_ALPM_CNTL
#define mmDP1_DP_ALPM_CNTL_BASE_IDX
#define mmDP1_DP_GSP8_CNTL
#define mmDP1_DP_GSP8_CNTL_BASE_IDX
#define mmDP1_DP_GSP9_CNTL
#define mmDP1_DP_GSP9_CNTL_BASE_IDX
#define mmDP1_DP_GSP10_CNTL
#define mmDP1_DP_GSP10_CNTL_BASE_IDX
#define mmDP1_DP_GSP11_CNTL
#define mmDP1_DP_GSP11_CNTL_BASE_IDX
#define mmDP1_DP_GSP_EN_DB_STATUS
#define mmDP1_DP_GSP_EN_DB_STATUS_BASE_IDX


// addressBlock: dce_dc_dcio_dcio_dispdec
// base address: 0x0
#define mmDC_GENERICA
#define mmDC_GENERICA_BASE_IDX
#define mmDC_GENERICB
#define mmDC_GENERICB_BASE_IDX
#define mmDCIO_CLOCK_CNTL
#define mmDCIO_CLOCK_CNTL_BASE_IDX
#define mmDC_REF_CLK_CNTL
#define mmDC_REF_CLK_CNTL_BASE_IDX
#define mmUNIPHYA_LINK_CNTL
#define mmUNIPHYA_LINK_CNTL_BASE_IDX
#define mmUNIPHYA_CHANNEL_XBAR_CNTL
#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX
#define mmUNIPHYB_LINK_CNTL
#define mmUNIPHYB_LINK_CNTL_BASE_IDX
#define mmUNIPHYB_CHANNEL_XBAR_CNTL
#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX
#define mmDCIO_WRCMD_DELAY
#define mmDCIO_WRCMD_DELAY_BASE_IDX
#define mmDC_PINSTRAPS
#define mmDC_PINSTRAPS_BASE_IDX
#define mmLVTMA_PWRSEQ_CNTL
#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX
#define mmLVTMA_PWRSEQ_STATE
#define mmLVTMA_PWRSEQ_STATE_BASE_IDX
#define mmLVTMA_PWRSEQ_REF_DIV
#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX
#define mmLVTMA_PWRSEQ_DELAY1
#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX
#define mmLVTMA_PWRSEQ_DELAY2
#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX
#define mmBL_PWM_CNTL
#define mmBL_PWM_CNTL_BASE_IDX
#define mmBL_PWM_CNTL2
#define mmBL_PWM_CNTL2_BASE_IDX
#define mmBL_PWM_PERIOD_CNTL
#define mmBL_PWM_PERIOD_CNTL_BASE_IDX
#define mmBL_PWM_GRP1_REG_LOCK
#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX
#define mmDCIO_GSL_GENLK_PAD_CNTL
#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX
#define mmDCIO_SOFT_RESET
#define mmDCIO_SOFT_RESET_BASE_IDX


// addressBlock: dce_dc_dcio_dcio_chip_dispdec
// base address: 0x0
#define mmDC_GPIO_GENERIC_MASK
#define mmDC_GPIO_GENERIC_MASK_BASE_IDX
#define mmDC_GPIO_GENERIC_A
#define mmDC_GPIO_GENERIC_A_BASE_IDX
#define mmDC_GPIO_GENERIC_EN
#define mmDC_GPIO_GENERIC_EN_BASE_IDX
#define mmDC_GPIO_GENERIC_Y
#define mmDC_GPIO_GENERIC_Y_BASE_IDX
#define mmDC_GPIO_DDC1_MASK
#define mmDC_GPIO_DDC1_MASK_BASE_IDX
#define mmDC_GPIO_DDC1_A
#define mmDC_GPIO_DDC1_A_BASE_IDX
#define mmDC_GPIO_DDC1_EN
#define mmDC_GPIO_DDC1_EN_BASE_IDX
#define mmDC_GPIO_DDC1_Y
#define mmDC_GPIO_DDC1_Y_BASE_IDX
#define mmDC_GPIO_DDC2_MASK
#define mmDC_GPIO_DDC2_MASK_BASE_IDX
#define mmDC_GPIO_DDC2_A
#define mmDC_GPIO_DDC2_A_BASE_IDX
#define mmDC_GPIO_DDC2_EN
#define mmDC_GPIO_DDC2_EN_BASE_IDX
#define mmDC_GPIO_DDC2_Y
#define mmDC_GPIO_DDC2_Y_BASE_IDX
#define mmDC_GPIO_DDCVGA_MASK
#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX
#define mmDC_GPIO_DDCVGA_A
#define mmDC_GPIO_DDCVGA_A_BASE_IDX
#define mmDC_GPIO_DDCVGA_EN
#define mmDC_GPIO_DDCVGA_EN_BASE_IDX
#define mmDC_GPIO_DDCVGA_Y
#define mmDC_GPIO_DDCVGA_Y_BASE_IDX
#define mmDC_GPIO_GENLK_MASK
#define mmDC_GPIO_GENLK_MASK_BASE_IDX
#define mmDC_GPIO_GENLK_A
#define mmDC_GPIO_GENLK_A_BASE_IDX
#define mmDC_GPIO_GENLK_EN
#define mmDC_GPIO_GENLK_EN_BASE_IDX
#define mmDC_GPIO_GENLK_Y
#define mmDC_GPIO_GENLK_Y_BASE_IDX
#define mmDC_GPIO_HPD_MASK
#define mmDC_GPIO_HPD_MASK_BASE_IDX
#define mmDC_GPIO_HPD_A
#define mmDC_GPIO_HPD_A_BASE_IDX
#define mmDC_GPIO_HPD_EN
#define mmDC_GPIO_HPD_EN_BASE_IDX
#define mmDC_GPIO_HPD_Y
#define mmDC_GPIO_HPD_Y_BASE_IDX
#define mmDC_GPIO_PWRSEQ_MASK
#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX
#define mmDC_GPIO_PWRSEQ_A
#define mmDC_GPIO_PWRSEQ_A_BASE_IDX
#define mmDC_GPIO_PWRSEQ_EN
#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX
#define mmDC_GPIO_PWRSEQ_Y
#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX
#define mmDC_GPIO_PAD_STRENGTH_1
#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX
#define mmDC_GPIO_PAD_STRENGTH_2
#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX
#define mmPHY_AUX_CNTL
#define mmPHY_AUX_CNTL_BASE_IDX
#define mmDC_GPIO_TX12_EN
#define mmDC_GPIO_TX12_EN_BASE_IDX
#define mmDC_GPIO_AUX_CTRL_0
#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX
#define mmDC_GPIO_AUX_CTRL_1
#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX
#define mmDC_GPIO_AUX_CTRL_2
#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX
#define mmDC_GPIO_RXEN
#define mmDC_GPIO_RXEN_BASE_IDX
#define mmDC_GPIO_PULLUPEN
#define mmDC_GPIO_PULLUPEN_BASE_IDX
#define mmDC_GPIO_AUX_CTRL_3
#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX
#define mmDC_GPIO_AUX_CTRL_4
#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX
#define mmDC_GPIO_AUX_CTRL_5
#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX
#define mmAUXI2C_PAD_ALL_PWR_OK
#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX



// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
// base address: 0x0
#define mmDSC_TOP0_DSC_TOP_CONTROL
#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX
#define mmDSC_TOP0_DSC_DEBUG_CONTROL
#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX


// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
// base address: 0x0
#define mmDSCCIF0_DSCCIF_CONFIG0
#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX
#define mmDSCCIF0_DSCCIF_CONFIG1
#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX


// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
// base address: 0x0
#define mmDSCC0_DSCC_CONFIG0
#define mmDSCC0_DSCC_CONFIG0_BASE_IDX
#define mmDSCC0_DSCC_CONFIG1
#define mmDSCC0_DSCC_CONFIG1_BASE_IDX
#define mmDSCC0_DSCC_STATUS
#define mmDSCC0_DSCC_STATUS_BASE_IDX
#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS
#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG0
#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG1
#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG2
#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG3
#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG4
#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG5
#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG6
#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG7
#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG8
#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG9
#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG10
#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG11
#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG12
#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG13
#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG14
#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG15
#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG16
#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG17
#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG18
#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG19
#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG20
#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG21
#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX
#define mmDSCC0_DSCC_PPS_CONFIG22
#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX
#define mmDSCC0_DSCC_MEM_POWER_CONTROL
#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX
#define mmDSCC0_DSCC_MAX_ABS_ERROR0
#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX
#define mmDSCC0_DSCC_MAX_ABS_ERROR1
#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX
#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3
#define mmDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX
#define mmDSCC0_DSCC_TEST_DEBUG_DATA0
#define mmDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX
#define mmDSCC0_DSCC_TEST_DEBUG_DATA1
#define mmDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX
#define mmDSCC0_DSCC_TEST_DEBUG_DATA2
#define mmDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX
#define mmDSCC0_DSCC_TEST_DEBUG_DATA3
#define mmDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX


// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
// base address: 0xc140
#define mmDC_PERFMON12_PERFCOUNTER_CNTL
#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON12_PERFCOUNTER_STATE
#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON12_PERFMON_CNTL
#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON12_PERFMON_CNTL2
#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON12_PERFMON_HI
#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON12_PERFMON_LOW
#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
// base address: 0x170
#define mmDSC_TOP1_DSC_TOP_CONTROL
#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX
#define mmDSC_TOP1_DSC_DEBUG_CONTROL
#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX


// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
// base address: 0x170
#define mmDSCCIF1_DSCCIF_CONFIG0
#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX
#define mmDSCCIF1_DSCCIF_CONFIG1
#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX


// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
// base address: 0x170
#define mmDSCC1_DSCC_CONFIG0
#define mmDSCC1_DSCC_CONFIG0_BASE_IDX
#define mmDSCC1_DSCC_CONFIG1
#define mmDSCC1_DSCC_CONFIG1_BASE_IDX
#define mmDSCC1_DSCC_STATUS
#define mmDSCC1_DSCC_STATUS_BASE_IDX
#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS
#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG0
#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG1
#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG2
#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG3
#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG4
#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG5
#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG6
#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG7
#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG8
#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG9
#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG10
#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG11
#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG12
#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG13
#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG14
#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG15
#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG16
#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG17
#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG18
#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG19
#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG20
#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG21
#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX
#define mmDSCC1_DSCC_PPS_CONFIG22
#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX
#define mmDSCC1_DSCC_MEM_POWER_CONTROL
#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX
#define mmDSCC1_DSCC_MAX_ABS_ERROR0
#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX
#define mmDSCC1_DSCC_MAX_ABS_ERROR1
#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX
#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3
#define mmDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX
#define mmDSCC1_DSCC_TEST_DEBUG_DATA0
#define mmDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX
#define mmDSCC1_DSCC_TEST_DEBUG_DATA1
#define mmDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX
#define mmDSCC1_DSCC_TEST_DEBUG_DATA2
#define mmDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX
#define mmDSCC1_DSCC_TEST_DEBUG_DATA3
#define mmDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX


// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
// base address: 0xc2b0
#define mmDC_PERFMON13_PERFCOUNTER_CNTL
#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON13_PERFCOUNTER_STATE
#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON13_PERFMON_CNTL
#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON13_PERFMON_CNTL2
#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON13_PERFMON_HI
#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON13_PERFMON_LOW
#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
// base address: 0x0
#define mmDWB_ENABLE_CLK_CTRL
#define mmDWB_ENABLE_CLK_CTRL_BASE_IDX
#define mmDWB_MEM_PWR_CTRL
#define mmDWB_MEM_PWR_CTRL_BASE_IDX
#define mmFC_MODE_CTRL
#define mmFC_MODE_CTRL_BASE_IDX
#define mmFC_FLOW_CTRL
#define mmFC_FLOW_CTRL_BASE_IDX
#define mmFC_WINDOW_START
#define mmFC_WINDOW_START_BASE_IDX
#define mmFC_WINDOW_SIZE
#define mmFC_WINDOW_SIZE_BASE_IDX
#define mmFC_SOURCE_SIZE
#define mmFC_SOURCE_SIZE_BASE_IDX
#define mmDWB_UPDATE_CTRL
#define mmDWB_UPDATE_CTRL_BASE_IDX
#define mmDWB_CRC_CTRL
#define mmDWB_CRC_CTRL_BASE_IDX
#define mmDWB_CRC_MASK_R_G
#define mmDWB_CRC_MASK_R_G_BASE_IDX
#define mmDWB_CRC_MASK_B_A
#define mmDWB_CRC_MASK_B_A_BASE_IDX
#define mmDWB_CRC_VAL_R_G
#define mmDWB_CRC_VAL_R_G_BASE_IDX
#define mmDWB_CRC_VAL_B_A
#define mmDWB_CRC_VAL_B_A_BASE_IDX
#define mmDWB_OUT_CTRL
#define mmDWB_OUT_CTRL_BASE_IDX
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX
#define mmDWB_HOST_READ_CONTROL
#define mmDWB_HOST_READ_CONTROL_BASE_IDX
#define mmDWB_OVERFLOW_STATUS
#define mmDWB_OVERFLOW_STATUS_BASE_IDX
#define mmDWB_OVERFLOW_COUNTER
#define mmDWB_OVERFLOW_COUNTER_BASE_IDX
#define mmDWB_SOFT_RESET
#define mmDWB_SOFT_RESET_BASE_IDX


// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
// base address: 0xca20
#define mmDC_PERFMON14_PERFCOUNTER_CNTL
#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON14_PERFCOUNTER_CNTL2
#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON14_PERFCOUNTER_STATE
#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON14_PERFMON_CNTL
#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON14_PERFMON_CNTL2
#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON14_PERFMON_CVALUE_LOW
#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON14_PERFMON_HI
#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON14_PERFMON_LOW
#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
// base address: 0x0
#define mmDWB_HDR_MULT_COEF
#define mmDWB_HDR_MULT_COEF_BASE_IDX
#define mmDWB_GAMUT_REMAP_MODE
#define mmDWB_GAMUT_REMAP_MODE_BASE_IDX
#define mmDWB_GAMUT_REMAP_COEF_FORMAT
#define mmDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX
#define mmDWB_GAMUT_REMAPA_C11_C12
#define mmDWB_GAMUT_REMAPA_C11_C12_BASE_IDX
#define mmDWB_GAMUT_REMAPA_C13_C14
#define mmDWB_GAMUT_REMAPA_C13_C14_BASE_IDX
#define mmDWB_GAMUT_REMAPA_C21_C22
#define mmDWB_GAMUT_REMAPA_C21_C22_BASE_IDX
#define mmDWB_GAMUT_REMAPA_C23_C24
#define mmDWB_GAMUT_REMAPA_C23_C24_BASE_IDX
#define mmDWB_GAMUT_REMAPA_C31_C32
#define mmDWB_GAMUT_REMAPA_C31_C32_BASE_IDX
#define mmDWB_GAMUT_REMAPA_C33_C34
#define mmDWB_GAMUT_REMAPA_C33_C34_BASE_IDX
#define mmDWB_GAMUT_REMAPB_C11_C12
#define mmDWB_GAMUT_REMAPB_C11_C12_BASE_IDX
#define mmDWB_GAMUT_REMAPB_C13_C14
#define mmDWB_GAMUT_REMAPB_C13_C14_BASE_IDX
#define mmDWB_GAMUT_REMAPB_C21_C22
#define mmDWB_GAMUT_REMAPB_C21_C22_BASE_IDX
#define mmDWB_GAMUT_REMAPB_C23_C24
#define mmDWB_GAMUT_REMAPB_C23_C24_BASE_IDX
#define mmDWB_GAMUT_REMAPB_C31_C32
#define mmDWB_GAMUT_REMAPB_C31_C32_BASE_IDX
#define mmDWB_GAMUT_REMAPB_C33_C34
#define mmDWB_GAMUT_REMAPB_C33_C34_BASE_IDX
#define mmDWB_OGAM_CONTROL
#define mmDWB_OGAM_CONTROL_BASE_IDX
#define mmDWB_OGAM_LUT_INDEX
#define mmDWB_OGAM_LUT_INDEX_BASE_IDX
#define mmDWB_OGAM_LUT_DATA
#define mmDWB_OGAM_LUT_DATA_BASE_IDX
#define mmDWB_OGAM_LUT_CONTROL
#define mmDWB_OGAM_LUT_CONTROL_BASE_IDX
#define mmDWB_OGAM_RAMA_START_CNTL_B
#define mmDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX
#define mmDWB_OGAM_RAMA_START_CNTL_G
#define mmDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX
#define mmDWB_OGAM_RAMA_START_CNTL_R
#define mmDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX
#define mmDWB_OGAM_RAMA_END_CNTL1_B
#define mmDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX
#define mmDWB_OGAM_RAMA_END_CNTL2_B
#define mmDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX
#define mmDWB_OGAM_RAMA_END_CNTL1_G
#define mmDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX
#define mmDWB_OGAM_RAMA_END_CNTL2_G
#define mmDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX
#define mmDWB_OGAM_RAMA_END_CNTL1_R
#define mmDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX
#define mmDWB_OGAM_RAMA_END_CNTL2_R
#define mmDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX
#define mmDWB_OGAM_RAMA_OFFSET_B
#define mmDWB_OGAM_RAMA_OFFSET_B_BASE_IDX
#define mmDWB_OGAM_RAMA_OFFSET_G
#define mmDWB_OGAM_RAMA_OFFSET_G_BASE_IDX
#define mmDWB_OGAM_RAMA_OFFSET_R
#define mmDWB_OGAM_RAMA_OFFSET_R_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_0_1
#define mmDWB_OGAM_RAMA_REGION_0_1_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_2_3
#define mmDWB_OGAM_RAMA_REGION_2_3_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_4_5
#define mmDWB_OGAM_RAMA_REGION_4_5_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_6_7
#define mmDWB_OGAM_RAMA_REGION_6_7_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_8_9
#define mmDWB_OGAM_RAMA_REGION_8_9_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_10_11
#define mmDWB_OGAM_RAMA_REGION_10_11_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_12_13
#define mmDWB_OGAM_RAMA_REGION_12_13_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_14_15
#define mmDWB_OGAM_RAMA_REGION_14_15_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_16_17
#define mmDWB_OGAM_RAMA_REGION_16_17_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_18_19
#define mmDWB_OGAM_RAMA_REGION_18_19_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_20_21
#define mmDWB_OGAM_RAMA_REGION_20_21_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_22_23
#define mmDWB_OGAM_RAMA_REGION_22_23_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_24_25
#define mmDWB_OGAM_RAMA_REGION_24_25_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_26_27
#define mmDWB_OGAM_RAMA_REGION_26_27_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_28_29
#define mmDWB_OGAM_RAMA_REGION_28_29_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_30_31
#define mmDWB_OGAM_RAMA_REGION_30_31_BASE_IDX
#define mmDWB_OGAM_RAMA_REGION_32_33
#define mmDWB_OGAM_RAMA_REGION_32_33_BASE_IDX
#define mmDWB_OGAM_RAMB_START_CNTL_B
#define mmDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX
#define mmDWB_OGAM_RAMB_START_CNTL_G
#define mmDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX
#define mmDWB_OGAM_RAMB_START_CNTL_R
#define mmDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX
#define mmDWB_OGAM_RAMB_END_CNTL1_B
#define mmDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX
#define mmDWB_OGAM_RAMB_END_CNTL2_B
#define mmDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX
#define mmDWB_OGAM_RAMB_END_CNTL1_G
#define mmDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX
#define mmDWB_OGAM_RAMB_END_CNTL2_G
#define mmDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX
#define mmDWB_OGAM_RAMB_END_CNTL1_R
#define mmDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX
#define mmDWB_OGAM_RAMB_END_CNTL2_R
#define mmDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX
#define mmDWB_OGAM_RAMB_OFFSET_B
#define mmDWB_OGAM_RAMB_OFFSET_B_BASE_IDX
#define mmDWB_OGAM_RAMB_OFFSET_G
#define mmDWB_OGAM_RAMB_OFFSET_G_BASE_IDX
#define mmDWB_OGAM_RAMB_OFFSET_R
#define mmDWB_OGAM_RAMB_OFFSET_R_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_0_1
#define mmDWB_OGAM_RAMB_REGION_0_1_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_2_3
#define mmDWB_OGAM_RAMB_REGION_2_3_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_4_5
#define mmDWB_OGAM_RAMB_REGION_4_5_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_6_7
#define mmDWB_OGAM_RAMB_REGION_6_7_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_8_9
#define mmDWB_OGAM_RAMB_REGION_8_9_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_10_11
#define mmDWB_OGAM_RAMB_REGION_10_11_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_12_13
#define mmDWB_OGAM_RAMB_REGION_12_13_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_14_15
#define mmDWB_OGAM_RAMB_REGION_14_15_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_16_17
#define mmDWB_OGAM_RAMB_REGION_16_17_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_18_19
#define mmDWB_OGAM_RAMB_REGION_18_19_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_20_21
#define mmDWB_OGAM_RAMB_REGION_20_21_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_22_23
#define mmDWB_OGAM_RAMB_REGION_22_23_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_24_25
#define mmDWB_OGAM_RAMB_REGION_24_25_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_26_27
#define mmDWB_OGAM_RAMB_REGION_26_27_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_28_29
#define mmDWB_OGAM_RAMB_REGION_28_29_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_30_31
#define mmDWB_OGAM_RAMB_REGION_30_31_BASE_IDX
#define mmDWB_OGAM_RAMB_REGION_32_33
#define mmDWB_OGAM_RAMB_REGION_32_33_BASE_IDX


// addressBlock: dce_dc_mpc_mpcc0_dispdec
// base address: 0x0
#define mmMPCC0_MPCC_TOP_SEL
#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX
#define mmMPCC0_MPCC_BOT_SEL
#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX
#define mmMPCC0_MPCC_OPP_ID
#define mmMPCC0_MPCC_OPP_ID_BASE_IDX
#define mmMPCC0_MPCC_CONTROL
#define mmMPCC0_MPCC_CONTROL_BASE_IDX
#define mmMPCC0_MPCC_SM_CONTROL
#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX
#define mmMPCC0_MPCC_TOP_GAIN
#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX
#define mmMPCC0_MPCC_BOT_GAIN_INSIDE
#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX
#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE
#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX
#define mmMPCC0_MPCC_BG_R_CR
#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX
#define mmMPCC0_MPCC_BG_G_Y
#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX
#define mmMPCC0_MPCC_BG_B_CB
#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX
#define mmMPCC0_MPCC_MEM_PWR_CTRL
#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX
#define mmMPCC0_MPCC_STATUS
#define mmMPCC0_MPCC_STATUS_BASE_IDX


// addressBlock: dce_dc_mpc_mpcc1_dispdec
// base address: 0x80
#define mmMPCC1_MPCC_TOP_SEL
#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX
#define mmMPCC1_MPCC_BOT_SEL
#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX
#define mmMPCC1_MPCC_OPP_ID
#define mmMPCC1_MPCC_OPP_ID_BASE_IDX
#define mmMPCC1_MPCC_CONTROL
#define mmMPCC1_MPCC_CONTROL_BASE_IDX
#define mmMPCC1_MPCC_SM_CONTROL
#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX
#define mmMPCC1_MPCC_TOP_GAIN
#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX
#define mmMPCC1_MPCC_BOT_GAIN_INSIDE
#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX
#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE
#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX
#define mmMPCC1_MPCC_BG_R_CR
#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX
#define mmMPCC1_MPCC_BG_G_Y
#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX
#define mmMPCC1_MPCC_BG_B_CB
#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX
#define mmMPCC1_MPCC_MEM_PWR_CTRL
#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX
#define mmMPCC1_MPCC_STATUS
#define mmMPCC1_MPCC_STATUS_BASE_IDX


// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
// base address: 0x0
#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL
#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX
#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT
#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX
#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE
#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX


// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
// base address: 0x200
#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL
#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX
#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT
#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX
#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE
#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX


// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
// base address: 0x0
#define mmMPC_CLOCK_CONTROL
#define mmMPC_CLOCK_CONTROL_BASE_IDX
#define mmMPC_SOFT_RESET
#define mmMPC_SOFT_RESET_BASE_IDX
#define mmMPC_CRC_CTRL
#define mmMPC_CRC_CTRL_BASE_IDX
#define mmMPC_CRC_SEL_CONTROL
#define mmMPC_CRC_SEL_CONTROL_BASE_IDX
#define mmMPC_CRC_RESULT_AR
#define mmMPC_CRC_RESULT_AR_BASE_IDX
#define mmMPC_CRC_RESULT_GB
#define mmMPC_CRC_RESULT_GB_BASE_IDX
#define mmMPC_CRC_RESULT_C
#define mmMPC_CRC_RESULT_C_BASE_IDX
#define mmMPC_PERFMON_EVENT_CTRL
#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX
#define mmMPC_BYPASS_BG_AR
#define mmMPC_BYPASS_BG_AR_BASE_IDX
#define mmMPC_BYPASS_BG_GB
#define mmMPC_BYPASS_BG_GB_BASE_IDX
#define mmMPC_HOST_READ_CONTROL
#define mmMPC_HOST_READ_CONTROL_BASE_IDX
#define mmMPC_DPP_PENDING_STATUS
#define mmMPC_DPP_PENDING_STATUS_BASE_IDX
#define mmMPC_PENDING_STATUS_MISC
#define mmMPC_PENDING_STATUS_MISC_BASE_IDX
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX
#define mmADR_CFG_VUPDATE_LOCK_SET0
#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX
#define mmADR_VUPDATE_LOCK_SET0
#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX
#define mmCFG_VUPDATE_LOCK_SET0
#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX
#define mmCUR_VUPDATE_LOCK_SET0
#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX
#define mmADR_CFG_VUPDATE_LOCK_SET1
#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX
#define mmADR_VUPDATE_LOCK_SET1
#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX
#define mmCFG_VUPDATE_LOCK_SET1
#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX
#define mmCUR_VUPDATE_LOCK_SET1
#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX
#define mmMPC_DWB0_MUX
#define mmMPC_DWB0_MUX_BASE_IDX


// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
// base address: 0x0
#define mmMPC_OUT0_MUX
#define mmMPC_OUT0_MUX_BASE_IDX
#define mmMPC_OUT0_DENORM_CONTROL
#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX
#define mmMPC_OUT0_DENORM_CLAMP_G_Y
#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX
#define mmMPC_OUT0_DENORM_CLAMP_B_CB
#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX
#define mmMPC_OUT1_MUX
#define mmMPC_OUT1_MUX_BASE_IDX
#define mmMPC_OUT1_DENORM_CONTROL
#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX
#define mmMPC_OUT1_DENORM_CLAMP_G_Y
#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX
#define mmMPC_OUT1_DENORM_CLAMP_B_CB
#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX
#define mmMPC_OUT_CSC_COEF_FORMAT
#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX
#define mmMPC_OUT0_CSC_MODE
#define mmMPC_OUT0_CSC_MODE_BASE_IDX
#define mmMPC_OUT0_CSC_C11_C12_A
#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX
#define mmMPC_OUT0_CSC_C13_C14_A
#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX
#define mmMPC_OUT0_CSC_C21_C22_A
#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX
#define mmMPC_OUT0_CSC_C23_C24_A
#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX
#define mmMPC_OUT0_CSC_C31_C32_A
#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX
#define mmMPC_OUT0_CSC_C33_C34_A
#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX
#define mmMPC_OUT0_CSC_C11_C12_B
#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX
#define mmMPC_OUT0_CSC_C13_C14_B
#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX
#define mmMPC_OUT0_CSC_C21_C22_B
#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX
#define mmMPC_OUT0_CSC_C23_C24_B
#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX
#define mmMPC_OUT0_CSC_C31_C32_B
#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX
#define mmMPC_OUT0_CSC_C33_C34_B
#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX
#define mmMPC_OUT1_CSC_MODE
#define mmMPC_OUT1_CSC_MODE_BASE_IDX
#define mmMPC_OUT1_CSC_C11_C12_A
#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX
#define mmMPC_OUT1_CSC_C13_C14_A
#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX
#define mmMPC_OUT1_CSC_C21_C22_A
#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX
#define mmMPC_OUT1_CSC_C23_C24_A
#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX
#define mmMPC_OUT1_CSC_C31_C32_A
#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX
#define mmMPC_OUT1_CSC_C33_C34_A
#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX
#define mmMPC_OUT1_CSC_C11_C12_B
#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX
#define mmMPC_OUT1_CSC_C13_C14_B
#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX
#define mmMPC_OUT1_CSC_C21_C22_B
#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX
#define mmMPC_OUT1_CSC_C23_C24_B
#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX
#define mmMPC_OUT1_CSC_C31_C32_B
#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX
#define mmMPC_OUT1_CSC_C33_C34_B
#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX


// addressBlock: dce_dc_mpc_mpc_rmu_dispdec
// base address: 0x0
#define mmMPC_RMU_CONTROL
#define mmMPC_RMU_CONTROL_BASE_IDX
#define mmMPC_RMU_MEM_PWR_CTRL
#define mmMPC_RMU_MEM_PWR_CTRL_BASE_IDX
#define mmMPC_RMU0_SHAPER_CONTROL
#define mmMPC_RMU0_SHAPER_CONTROL_BASE_IDX
#define mmMPC_RMU0_SHAPER_OFFSET_R
#define mmMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX
#define mmMPC_RMU0_SHAPER_OFFSET_G
#define mmMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX
#define mmMPC_RMU0_SHAPER_OFFSET_B
#define mmMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX
#define mmMPC_RMU0_SHAPER_SCALE_R
#define mmMPC_RMU0_SHAPER_SCALE_R_BASE_IDX
#define mmMPC_RMU0_SHAPER_SCALE_G_B
#define mmMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX
#define mmMPC_RMU0_SHAPER_LUT_INDEX
#define mmMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX
#define mmMPC_RMU0_SHAPER_LUT_DATA
#define mmMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX
#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK
#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1
#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5
#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7
#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9
#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11
#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13
#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15
#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17
#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19
#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21
#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23
#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25
#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27
#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29
#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31
#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33
#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1
#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5
#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7
#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9
#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11
#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13
#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15
#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17
#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19
#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21
#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23
#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25
#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27
#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29
#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31
#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX
#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33
#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX
#define mmMPC_RMU0_3DLUT_MODE
#define mmMPC_RMU0_3DLUT_MODE_BASE_IDX
#define mmMPC_RMU0_3DLUT_INDEX
#define mmMPC_RMU0_3DLUT_INDEX_BASE_IDX
#define mmMPC_RMU0_3DLUT_DATA
#define mmMPC_RMU0_3DLUT_DATA_BASE_IDX
#define mmMPC_RMU0_3DLUT_DATA_30BIT
#define mmMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX
#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL
#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX
#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR
#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX
// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
// base address: 0x1901c
#define mmDC_PERFMON15_PERFCOUNTER_CNTL
#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON15_PERFCOUNTER_CNTL2
#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON15_PERFCOUNTER_STATE
#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON15_PERFMON_CNTL
#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON15_PERFMON_CNTL2
#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON15_PERFMON_CVALUE_LOW
#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON15_PERFMON_HI
#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON15_PERFMON_LOW
#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
// base address: 0x2646c
#define mmAFMT2_AFMT_VBI_PACKET_CONTROL
#define mmAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX
#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2
#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX
#define mmAFMT2_AFMT_60958_0
#define mmAFMT2_AFMT_60958_0_BASE_IDX
#define mmAFMT2_AFMT_60958_1
#define mmAFMT2_AFMT_60958_1_BASE_IDX
#define mmAFMT2_AFMT_60958_2
#define mmAFMT2_AFMT_60958_2_BASE_IDX
#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL
#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX
#define mmAFMT2_AFMT_INFOFRAME_CONTROL0
#define mmAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX
#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL
#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX
#define mmAFMT2_AFMT_MEM_PWR
#define mmAFMT2_AFMT_MEM_PWR_BASE_IDX


// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
// base address: 0x264c4
#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL
#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX
#define mmVPG2_VPG_GENERIC_PACKET_DATA
#define mmVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX
#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL
#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX
#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL
#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX
#define mmVPG2_VPG_GENERIC_STATUS
#define mmVPG2_VPG_GENERIC_STATUS_BASE_IDX


// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
// base address: 0x264f0
#define mmDME2_DME_CONTROL
#define mmDME2_DME_CONTROL_BASE_IDX
#define mmDME2_DME_MEMORY_CONTROL
#define mmDME2_DME_MEMORY_CONTROL_BASE_IDX


// addressBlock: dce_dc_hpo_hpo_top_dispdec
// base address: 0x0
#define mmHPO_TOP_CLOCK_CONTROL
#define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX


// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
// base address: 0x1a698
#define mmDC_PERFMON16_PERFCOUNTER_CNTL
#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX
#define mmDC_PERFMON16_PERFCOUNTER_STATE
#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX
#define mmDC_PERFMON16_PERFMON_CNTL
#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX
#define mmDC_PERFMON16_PERFMON_CNTL2
#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX
#define mmDC_PERFMON16_PERFMON_HI
#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX
#define mmDC_PERFMON16_PERFMON_LOW
#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX


// addressBlock: dce_dc_opp_abm0_dispdec
// base address: 0x0
#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL
#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX
#define mmABM0_BL1_PWM_USER_LEVEL
#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX
#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL
#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX
#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL
#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX
#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE
#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX
#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE
#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX
#define mmABM0_BL1_PWM_ABM_CNTL
#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX
#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE
#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX
#define mmABM0_BL1_PWM_GRP2_REG_LOCK
#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX
#define mmABM0_DC_ABM1_CNTL
#define mmABM0_DC_ABM1_CNTL_BASE_IDX
#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL
#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX
#define mmABM0_DC_ABM1_ACE_THRES_12
#define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX
#define mmABM0_DC_ABM1_ACE_THRES_34
#define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX
#define mmABM0_DC_ABM1_ACE_CNTL_MISC
#define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX
#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS
#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX
#define mmABM0_DC_ABM1_HG_MISC_CTRL
#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX
#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA
#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX
#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA
#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX
#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX
#define mmABM0_DC_ABM1_LS_PIXEL_COUNT
#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX
#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX
#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX
#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX
#define mmABM0_DC_ABM1_HG_SAMPLE_RATE
#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX
#define mmABM0_DC_ABM1_LS_SAMPLE_RATE
#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX
#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX
#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX
#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX
#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX
#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_1
#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_2
#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_3
#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_4
#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_5
#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_6
#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_7
#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_8
#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_9
#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_10
#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_11
#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_12
#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_13
#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_14
#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_15
#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_16
#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_17
#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_18
#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_19
#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_20
#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_21
#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_22
#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_23
#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX
#define mmABM0_DC_ABM1_HG_RESULT_24
#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX
#define mmABM0_DC_ABM1_BL_MASTER_LOCK
#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX


// addressBlock: dce_dc_opp_abm1_dispdec
// base address: 0x104
#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL
#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX
#define mmABM1_BL1_PWM_USER_LEVEL
#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX
#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL
#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX
#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL
#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX
#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE
#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX
#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE
#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX
#define mmABM1_BL1_PWM_ABM_CNTL
#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX
#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE
#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX
#define mmABM1_BL1_PWM_GRP2_REG_LOCK
#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX
#define mmABM1_DC_ABM1_CNTL
#define mmABM1_DC_ABM1_CNTL_BASE_IDX
#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL
#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX
#define mmABM1_DC_ABM1_ACE_THRES_12
#define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX
#define mmABM1_DC_ABM1_ACE_THRES_34
#define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX
#define mmABM1_DC_ABM1_ACE_CNTL_MISC
#define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX
#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS
#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX
#define mmABM1_DC_ABM1_HG_MISC_CTRL
#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX
#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA
#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX
#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA
#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX
#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX
#define mmABM1_DC_ABM1_LS_PIXEL_COUNT
#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX
#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX
#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX
#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX
#define mmABM1_DC_ABM1_HG_SAMPLE_RATE
#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX
#define mmABM1_DC_ABM1_LS_SAMPLE_RATE
#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX
#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX
#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX
#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX
#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX
#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_1
#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_2
#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_3
#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_4
#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_5
#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_6
#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_7
#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_8
#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_9
#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_10
#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_11
#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_12
#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_13
#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_14
#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_15
#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_16
#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_17
#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_18
#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_19
#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_20
#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_21
#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_22
#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_23
#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX
#define mmABM1_DC_ABM1_HG_RESULT_24
#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX
#define mmABM1_DC_ABM1_BL_MASTER_LOCK
#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX


// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x0
#define mmCORB_WRITE_POINTER
#define mmCORB_WRITE_POINTER_BASE_IDX
#define mmCORB_READ_POINTER
#define mmCORB_READ_POINTER_BASE_IDX
#define mmCORB_CONTROL
#define mmCORB_CONTROL_BASE_IDX
#define mmCORB_STATUS
#define mmCORB_STATUS_BASE_IDX
#define mmCORB_SIZE
#define mmCORB_SIZE_BASE_IDX
#define mmRIRB_LOWER_BASE_ADDRESS
#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX
#define mmRIRB_UPPER_BASE_ADDRESS
#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX
#define mmRIRB_WRITE_POINTER
#define mmRIRB_WRITE_POINTER_BASE_IDX
#define mmRESPONSE_INTERRUPT_COUNT
#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX
#define mmRIRB_CONTROL
#define mmRIRB_CONTROL_BASE_IDX
#define mmRIRB_STATUS
#define mmRIRB_STATUS_BASE_IDX
#define mmRIRB_SIZE
#define mmRIRB_SIZE_BASE_IDX
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX
#define mmIMMEDIATE_COMMAND_STATUS
#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX
#define mmDMA_POSITION_LOWER_BASE_ADDRESS
#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX
#define mmDMA_POSITION_UPPER_BASE_ADDRESS
#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX
#define mmWALL_CLOCK_COUNTER_ALIAS
#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX


// addressBlock: dce_dc_hda_azendpoint_azdec
// base address: 0x0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX


// addressBlock: dce_dc_hda_azinputendpoint_azdec
// base address: 0x0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX



// addressBlock: vga_vgaseqind
// base address: 0x0
#define ixSEQ00
#define ixSEQ01
#define ixSEQ02
#define ixSEQ03
#define ixSEQ04


// addressBlock: vga_vgacrtind
// base address: 0x0
#define ixCRT00
#define ixCRT01
#define ixCRT02
#define ixCRT03
#define ixCRT04
#define ixCRT05
#define ixCRT06
#define ixCRT07
#define ixCRT08
#define ixCRT09
#define ixCRT0A
#define ixCRT0B
#define ixCRT0C
#define ixCRT0D
#define ixCRT0E
#define ixCRT0F
#define ixCRT10
#define ixCRT11
#define ixCRT12
#define ixCRT13
#define ixCRT14
#define ixCRT15
#define ixCRT16
#define ixCRT17
#define ixCRT18
#define ixCRT1E
#define ixCRT1F
#define ixCRT22


// addressBlock: vga_vgagrphind
// base address: 0x0
#define ixGRA00
#define ixGRA01
#define ixGRA02
#define ixGRA03
#define ixGRA04
#define ixGRA05
#define ixGRA06
#define ixGRA07
#define ixGRA08


// addressBlock: vga_vgaattrind
// base address: 0x0
#define ixATTR00
#define ixATTR01
#define ixATTR02
#define ixATTR03
#define ixATTR04
#define ixATTR05
#define ixATTR06
#define ixATTR07
#define ixATTR08
#define ixATTR09
#define ixATTR0A
#define ixATTR0B
#define ixATTR0C
#define ixATTR0D
#define ixATTR0E
#define ixATTR0F
#define ixATTR10
#define ixATTR11
#define ixATTR12
#define ixATTR13
#define ixATTR14


// addressBlock: azendpoint_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH


// addressBlock: azendpoint_descriptorind
// base address: 0x0
#define ixAUDIO_DESCRIPTOR0
#define ixAUDIO_DESCRIPTOR1
#define ixAUDIO_DESCRIPTOR2
#define ixAUDIO_DESCRIPTOR3
#define ixAUDIO_DESCRIPTOR4
#define ixAUDIO_DESCRIPTOR5
#define ixAUDIO_DESCRIPTOR6
#define ixAUDIO_DESCRIPTOR7
#define ixAUDIO_DESCRIPTOR8
#define ixAUDIO_DESCRIPTOR9
#define ixAUDIO_DESCRIPTOR10
#define ixAUDIO_DESCRIPTOR11
#define ixAUDIO_DESCRIPTOR12
#define ixAUDIO_DESCRIPTOR13


// addressBlock: azendpoint_sinkinfoind
// base address: 0x0
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1
#define ixSINK_DESCRIPTION0
#define ixSINK_DESCRIPTION1
#define ixSINK_DESCRIPTION2
#define ixSINK_DESCRIPTION3
#define ixSINK_DESCRIPTION4
#define ixSINK_DESCRIPTION5
#define ixSINK_DESCRIPTION6
#define ixSINK_DESCRIPTION7
#define ixSINK_DESCRIPTION8
#define ixSINK_DESCRIPTION9
#define ixSINK_DESCRIPTION10
#define ixSINK_DESCRIPTION11
#define ixSINK_DESCRIPTION12
#define ixSINK_DESCRIPTION13
#define ixSINK_DESCRIPTION14
#define ixSINK_DESCRIPTION15
#define ixSINK_DESCRIPTION16
#define ixSINK_DESCRIPTION17


// addressBlock: azf0controller_azinputcrc0resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC0_CHANNEL0
#define ixAZALIA_INPUT_CRC0_CHANNEL1
#define ixAZALIA_INPUT_CRC0_CHANNEL2
#define ixAZALIA_INPUT_CRC0_CHANNEL3
#define ixAZALIA_INPUT_CRC0_CHANNEL4
#define ixAZALIA_INPUT_CRC0_CHANNEL5
#define ixAZALIA_INPUT_CRC0_CHANNEL6
#define ixAZALIA_INPUT_CRC0_CHANNEL7


// addressBlock: azf0controller_azinputcrc1resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC1_CHANNEL0
#define ixAZALIA_INPUT_CRC1_CHANNEL1
#define ixAZALIA_INPUT_CRC1_CHANNEL2
#define ixAZALIA_INPUT_CRC1_CHANNEL3
#define ixAZALIA_INPUT_CRC1_CHANNEL4
#define ixAZALIA_INPUT_CRC1_CHANNEL5
#define ixAZALIA_INPUT_CRC1_CHANNEL6
#define ixAZALIA_INPUT_CRC1_CHANNEL7


// addressBlock: azf0controller_azcrc0resultind
// base address: 0x0
#define ixAZALIA_CRC0_CHANNEL0
#define ixAZALIA_CRC0_CHANNEL1
#define ixAZALIA_CRC0_CHANNEL2
#define ixAZALIA_CRC0_CHANNEL3
#define ixAZALIA_CRC0_CHANNEL4
#define ixAZALIA_CRC0_CHANNEL5
#define ixAZALIA_CRC0_CHANNEL6
#define ixAZALIA_CRC0_CHANNEL7


// addressBlock: azf0controller_azcrc1resultind
// base address: 0x0
#define ixAZALIA_CRC1_CHANNEL0
#define ixAZALIA_CRC1_CHANNEL1
#define ixAZALIA_CRC1_CHANNEL2
#define ixAZALIA_CRC1_CHANNEL3
#define ixAZALIA_CRC1_CHANNEL4
#define ixAZALIA_CRC1_CHANNEL5
#define ixAZALIA_CRC1_CHANNEL6
#define ixAZALIA_CRC1_CHANNEL7


// addressBlock: azinputendpoint_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES


// addressBlock: azroot_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES


// addressBlock: azf0stream0_streamind
// base address: 0x0
#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream1_streamind
// base address: 0x0
#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream2_streamind
// base address: 0x0
#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream3_streamind
// base address: 0x0
#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream4_streamind
// base address: 0x0
#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream5_streamind
// base address: 0x0
#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream6_streamind
// base address: 0x0
#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream7_streamind
// base address: 0x0
#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream8_streamind
// base address: 0x0
#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream9_streamind
// base address: 0x0
#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream10_streamind
// base address: 0x0
#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream11_streamind
// base address: 0x0
#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream12_streamind
// base address: 0x0
#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream13_streamind
// base address: 0x0
#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream14_streamind
// base address: 0x0
#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0stream15_streamind
// base address: 0x0
#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT


// addressBlock: azf0endpoint0_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS


// addressBlock: azf0endpoint1_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS


// addressBlock: azf0endpoint2_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS


// addressBlock: azf0endpoint3_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS


// addressBlock: azf0endpoint4_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS


// addressBlock: azf0endpoint5_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS


// addressBlock: azf0endpoint6_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS


// addressBlock: azf0endpoint7_endpointind
// base address: 0x0
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS


// addressBlock: azf0inputendpoint0_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME


// addressBlock: azf0inputendpoint1_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME


// addressBlock: azf0inputendpoint2_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME


// addressBlock: azf0inputendpoint3_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME


// addressBlock: azf0inputendpoint4_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME


// addressBlock: azf0inputendpoint5_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME


// addressBlock: azf0inputendpoint6_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME


// addressBlock: azf0inputendpoint7_inputendpointind
// base address: 0x0
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME

#endif