linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dm_services.h"

#include "core_types.h"

#include "reg_helper.h"
#include "dcn20/dcn20_dpp.h"
#include "basics/conversion.h"

#include "dcn10/dcn10_cm_common.h"

#define REG(reg) …

#define IND_REG(index) …

#define CTX …

#undef FN
#define FN(reg_name, field_name) …


static void dpp2_enable_cm_block(
		struct dpp *dpp_base)
{ … }


static bool dpp2_degamma_ram_inuse(
		struct dpp *dpp_base,
		bool *ram_a_inuse)
{ … }

static void dpp2_program_degamma_lut(
		struct dpp *dpp_base,
		const struct pwl_result_data *rgb,
		uint32_t num,
		bool is_ram_a)
{ … }

void dpp2_set_degamma_pwl(
		struct dpp *dpp_base,
		const struct pwl_params *params)
{ … }

void dpp2_set_degamma(
		struct dpp *dpp_base,
		enum ipp_degamma_mode mode)
{ … }

static void program_gamut_remap(
		struct dcn20_dpp *dpp,
		const uint16_t *regval,
		enum dcn20_gamut_remap_select select)
{ … }

void dpp2_cm_set_gamut_remap(
	struct dpp *dpp_base,
	const struct dpp_grph_csc_adjustment *adjust)
{ … }

static void read_gamut_remap(struct dcn20_dpp *dpp,
			     uint16_t *regval,
			     enum dcn20_gamut_remap_select *select)
{ … }

void dpp2_cm_get_gamut_remap(struct dpp *dpp_base,
			     struct dpp_grph_csc_adjustment *adjust)
{ … }

void dpp2_program_input_csc(
		struct dpp *dpp_base,
		enum dc_color_space color_space,
		enum dcn20_input_csc_select input_select,
		const struct out_csc_color_matrix *tbl_entry)
{ … }

static void dpp20_power_on_blnd_lut(
	struct dpp *dpp_base,
	bool power_on)
{ … }

static void dpp20_configure_blnd_lut(
		struct dpp *dpp_base,
		bool is_ram_a)
{ … }

static void dpp20_program_blnd_pwl(
		struct dpp *dpp_base,
		const struct pwl_result_data *rgb,
		uint32_t num)
{ … }

static void dcn20_dpp_cm_get_reg_field(
		struct dcn20_dpp *dpp,
		struct xfer_func_reg *reg)
{ … }

/*program blnd lut RAM A*/
static void dpp20_program_blnd_luta_settings(
		struct dpp *dpp_base,
		const struct pwl_params *params)
{ … }

/*program blnd lut RAM B*/
static void dpp20_program_blnd_lutb_settings(
		struct dpp *dpp_base,
		const struct pwl_params *params)
{ … }

static enum dc_lut_mode dpp20_get_blndgam_current(struct dpp *dpp_base)
{ … }

bool dpp20_program_blnd_lut(
	struct dpp *dpp_base, const struct pwl_params *params)
{ … }


static void dpp20_program_shaper_lut(
		struct dpp *dpp_base,
		const struct pwl_result_data *rgb,
		uint32_t num)
{ … }

static enum dc_lut_mode dpp20_get_shaper_current(struct dpp *dpp_base)
{ … }

static void dpp20_configure_shaper_lut(
		struct dpp *dpp_base,
		bool is_ram_a)
{ … }

/*program shaper RAM A*/

static void dpp20_program_shaper_luta_settings(
		struct dpp *dpp_base,
		const struct pwl_params *params)
{ … }

/*program shaper RAM B*/
static void dpp20_program_shaper_lutb_settings(
		struct dpp *dpp_base,
		const struct pwl_params *params)
{ … }


bool dpp20_program_shaper(
		struct dpp *dpp_base,
		const struct pwl_params *params)
{ … }

static enum dc_lut_mode get3dlut_config(
			struct dpp *dpp_base,
			bool *is_17x17x17,
			bool *is_12bits_color_channel)
{ … }
/*
 * select ramA or ramB, or bypass
 * select color channel size 10 or 12 bits
 * select 3dlut size 17x17x17 or 9x9x9
 */
static void dpp20_set_3dlut_mode(
		struct dpp *dpp_base,
		enum dc_lut_mode mode,
		bool is_color_channel_12bits,
		bool is_lut_size17x17x17)
{ … }

static void dpp20_select_3dlut_ram(
		struct dpp *dpp_base,
		enum dc_lut_mode mode,
		bool is_color_channel_12bits)
{ … }



static void dpp20_set3dlut_ram12(
		struct dpp *dpp_base,
		const struct dc_rgb *lut,
		uint32_t entries)
{ … }

/*
 * load selected lut with 10 bits color channels
 */
static void dpp20_set3dlut_ram10(
		struct dpp *dpp_base,
		const struct dc_rgb *lut,
		uint32_t entries)
{ … }


static void dpp20_select_3dlut_ram_mask(
		struct dpp *dpp_base,
		uint32_t ram_selection_mask)
{ … }

bool dpp20_program_3dlut(
		struct dpp *dpp_base,
		const struct tetrahedral_params *params)
{ … }

void dpp2_set_hdr_multiplier(
		struct dpp *dpp_base,
		uint32_t multiplier)
{ … }