linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

/*
 * Copyright 2020 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dm_services.h"
#include "core_types.h"
#include "reg_helper.h"
#include "dcn30/dcn30_dpp.h"
#include "basics/conversion.h"
#include "dcn30/dcn30_cm_common.h"

#define REG(reg) …

#define CTX …

#undef FN
#define FN(reg_name, field_name) …


void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
{ … }

/*program post scaler scs block in dpp CM*/
void dpp3_program_post_csc(
		struct dpp *dpp_base,
		enum dc_color_space color_space,
		enum dcn10_input_csc_select input_select,
		const struct out_csc_color_matrix *tbl_entry)
{ … }


/*CNVC degam unit has read only LUTs*/
void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)
{ … }

void dpp3_cnv_setup (
		struct dpp *dpp_base,
		enum surface_pixel_format format,
		enum expansion_mode mode,
		struct dc_csc_transform input_csc_color_matrix,
		enum dc_color_space input_color_space,
		struct cnv_alpha_2bit_lut *alpha_2bit_lut)
{ … }

#define IDENTITY_RATIO(ratio) …

void dpp3_set_cursor_attributes(
		struct dpp *dpp_base,
		struct dc_cursor_attributes *cursor_attributes)
{ … }


bool dpp3_get_optimal_number_of_taps(
		struct dpp *dpp,
		struct scaler_data *scl_data,
		const struct scaling_taps *in_taps)
{ … }

static void dpp3_deferred_update(struct dpp *dpp_base)
{ … }

static void dpp3_power_on_blnd_lut(
	struct dpp *dpp_base,
	bool power_on)
{ … }

static void dpp3_power_on_hdr3dlut(
	struct dpp *dpp_base,
	bool power_on)
{ … }

static void dpp3_power_on_shaper(
	struct dpp *dpp_base,
	bool power_on)
{ … }

static void dpp3_configure_blnd_lut(
		struct dpp *dpp_base,
		bool is_ram_a)
{ … }

static void dpp3_program_blnd_pwl(
		struct dpp *dpp_base,
		const struct pwl_result_data *rgb,
		uint32_t num)
{ … }

static void dcn3_dpp_cm_get_reg_field(
		struct dcn3_dpp *dpp,
		struct dcn3_xfer_func_reg *reg)
{ … }

/*program blnd lut RAM A*/
static void dpp3_program_blnd_luta_settings(
		struct dpp *dpp_base,
		const struct pwl_params *params)
{ … }

/*program blnd lut RAM B*/
static void dpp3_program_blnd_lutb_settings(
		struct dpp *dpp_base,
		const struct pwl_params *params)
{ … }

static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)
{ … }

static bool dpp3_program_blnd_lut(struct dpp *dpp_base,
				  const struct pwl_params *params)
{ … }


static void dpp3_program_shaper_lut(
		struct dpp *dpp_base,
		const struct pwl_result_data *rgb,
		uint32_t num)
{ … }

static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)
{ … }

static void dpp3_configure_shaper_lut(
		struct dpp *dpp_base,
		bool is_ram_a)
{ … }

/*program shaper RAM A*/

static void dpp3_program_shaper_luta_settings(
		struct dpp *dpp_base,
		const struct pwl_params *params)
{ … }

/*program shaper RAM B*/
static void dpp3_program_shaper_lutb_settings(
		struct dpp *dpp_base,
		const struct pwl_params *params)
{ … }


static bool dpp3_program_shaper(struct dpp *dpp_base,
				const struct pwl_params *params)
{ … }

static enum dc_lut_mode get3dlut_config(
			struct dpp *dpp_base,
			bool *is_17x17x17,
			bool *is_12bits_color_channel)
{ … }
/*
 * select ramA or ramB, or bypass
 * select color channel size 10 or 12 bits
 * select 3dlut size 17x17x17 or 9x9x9
 */
static void dpp3_set_3dlut_mode(
		struct dpp *dpp_base,
		enum dc_lut_mode mode,
		bool is_color_channel_12bits,
		bool is_lut_size17x17x17)
{ … }

static void dpp3_select_3dlut_ram(
		struct dpp *dpp_base,
		enum dc_lut_mode mode,
		bool is_color_channel_12bits)
{ … }



static void dpp3_set3dlut_ram12(
		struct dpp *dpp_base,
		const struct dc_rgb *lut,
		uint32_t entries)
{ … }

/*
 * load selected lut with 10 bits color channels
 */
static void dpp3_set3dlut_ram10(
		struct dpp *dpp_base,
		const struct dc_rgb *lut,
		uint32_t entries)
{ … }


static void dpp3_select_3dlut_ram_mask(
		struct dpp *dpp_base,
		uint32_t ram_selection_mask)
{ … }

static bool dpp3_program_3dlut(struct dpp *dpp_base,
			       const struct tetrahedral_params *params)
{ … }
static struct dpp_funcs dcn30_dpp_funcs = …;


static struct dpp_caps dcn30_dpp_cap = …;

bool dpp3_construct(
	struct dcn3_dpp *dpp,
	struct dc_context *ctx,
	uint32_t inst,
	const struct dcn3_dpp_registers *tf_regs,
	const struct dcn3_dpp_shift *tf_shift,
	const struct dcn3_dpp_mask *tf_mask)
{ … }